Revision 5e755519 target-mips/cpu.h

b/target-mips/cpu.h
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#define MIPS_HFLAG_TMASK  0x007F
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#define MIPS_HFLAG_MODE   0x001F /* execution modes                    */
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#define MIPS_HFLAG_UM     0x0001 /* user mode                          */
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#define MIPS_HFLAG_DM     0x0008 /* Debug mode                         */
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#define MIPS_HFLAG_SM     0x0010 /* Supervisor mode                    */
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#define MIPS_HFLAG_64     0x0020 /* 64-bit instructions enabled        */
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#define MIPS_HFLAG_DM     0x0002 /* Debug mode                         */
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#define MIPS_HFLAG_SM     0x0004 /* Supervisor mode                    */
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#define MIPS_HFLAG_64     0x0008 /* 64-bit instructions enabled        */
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#define MIPS_HFLAG_FPU    0x0010 /* FPU enabled                        */
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#define MIPS_HFLAG_F64    0x0020 /* 64-bit FPU enabled                 */
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#define MIPS_HFLAG_RE     0x0040 /* Reversed endianness                */
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    /* If translation is interrupted between the branch instruction and
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     * the delay slot, record what type of branch it is so that we can

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