Revision 5e755519 target-mips/op.c
b/target-mips/op.c | ||
---|---|---|
1349 | 1349 |
uint32_t val, old; |
1350 | 1350 |
uint32_t mask = env->Status_rw_bitmask; |
1351 | 1351 |
|
1352 |
/* No reverse endianness, no MDMX/DSP, no 64bit ops |
|
1353 |
implemented. */ |
|
1352 |
/* No reverse endianness, no MDMX/DSP implemented. */ |
|
1354 | 1353 |
val = T0 & mask; |
1355 | 1354 |
old = env->CP0_Status; |
1356 | 1355 |
if (!(val & (1 << CP0St_EXL)) && |
... | ... | |
1364 | 1363 |
!(val & (1 << CP0St_UX))) |
1365 | 1364 |
env->hflags &= ~MIPS_HFLAG_64; |
1366 | 1365 |
#endif |
1366 |
if (val & (1 << CP0St_CU1)) |
|
1367 |
env->hflags |= MIPS_HFLAG_FPU; |
|
1368 |
else |
|
1369 |
env->hflags &= ~MIPS_HFLAG_FPU; |
|
1370 |
if (val & (1 << CP0St_FR)) |
|
1371 |
env->hflags |= MIPS_HFLAG_F64; |
|
1372 |
else |
|
1373 |
env->hflags &= ~MIPS_HFLAG_F64; |
|
1367 | 1374 |
env->CP0_Status = (env->CP0_Status & ~mask) | val; |
1368 | 1375 |
if (loglevel & CPU_LOG_EXEC) |
1369 | 1376 |
CALL_FROM_TB2(do_mtc0_status_debug, old, val); |
... | ... | |
1606 | 1613 |
RETURN(); |
1607 | 1614 |
} |
1608 | 1615 |
|
1609 |
void op_cp1_enabled(void) |
|
1610 |
{ |
|
1611 |
if (!(env->CP0_Status & (1 << CP0St_CU1))) { |
|
1612 |
CALL_FROM_TB2(do_raise_exception_err, EXCP_CpU, 1); |
|
1613 |
} |
|
1614 |
RETURN(); |
|
1615 |
} |
|
1616 |
|
|
1617 |
void op_cp1_64bitmode(void) |
|
1618 |
{ |
|
1619 |
if (!(env->CP0_Status & (1 << CP0St_FR))) { |
|
1620 |
CALL_FROM_TB1(do_raise_exception, EXCP_RI); |
|
1621 |
} |
|
1622 |
RETURN(); |
|
1623 |
} |
|
1624 |
|
|
1625 |
/* |
|
1626 |
* Verify if floating point register is valid; an operation is not defined |
|
1627 |
* if bit 0 of any register specification is set and the FR bit in the |
|
1628 |
* Status register equals zero, since the register numbers specify an |
|
1629 |
* even-odd pair of adjacent coprocessor general registers. When the FR bit |
|
1630 |
* in the Status register equals one, both even and odd register numbers |
|
1631 |
* are valid. This limitation exists only for 64 bit wide (d,l,ps) registers. |
|
1632 |
* |
|
1633 |
* Multiple 64 bit wide registers can be checked by calling |
|
1634 |
* gen_op_cp1_registers(freg1 | freg2 | ... | fregN); |
|
1635 |
*/ |
|
1636 |
void op_cp1_registers(void) |
|
1637 |
{ |
|
1638 |
if (!(env->CP0_Status & (1 << CP0St_FR)) && (PARAM1 & 1)) { |
|
1639 |
CALL_FROM_TB1(do_raise_exception, EXCP_RI); |
|
1640 |
} |
|
1641 |
RETURN(); |
|
1642 |
} |
|
1643 |
|
|
1644 | 1616 |
void op_cfc1 (void) |
1645 | 1617 |
{ |
1646 | 1618 |
switch (T1) { |
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