root / hw / etraxfs_timer.c @ 5ef98b47
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1 | 83fa1010 | ths | /*
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2 | e62b5b13 | edgar_igl | * QEMU ETRAX Timers
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3 | 83fa1010 | ths | *
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4 | 83fa1010 | ths | * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
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5 | 83fa1010 | ths | *
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6 | 83fa1010 | ths | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 83fa1010 | ths | * of this software and associated documentation files (the "Software"), to deal
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8 | 83fa1010 | ths | * in the Software without restriction, including without limitation the rights
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9 | 83fa1010 | ths | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 83fa1010 | ths | * copies of the Software, and to permit persons to whom the Software is
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11 | 83fa1010 | ths | * furnished to do so, subject to the following conditions:
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12 | 83fa1010 | ths | *
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13 | 83fa1010 | ths | * The above copyright notice and this permission notice shall be included in
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14 | 83fa1010 | ths | * all copies or substantial portions of the Software.
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15 | 83fa1010 | ths | *
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16 | 83fa1010 | ths | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 83fa1010 | ths | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 83fa1010 | ths | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 83fa1010 | ths | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 83fa1010 | ths | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 83fa1010 | ths | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 83fa1010 | ths | * THE SOFTWARE.
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23 | 83fa1010 | ths | */
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24 | 83fa1010 | ths | #include <stdio.h> |
25 | 83fa1010 | ths | #include <sys/time.h> |
26 | 87ecb68b | pbrook | #include "hw.h" |
27 | 5439779e | edgar_igl | #include "sysemu.h" |
28 | 87ecb68b | pbrook | #include "qemu-timer.h" |
29 | 83fa1010 | ths | |
30 | bbaf29c7 | edgar_igl | #define D(x)
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31 | bbaf29c7 | edgar_igl | |
32 | ca87d03b | edgar_igl | #define RW_TMR0_DIV 0x00 |
33 | ca87d03b | edgar_igl | #define R_TMR0_DATA 0x04 |
34 | ca87d03b | edgar_igl | #define RW_TMR0_CTRL 0x08 |
35 | ca87d03b | edgar_igl | #define RW_TMR1_DIV 0x10 |
36 | ca87d03b | edgar_igl | #define R_TMR1_DATA 0x14 |
37 | ca87d03b | edgar_igl | #define RW_TMR1_CTRL 0x18 |
38 | ca87d03b | edgar_igl | #define R_TIME 0x38 |
39 | ca87d03b | edgar_igl | #define RW_WD_CTRL 0x40 |
40 | 5439779e | edgar_igl | #define R_WD_STAT 0x44 |
41 | ca87d03b | edgar_igl | #define RW_INTR_MASK 0x48 |
42 | ca87d03b | edgar_igl | #define RW_ACK_INTR 0x4c |
43 | ca87d03b | edgar_igl | #define R_INTR 0x50 |
44 | ca87d03b | edgar_igl | #define R_MASKED_INTR 0x54 |
45 | 83fa1010 | ths | |
46 | 83fa1010 | ths | struct fs_timer_t {
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47 | ca87d03b | edgar_igl | CPUState *env; |
48 | ca87d03b | edgar_igl | qemu_irq *irq; |
49 | 5ef98b47 | edgar_igl | qemu_irq *nmi; |
50 | ca87d03b | edgar_igl | target_phys_addr_t base; |
51 | ca87d03b | edgar_igl | |
52 | 5439779e | edgar_igl | QEMUBH *bh_t0; |
53 | 5439779e | edgar_igl | QEMUBH *bh_t1; |
54 | 5439779e | edgar_igl | QEMUBH *bh_wd; |
55 | 5439779e | edgar_igl | ptimer_state *ptimer_t0; |
56 | 5439779e | edgar_igl | ptimer_state *ptimer_t1; |
57 | 5439779e | edgar_igl | ptimer_state *ptimer_wd; |
58 | bbaf29c7 | edgar_igl | struct timeval last;
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59 | e62b5b13 | edgar_igl | |
60 | 5ef98b47 | edgar_igl | int wd_hits;
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61 | 5ef98b47 | edgar_igl | |
62 | 60237223 | edgar_igl | /* Control registers. */
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63 | 60237223 | edgar_igl | uint32_t rw_tmr0_div; |
64 | 60237223 | edgar_igl | uint32_t r_tmr0_data; |
65 | 60237223 | edgar_igl | uint32_t rw_tmr0_ctrl; |
66 | 60237223 | edgar_igl | |
67 | 60237223 | edgar_igl | uint32_t rw_tmr1_div; |
68 | 60237223 | edgar_igl | uint32_t r_tmr1_data; |
69 | 60237223 | edgar_igl | uint32_t rw_tmr1_ctrl; |
70 | 60237223 | edgar_igl | |
71 | 5439779e | edgar_igl | uint32_t rw_wd_ctrl; |
72 | 5439779e | edgar_igl | |
73 | e62b5b13 | edgar_igl | uint32_t rw_intr_mask; |
74 | e62b5b13 | edgar_igl | uint32_t rw_ack_intr; |
75 | e62b5b13 | edgar_igl | uint32_t r_intr; |
76 | 60237223 | edgar_igl | uint32_t r_masked_intr; |
77 | 83fa1010 | ths | }; |
78 | 83fa1010 | ths | |
79 | ca87d03b | edgar_igl | static uint32_t timer_rinvalid (void *opaque, target_phys_addr_t addr) |
80 | 83fa1010 | ths | { |
81 | ca87d03b | edgar_igl | struct fs_timer_t *t = opaque;
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82 | ca87d03b | edgar_igl | CPUState *env = t->env; |
83 | ca87d03b | edgar_igl | cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n",
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84 | ca87d03b | edgar_igl | addr, env->pc); |
85 | ca87d03b | edgar_igl | return 0; |
86 | 83fa1010 | ths | } |
87 | 83fa1010 | ths | |
88 | 83fa1010 | ths | static uint32_t timer_readl (void *opaque, target_phys_addr_t addr) |
89 | 83fa1010 | ths | { |
90 | ca87d03b | edgar_igl | struct fs_timer_t *t = opaque;
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91 | ca87d03b | edgar_igl | D(CPUState *env = t->env); |
92 | 83fa1010 | ths | uint32_t r = 0;
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93 | 83fa1010 | ths | |
94 | ca87d03b | edgar_igl | /* Make addr relative to this instances base. */
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95 | ca87d03b | edgar_igl | addr -= t->base; |
96 | 83fa1010 | ths | switch (addr) {
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97 | 83fa1010 | ths | case R_TMR0_DATA:
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98 | 83fa1010 | ths | break;
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99 | 83fa1010 | ths | case R_TMR1_DATA:
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100 | bbaf29c7 | edgar_igl | D(printf ("R_TMR1_DATA\n"));
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101 | 83fa1010 | ths | break;
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102 | 83fa1010 | ths | case R_TIME:
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103 | 60237223 | edgar_igl | r = qemu_get_clock(vm_clock) * 10;
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104 | 83fa1010 | ths | break;
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105 | 83fa1010 | ths | case RW_INTR_MASK:
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106 | ca87d03b | edgar_igl | r = t->rw_intr_mask; |
107 | 83fa1010 | ths | break;
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108 | 83fa1010 | ths | case R_MASKED_INTR:
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109 | ca87d03b | edgar_igl | r = t->r_intr & t->rw_intr_mask; |
110 | 83fa1010 | ths | break;
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111 | 83fa1010 | ths | default:
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112 | e62b5b13 | edgar_igl | D(printf ("%s %x p=%x\n", __func__, addr, env->pc));
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113 | 83fa1010 | ths | break;
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114 | 83fa1010 | ths | } |
115 | 83fa1010 | ths | return r;
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116 | 83fa1010 | ths | } |
117 | 83fa1010 | ths | |
118 | 83fa1010 | ths | static void |
119 | ca87d03b | edgar_igl | timer_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
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120 | 83fa1010 | ths | { |
121 | ca87d03b | edgar_igl | struct fs_timer_t *t = opaque;
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122 | ca87d03b | edgar_igl | CPUState *env = t->env; |
123 | ca87d03b | edgar_igl | cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n",
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124 | ca87d03b | edgar_igl | addr, env->pc); |
125 | 83fa1010 | ths | } |
126 | 83fa1010 | ths | |
127 | f0b86b14 | edgar_igl | #define TIMER_SLOWDOWN 1 |
128 | 5439779e | edgar_igl | static void update_ctrl(struct fs_timer_t *t, int tnum) |
129 | 83fa1010 | ths | { |
130 | 60237223 | edgar_igl | unsigned int op; |
131 | 60237223 | edgar_igl | unsigned int freq; |
132 | 60237223 | edgar_igl | unsigned int freq_hz; |
133 | 60237223 | edgar_igl | unsigned int div; |
134 | 5439779e | edgar_igl | uint32_t ctrl; |
135 | 5ef98b47 | edgar_igl | |
136 | 5439779e | edgar_igl | ptimer_state *timer; |
137 | 5439779e | edgar_igl | |
138 | 5439779e | edgar_igl | if (tnum == 0) { |
139 | 5439779e | edgar_igl | ctrl = t->rw_tmr0_ctrl; |
140 | 5439779e | edgar_igl | div = t->rw_tmr0_div; |
141 | 5439779e | edgar_igl | timer = t->ptimer_t0; |
142 | 5439779e | edgar_igl | } else {
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143 | 5439779e | edgar_igl | ctrl = t->rw_tmr1_ctrl; |
144 | 5439779e | edgar_igl | div = t->rw_tmr1_div; |
145 | 5439779e | edgar_igl | timer = t->ptimer_t1; |
146 | 5439779e | edgar_igl | } |
147 | 5439779e | edgar_igl | |
148 | 83fa1010 | ths | |
149 | 5439779e | edgar_igl | op = ctrl & 3;
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150 | 5439779e | edgar_igl | freq = ctrl >> 2;
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151 | 83fa1010 | ths | freq_hz = 32000000;
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152 | 83fa1010 | ths | |
153 | 83fa1010 | ths | switch (freq)
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154 | 83fa1010 | ths | { |
155 | 83fa1010 | ths | case 0: |
156 | 83fa1010 | ths | case 1: |
157 | e62b5b13 | edgar_igl | D(printf ("extern or disabled timer clock?\n"));
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158 | 83fa1010 | ths | break;
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159 | 83fa1010 | ths | case 4: freq_hz = 29493000; break; |
160 | 83fa1010 | ths | case 5: freq_hz = 32000000; break; |
161 | 83fa1010 | ths | case 6: freq_hz = 32768000; break; |
162 | 5439779e | edgar_igl | case 7: freq_hz = 100001000; break; |
163 | 83fa1010 | ths | default:
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164 | 83fa1010 | ths | abort(); |
165 | 83fa1010 | ths | break;
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166 | 83fa1010 | ths | } |
167 | 83fa1010 | ths | |
168 | 5439779e | edgar_igl | D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
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169 | 5439779e | edgar_igl | div = div * TIMER_SLOWDOWN; |
170 | 5ef98b47 | edgar_igl | div >>= 10;
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171 | 5ef98b47 | edgar_igl | freq_hz >>= 10;
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172 | 5439779e | edgar_igl | ptimer_set_freq(timer, freq_hz); |
173 | 5439779e | edgar_igl | ptimer_set_limit(timer, div, 0);
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174 | 83fa1010 | ths | |
175 | 83fa1010 | ths | switch (op)
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176 | 83fa1010 | ths | { |
177 | 83fa1010 | ths | case 0: |
178 | 60237223 | edgar_igl | /* Load. */
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179 | 5439779e | edgar_igl | ptimer_set_limit(timer, div, 1);
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180 | 83fa1010 | ths | break;
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181 | 83fa1010 | ths | case 1: |
182 | 60237223 | edgar_igl | /* Hold. */
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183 | 5439779e | edgar_igl | ptimer_stop(timer); |
184 | 83fa1010 | ths | break;
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185 | 83fa1010 | ths | case 2: |
186 | 60237223 | edgar_igl | /* Run. */
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187 | 5439779e | edgar_igl | ptimer_run(timer, 0);
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188 | 83fa1010 | ths | break;
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189 | 83fa1010 | ths | default:
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190 | 83fa1010 | ths | abort(); |
191 | 83fa1010 | ths | break;
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192 | 83fa1010 | ths | } |
193 | 83fa1010 | ths | } |
194 | 83fa1010 | ths | |
195 | 60237223 | edgar_igl | static void timer_update_irq(struct fs_timer_t *t) |
196 | 83fa1010 | ths | { |
197 | 60237223 | edgar_igl | t->r_intr &= ~(t->rw_ack_intr); |
198 | 60237223 | edgar_igl | t->r_masked_intr = t->r_intr & t->rw_intr_mask; |
199 | 60237223 | edgar_igl | |
200 | 60237223 | edgar_igl | D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
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201 | eb173de6 | edgar_igl | if (t->r_masked_intr)
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202 | 60237223 | edgar_igl | qemu_irq_raise(t->irq[0]);
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203 | 60237223 | edgar_igl | else
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204 | bbaf29c7 | edgar_igl | qemu_irq_lower(t->irq[0]);
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205 | 83fa1010 | ths | } |
206 | 83fa1010 | ths | |
207 | 5439779e | edgar_igl | static void timer0_hit(void *opaque) |
208 | 60237223 | edgar_igl | { |
209 | 63c1d925 | edgar_igl | struct fs_timer_t *t = opaque;
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210 | 60237223 | edgar_igl | t->r_intr |= 1;
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211 | 60237223 | edgar_igl | timer_update_irq(t); |
212 | 60237223 | edgar_igl | } |
213 | 60237223 | edgar_igl | |
214 | 5439779e | edgar_igl | static void timer1_hit(void *opaque) |
215 | 5439779e | edgar_igl | { |
216 | 5439779e | edgar_igl | struct fs_timer_t *t = opaque;
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217 | 5439779e | edgar_igl | t->r_intr |= 2;
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218 | 5439779e | edgar_igl | timer_update_irq(t); |
219 | 5439779e | edgar_igl | } |
220 | 5439779e | edgar_igl | |
221 | 5439779e | edgar_igl | static void watchdog_hit(void *opaque) |
222 | 5439779e | edgar_igl | { |
223 | 5ef98b47 | edgar_igl | struct fs_timer_t *t = opaque;
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224 | 5ef98b47 | edgar_igl | if (t->wd_hits == 0) { |
225 | 5ef98b47 | edgar_igl | /* real hw gives a single tick before reseting but we are
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226 | 5ef98b47 | edgar_igl | a bit friendlier to compensate for our slower execution. */
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227 | 5ef98b47 | edgar_igl | ptimer_set_count(t->ptimer_wd, 10);
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228 | 5ef98b47 | edgar_igl | ptimer_run(t->ptimer_wd, 1);
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229 | 5ef98b47 | edgar_igl | qemu_irq_raise(t->nmi[0]);
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230 | 5ef98b47 | edgar_igl | } |
231 | 5ef98b47 | edgar_igl | else
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232 | 5ef98b47 | edgar_igl | qemu_system_reset_request(); |
233 | 5ef98b47 | edgar_igl | |
234 | 5ef98b47 | edgar_igl | t->wd_hits++; |
235 | 5439779e | edgar_igl | } |
236 | 5439779e | edgar_igl | |
237 | 5439779e | edgar_igl | static inline void timer_watchdog_update(struct fs_timer_t *t, uint32_t value) |
238 | 5439779e | edgar_igl | { |
239 | 5439779e | edgar_igl | unsigned int wd_en = t->rw_wd_ctrl & (1 << 8); |
240 | 5439779e | edgar_igl | unsigned int wd_key = t->rw_wd_ctrl >> 9; |
241 | 5439779e | edgar_igl | unsigned int wd_cnt = t->rw_wd_ctrl & 511; |
242 | 5439779e | edgar_igl | unsigned int new_key = value >> 9 & ((1 << 7) - 1); |
243 | 5439779e | edgar_igl | unsigned int new_cmd = (value >> 8) & 1; |
244 | 5439779e | edgar_igl | |
245 | 5439779e | edgar_igl | /* If the watchdog is enabled, they written key must match the
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246 | 5439779e | edgar_igl | complement of the previous. */
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247 | 5439779e | edgar_igl | wd_key = ~wd_key & ((1 << 7) - 1); |
248 | 5439779e | edgar_igl | |
249 | 5439779e | edgar_igl | if (wd_en && wd_key != new_key)
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250 | 5439779e | edgar_igl | return;
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251 | 5439779e | edgar_igl | |
252 | 5439779e | edgar_igl | D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n",
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253 | 96768ff7 | edgar_igl | wd_en, new_key, wd_key, new_cmd, wd_cnt)); |
254 | 5439779e | edgar_igl | |
255 | 5ef98b47 | edgar_igl | if (t->wd_hits)
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256 | 5ef98b47 | edgar_igl | qemu_irq_lower(t->nmi[0]);
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257 | 5ef98b47 | edgar_igl | |
258 | 5ef98b47 | edgar_igl | t->wd_hits = 0;
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259 | 5ef98b47 | edgar_igl | |
260 | 5439779e | edgar_igl | ptimer_set_freq(t->ptimer_wd, 760);
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261 | 5439779e | edgar_igl | if (wd_cnt == 0) |
262 | 5439779e | edgar_igl | wd_cnt = 256;
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263 | 5439779e | edgar_igl | ptimer_set_count(t->ptimer_wd, wd_cnt); |
264 | 5439779e | edgar_igl | if (new_cmd)
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265 | 5439779e | edgar_igl | ptimer_run(t->ptimer_wd, 1);
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266 | 5439779e | edgar_igl | else
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267 | 5439779e | edgar_igl | ptimer_stop(t->ptimer_wd); |
268 | 5439779e | edgar_igl | |
269 | 5439779e | edgar_igl | t->rw_wd_ctrl = value; |
270 | 5439779e | edgar_igl | } |
271 | 5439779e | edgar_igl | |
272 | 83fa1010 | ths | static void |
273 | 83fa1010 | ths | timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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274 | 83fa1010 | ths | { |
275 | ca87d03b | edgar_igl | struct fs_timer_t *t = opaque;
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276 | ca87d03b | edgar_igl | CPUState *env = t->env; |
277 | bbaf29c7 | edgar_igl | |
278 | ca87d03b | edgar_igl | /* Make addr relative to this instances base. */
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279 | ca87d03b | edgar_igl | addr -= t->base; |
280 | 83fa1010 | ths | switch (addr)
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281 | 83fa1010 | ths | { |
282 | 83fa1010 | ths | case RW_TMR0_DIV:
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283 | 60237223 | edgar_igl | t->rw_tmr0_div = value; |
284 | 83fa1010 | ths | break;
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285 | 83fa1010 | ths | case RW_TMR0_CTRL:
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286 | bbaf29c7 | edgar_igl | D(printf ("RW_TMR0_CTRL=%x\n", value));
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287 | 60237223 | edgar_igl | t->rw_tmr0_ctrl = value; |
288 | 5439779e | edgar_igl | update_ctrl(t, 0);
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289 | 83fa1010 | ths | break;
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290 | 83fa1010 | ths | case RW_TMR1_DIV:
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291 | 60237223 | edgar_igl | t->rw_tmr1_div = value; |
292 | 83fa1010 | ths | break;
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293 | 83fa1010 | ths | case RW_TMR1_CTRL:
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294 | bbaf29c7 | edgar_igl | D(printf ("RW_TMR1_CTRL=%x\n", value));
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295 | 5439779e | edgar_igl | t->rw_tmr1_ctrl = value; |
296 | 5439779e | edgar_igl | update_ctrl(t, 1);
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297 | 83fa1010 | ths | break;
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298 | 83fa1010 | ths | case RW_INTR_MASK:
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299 | bbaf29c7 | edgar_igl | D(printf ("RW_INTR_MASK=%x\n", value));
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300 | ca87d03b | edgar_igl | t->rw_intr_mask = value; |
301 | 60237223 | edgar_igl | timer_update_irq(t); |
302 | e62b5b13 | edgar_igl | break;
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303 | e62b5b13 | edgar_igl | case RW_WD_CTRL:
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304 | 5439779e | edgar_igl | timer_watchdog_update(t, value); |
305 | 83fa1010 | ths | break;
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306 | 83fa1010 | ths | case RW_ACK_INTR:
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307 | 60237223 | edgar_igl | t->rw_ack_intr = value; |
308 | 60237223 | edgar_igl | timer_update_irq(t); |
309 | 60237223 | edgar_igl | t->rw_ack_intr = 0;
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310 | 83fa1010 | ths | break;
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311 | 83fa1010 | ths | default:
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312 | 83fa1010 | ths | printf ("%s %x %x pc=%x\n",
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313 | 83fa1010 | ths | __func__, addr, value, env->pc); |
314 | 83fa1010 | ths | break;
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315 | 83fa1010 | ths | } |
316 | 83fa1010 | ths | } |
317 | 83fa1010 | ths | |
318 | 83fa1010 | ths | static CPUReadMemoryFunc *timer_read[] = {
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319 | 5439779e | edgar_igl | &timer_rinvalid, |
320 | 5439779e | edgar_igl | &timer_rinvalid, |
321 | 5439779e | edgar_igl | &timer_readl, |
322 | 83fa1010 | ths | }; |
323 | 83fa1010 | ths | |
324 | 83fa1010 | ths | static CPUWriteMemoryFunc *timer_write[] = {
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325 | 5439779e | edgar_igl | &timer_winvalid, |
326 | 5439779e | edgar_igl | &timer_winvalid, |
327 | 5439779e | edgar_igl | &timer_writel, |
328 | 83fa1010 | ths | }; |
329 | 83fa1010 | ths | |
330 | 5439779e | edgar_igl | static void etraxfs_timer_reset(void *opaque) |
331 | 5439779e | edgar_igl | { |
332 | 5439779e | edgar_igl | struct fs_timer_t *t = opaque;
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333 | 5439779e | edgar_igl | |
334 | 5439779e | edgar_igl | ptimer_stop(t->ptimer_t0); |
335 | 5439779e | edgar_igl | ptimer_stop(t->ptimer_t1); |
336 | 5439779e | edgar_igl | ptimer_stop(t->ptimer_wd); |
337 | 5439779e | edgar_igl | t->rw_wd_ctrl = 0;
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338 | 5439779e | edgar_igl | t->r_intr = 0;
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339 | 5439779e | edgar_igl | t->rw_intr_mask = 0;
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340 | 5439779e | edgar_igl | qemu_irq_lower(t->irq[0]);
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341 | 5439779e | edgar_igl | } |
342 | 5439779e | edgar_igl | |
343 | 5ef98b47 | edgar_igl | void etraxfs_timer_init(CPUState *env, qemu_irq *irqs, qemu_irq *nmi,
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344 | ca87d03b | edgar_igl | target_phys_addr_t base) |
345 | 83fa1010 | ths | { |
346 | ca87d03b | edgar_igl | static struct fs_timer_t *t; |
347 | 83fa1010 | ths | int timer_regs;
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348 | 83fa1010 | ths | |
349 | ca87d03b | edgar_igl | t = qemu_mallocz(sizeof *t);
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350 | ca87d03b | edgar_igl | if (!t)
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351 | ca87d03b | edgar_igl | return;
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352 | bbaf29c7 | edgar_igl | |
353 | 5439779e | edgar_igl | t->bh_t0 = qemu_bh_new(timer0_hit, t); |
354 | 5439779e | edgar_igl | t->bh_t1 = qemu_bh_new(timer1_hit, t); |
355 | 5439779e | edgar_igl | t->bh_wd = qemu_bh_new(watchdog_hit, t); |
356 | 5439779e | edgar_igl | t->ptimer_t0 = ptimer_init(t->bh_t0); |
357 | 5439779e | edgar_igl | t->ptimer_t1 = ptimer_init(t->bh_t1); |
358 | 5439779e | edgar_igl | t->ptimer_wd = ptimer_init(t->bh_wd); |
359 | 60237223 | edgar_igl | t->irq = irqs; |
360 | 5ef98b47 | edgar_igl | t->nmi = nmi; |
361 | ca87d03b | edgar_igl | t->env = env; |
362 | ca87d03b | edgar_igl | t->base = base; |
363 | 83fa1010 | ths | |
364 | ca87d03b | edgar_igl | timer_regs = cpu_register_io_memory(0, timer_read, timer_write, t);
|
365 | ca87d03b | edgar_igl | cpu_register_physical_memory (base, 0x5c, timer_regs);
|
366 | 5439779e | edgar_igl | |
367 | 5439779e | edgar_igl | qemu_register_reset(etraxfs_timer_reset, t); |
368 | 83fa1010 | ths | } |