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1 | ff1f20a3 | bellard | /*
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2 | ff1f20a3 | bellard | * dyngen helpers
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3 | 5fafdf24 | ths | *
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4 | ff1f20a3 | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | ff1f20a3 | bellard | *
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6 | ff1f20a3 | bellard | * This library is free software; you can redistribute it and/or
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7 | ff1f20a3 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | ff1f20a3 | bellard | * License as published by the Free Software Foundation; either
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9 | ff1f20a3 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | ff1f20a3 | bellard | *
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11 | ff1f20a3 | bellard | * This library is distributed in the hope that it will be useful,
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12 | ff1f20a3 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | ff1f20a3 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | ff1f20a3 | bellard | * Lesser General Public License for more details.
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15 | ff1f20a3 | bellard | *
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16 | ff1f20a3 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | ff1f20a3 | bellard | * License along with this library; if not, write to the Free Software
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18 | ff1f20a3 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | ff1f20a3 | bellard | */
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20 | ff1f20a3 | bellard | |
21 | 03daf0e3 | bellard | int __op_param1, __op_param2, __op_param3;
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22 | 46152182 | pbrook | #if defined(__sparc__) || defined(__arm__)
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23 | fdbb4691 | bellard | void __op_gen_label1(){}
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24 | fdbb4691 | bellard | void __op_gen_label2(){}
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25 | fdbb4691 | bellard | void __op_gen_label3(){}
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26 | fdbb4691 | bellard | #else
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27 | fdbb4691 | bellard | int __op_gen_label1, __op_gen_label2, __op_gen_label3;
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28 | fdbb4691 | bellard | #endif
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29 | c106152d | bellard | int __op_jmp0, __op_jmp1, __op_jmp2, __op_jmp3;
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30 | 03daf0e3 | bellard | |
31 | 522777bb | ths | #if defined(__i386__) || defined(__x86_64__) || defined(__s390__)
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32 | 03daf0e3 | bellard | static inline void flush_icache_range(unsigned long start, unsigned long stop) |
33 | 03daf0e3 | bellard | { |
34 | 03daf0e3 | bellard | } |
35 | 522777bb | ths | #elif defined(__ia64__)
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36 | 03daf0e3 | bellard | static inline void flush_icache_range(unsigned long start, unsigned long stop) |
37 | 03daf0e3 | bellard | { |
38 | b8076a74 | bellard | while (start < stop) {
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39 | b8076a74 | bellard | asm volatile ("fc %0" :: "r"(start)); |
40 | b8076a74 | bellard | start += 32;
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41 | b8076a74 | bellard | } |
42 | b8076a74 | bellard | asm volatile (";;sync.i;;srlz.i;;"); |
43 | 03daf0e3 | bellard | } |
44 | 522777bb | ths | #elif defined(__powerpc__)
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45 | 03daf0e3 | bellard | |
46 | 03daf0e3 | bellard | #define MIN_CACHE_LINE_SIZE 8 /* conservative value */ |
47 | 03daf0e3 | bellard | |
48 | 03daf0e3 | bellard | static void inline flush_icache_range(unsigned long start, unsigned long stop) |
49 | 03daf0e3 | bellard | { |
50 | 03daf0e3 | bellard | unsigned long p; |
51 | 03daf0e3 | bellard | |
52 | f5ba07d3 | pbrook | start &= ~(MIN_CACHE_LINE_SIZE - 1);
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53 | 03daf0e3 | bellard | stop = (stop + MIN_CACHE_LINE_SIZE - 1) & ~(MIN_CACHE_LINE_SIZE - 1); |
54 | 5fafdf24 | ths | |
55 | 03daf0e3 | bellard | for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
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56 | 03daf0e3 | bellard | asm volatile ("dcbst 0,%0" : : "r"(p) : "memory"); |
57 | 03daf0e3 | bellard | } |
58 | 03daf0e3 | bellard | asm volatile ("sync" : : : "memory"); |
59 | 03daf0e3 | bellard | for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
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60 | 03daf0e3 | bellard | asm volatile ("icbi 0,%0" : : "r"(p) : "memory"); |
61 | 03daf0e3 | bellard | } |
62 | 03daf0e3 | bellard | asm volatile ("sync" : : : "memory"); |
63 | 03daf0e3 | bellard | asm volatile ("isync" : : : "memory"); |
64 | 03daf0e3 | bellard | } |
65 | 522777bb | ths | #elif defined(__alpha__)
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66 | 03daf0e3 | bellard | static inline void flush_icache_range(unsigned long start, unsigned long stop) |
67 | 03daf0e3 | bellard | { |
68 | 03daf0e3 | bellard | asm ("imb"); |
69 | 03daf0e3 | bellard | } |
70 | 522777bb | ths | #elif defined(__sparc__)
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71 | 03daf0e3 | bellard | static void inline flush_icache_range(unsigned long start, unsigned long stop) |
72 | 03daf0e3 | bellard | { |
73 | 03daf0e3 | bellard | unsigned long p; |
74 | 03daf0e3 | bellard | |
75 | 03daf0e3 | bellard | p = start & ~(8UL - 1UL); |
76 | 03daf0e3 | bellard | stop = (stop + (8UL - 1UL)) & ~(8UL - 1UL); |
77 | 03daf0e3 | bellard | |
78 | 03daf0e3 | bellard | for (; p < stop; p += 8) |
79 | 03daf0e3 | bellard | __asm__ __volatile__("flush\t%0" : : "r" (p)); |
80 | 03daf0e3 | bellard | } |
81 | 522777bb | ths | #elif defined(__arm__)
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82 | 03daf0e3 | bellard | static inline void flush_icache_range(unsigned long start, unsigned long stop) |
83 | 03daf0e3 | bellard | { |
84 | 03daf0e3 | bellard | register unsigned long _beg __asm ("a1") = start; |
85 | 03daf0e3 | bellard | register unsigned long _end __asm ("a2") = stop; |
86 | 03daf0e3 | bellard | register unsigned long _flg __asm ("a3") = 0; |
87 | 03daf0e3 | bellard | __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg)); |
88 | 03daf0e3 | bellard | } |
89 | 522777bb | ths | #elif defined(__mc68000)
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90 | 03daf0e3 | bellard | |
91 | 522777bb | ths | # include <asm/cachectl.h> |
92 | 38e584a0 | bellard | static inline void flush_icache_range(unsigned long start, unsigned long stop) |
93 | 38e584a0 | bellard | { |
94 | 38e584a0 | bellard | cacheflush(start,FLUSH_SCOPE_LINE,FLUSH_CACHE_BOTH,stop-start+16);
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95 | 38e584a0 | bellard | } |
96 | 522777bb | ths | #elif defined(__mips__)
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97 | 522777bb | ths | |
98 | 522777bb | ths | #include <sys/cachectl.h> |
99 | 522777bb | ths | static inline void flush_icache_range(unsigned long start, unsigned long stop) |
100 | 522777bb | ths | { |
101 | 522777bb | ths | _flush_cache ((void *)start, stop - start, BCACHE);
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102 | 522777bb | ths | } |
103 | 522777bb | ths | #else
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104 | 522777bb | ths | #error unsupported CPU
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105 | 38e584a0 | bellard | #endif
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106 | 38e584a0 | bellard | |
107 | ff1f20a3 | bellard | #ifdef __alpha__
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108 | ff1f20a3 | bellard | |
109 | ff1f20a3 | bellard | register int gp asm("$29"); |
110 | ff1f20a3 | bellard | |
111 | ff1f20a3 | bellard | static inline void immediate_ldah(void *p, int val) { |
112 | ff1f20a3 | bellard | uint32_t *dest = p; |
113 | ff1f20a3 | bellard | long high = ((val >> 16) + ((val >> 15) & 1)) & 0xffff; |
114 | ff1f20a3 | bellard | |
115 | ff1f20a3 | bellard | *dest &= ~0xffff;
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116 | ff1f20a3 | bellard | *dest |= high; |
117 | ff1f20a3 | bellard | *dest |= 31 << 16; |
118 | ff1f20a3 | bellard | } |
119 | ff1f20a3 | bellard | static inline void immediate_lda(void *dest, int val) { |
120 | ff1f20a3 | bellard | *(uint16_t *) dest = val; |
121 | ff1f20a3 | bellard | } |
122 | ff1f20a3 | bellard | void fix_bsr(void *p, int offset) { |
123 | ff1f20a3 | bellard | uint32_t *dest = p; |
124 | ff1f20a3 | bellard | *dest &= ~((1 << 21) - 1); |
125 | ff1f20a3 | bellard | *dest |= (offset >> 2) & ((1 << 21) - 1); |
126 | ff1f20a3 | bellard | } |
127 | ff1f20a3 | bellard | |
128 | ff1f20a3 | bellard | #endif /* __alpha__ */ |
129 | ff1f20a3 | bellard | |
130 | ff1f20a3 | bellard | #ifdef __arm__
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131 | ff1f20a3 | bellard | |
132 | 46152182 | pbrook | #define ARM_LDR_TABLE_SIZE 1024 |
133 | ff1f20a3 | bellard | |
134 | ff1f20a3 | bellard | typedef struct LDREntry { |
135 | ff1f20a3 | bellard | uint8_t *ptr; |
136 | ff1f20a3 | bellard | uint32_t *data_ptr; |
137 | 46152182 | pbrook | unsigned type:2; |
138 | ff1f20a3 | bellard | } LDREntry; |
139 | ff1f20a3 | bellard | |
140 | ff1f20a3 | bellard | static LDREntry arm_ldr_table[1024]; |
141 | 46152182 | pbrook | static uint32_t arm_data_table[ARM_LDR_TABLE_SIZE];
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142 | ff1f20a3 | bellard | |
143 | ff1f20a3 | bellard | extern char exec_loop; |
144 | ff1f20a3 | bellard | |
145 | ff1f20a3 | bellard | static inline void arm_reloc_pc24(uint32_t *ptr, uint32_t insn, int val) |
146 | ff1f20a3 | bellard | { |
147 | ff1f20a3 | bellard | *ptr = (insn & ~0xffffff) | ((insn + ((val - (int)ptr) >> 2)) & 0xffffff); |
148 | ff1f20a3 | bellard | } |
149 | ff1f20a3 | bellard | |
150 | ff1f20a3 | bellard | static uint8_t *arm_flush_ldr(uint8_t *gen_code_ptr,
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151 | 5fafdf24 | ths | LDREntry *ldr_start, LDREntry *ldr_end, |
152 | 5fafdf24 | ths | uint32_t *data_start, uint32_t *data_end, |
153 | ff1f20a3 | bellard | int gen_jmp)
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154 | ff1f20a3 | bellard | { |
155 | ff1f20a3 | bellard | LDREntry *le; |
156 | ff1f20a3 | bellard | uint32_t *ptr; |
157 | ff1f20a3 | bellard | int offset, data_size, target;
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158 | ff1f20a3 | bellard | uint8_t *data_ptr; |
159 | ff1f20a3 | bellard | uint32_t insn; |
160 | 46152182 | pbrook | uint32_t mask; |
161 | 5fafdf24 | ths | |
162 | 46152182 | pbrook | data_size = (data_end - data_start) << 2;
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163 | ff1f20a3 | bellard | |
164 | 9621339d | bellard | if (gen_jmp) {
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165 | ff1f20a3 | bellard | /* generate branch to skip the data */
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166 | ff1f20a3 | bellard | if (data_size == 0) |
167 | ff1f20a3 | bellard | return gen_code_ptr;
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168 | ff1f20a3 | bellard | target = (long)gen_code_ptr + data_size + 4; |
169 | ff1f20a3 | bellard | arm_reloc_pc24((uint32_t *)gen_code_ptr, 0xeafffffe, target);
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170 | ff1f20a3 | bellard | gen_code_ptr += 4;
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171 | ff1f20a3 | bellard | } |
172 | 5fafdf24 | ths | |
173 | ff1f20a3 | bellard | /* copy the data */
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174 | ff1f20a3 | bellard | data_ptr = gen_code_ptr; |
175 | ff1f20a3 | bellard | memcpy(gen_code_ptr, data_start, data_size); |
176 | ff1f20a3 | bellard | gen_code_ptr += data_size; |
177 | 5fafdf24 | ths | |
178 | ff1f20a3 | bellard | /* patch the ldr to point to the data */
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179 | ff1f20a3 | bellard | for(le = ldr_start; le < ldr_end; le++) {
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180 | ff1f20a3 | bellard | ptr = (uint32_t *)le->ptr; |
181 | 5fafdf24 | ths | offset = ((unsigned long)(le->data_ptr) - (unsigned long)data_start) + |
182 | 5fafdf24 | ths | (unsigned long)data_ptr - |
183 | ff1f20a3 | bellard | (unsigned long)ptr - 8; |
184 | ff1f20a3 | bellard | if (offset < 0) { |
185 | 46152182 | pbrook | fprintf(stderr, "Negative constant pool offset\n");
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186 | ff1f20a3 | bellard | abort(); |
187 | ff1f20a3 | bellard | } |
188 | 46152182 | pbrook | switch (le->type) {
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189 | 46152182 | pbrook | case 0: /* ldr */ |
190 | 46152182 | pbrook | mask = ~0x00800fff;
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191 | 46152182 | pbrook | if (offset >= 4096) { |
192 | 46152182 | pbrook | fprintf(stderr, "Bad ldr offset\n");
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193 | 46152182 | pbrook | abort(); |
194 | 46152182 | pbrook | } |
195 | 46152182 | pbrook | break;
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196 | 46152182 | pbrook | case 1: /* ldc */ |
197 | 46152182 | pbrook | mask = ~0x008000ff;
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198 | 46152182 | pbrook | if (offset >= 1024 ) { |
199 | 46152182 | pbrook | fprintf(stderr, "Bad ldc offset\n");
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200 | 46152182 | pbrook | abort(); |
201 | 46152182 | pbrook | } |
202 | 46152182 | pbrook | break;
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203 | 46152182 | pbrook | case 2: /* add */ |
204 | 46152182 | pbrook | mask = ~0xfff;
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205 | 46152182 | pbrook | if (offset >= 1024 ) { |
206 | 46152182 | pbrook | fprintf(stderr, "Bad add offset\n");
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207 | 46152182 | pbrook | abort(); |
208 | 46152182 | pbrook | } |
209 | 46152182 | pbrook | break;
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210 | 46152182 | pbrook | default:
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211 | 46152182 | pbrook | fprintf(stderr, "Bad pc relative fixup\n");
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212 | 46152182 | pbrook | abort(); |
213 | 46152182 | pbrook | } |
214 | 46152182 | pbrook | insn = *ptr & mask; |
215 | 46152182 | pbrook | switch (le->type) {
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216 | 46152182 | pbrook | case 0: /* ldr */ |
217 | 46152182 | pbrook | insn |= offset | 0x00800000;
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218 | 46152182 | pbrook | break;
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219 | 46152182 | pbrook | case 1: /* ldc */ |
220 | 46152182 | pbrook | insn |= (offset >> 2) | 0x00800000; |
221 | 46152182 | pbrook | break;
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222 | 46152182 | pbrook | case 2: /* add */ |
223 | 46152182 | pbrook | insn |= (offset >> 2) | 0xf00; |
224 | 46152182 | pbrook | break;
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225 | 46152182 | pbrook | } |
226 | ff1f20a3 | bellard | *ptr = insn; |
227 | ff1f20a3 | bellard | } |
228 | ff1f20a3 | bellard | return gen_code_ptr;
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229 | ff1f20a3 | bellard | } |
230 | ff1f20a3 | bellard | |
231 | ff1f20a3 | bellard | #endif /* __arm__ */ |
232 | b8076a74 | bellard | |
233 | b8076a74 | bellard | #ifdef __ia64
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234 | b8076a74 | bellard | |
235 | b8076a74 | bellard | /* Patch instruction with "val" where "mask" has 1 bits. */
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236 | b8076a74 | bellard | static inline void ia64_patch (uint64_t insn_addr, uint64_t mask, uint64_t val) |
237 | b8076a74 | bellard | { |
238 | b8076a74 | bellard | uint64_t m0, m1, v0, v1, b0, b1, *b = (uint64_t *) (insn_addr & -16);
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239 | b8076a74 | bellard | # define insn_mask ((1UL << 41) - 1) |
240 | b8076a74 | bellard | unsigned long shift; |
241 | b8076a74 | bellard | |
242 | b8076a74 | bellard | b0 = b[0]; b1 = b[1]; |
243 | b8076a74 | bellard | shift = 5 + 41 * (insn_addr % 16); /* 5 template, 3 x 41-bit insns */ |
244 | b8076a74 | bellard | if (shift >= 64) { |
245 | b8076a74 | bellard | m1 = mask << (shift - 64);
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246 | b8076a74 | bellard | v1 = val << (shift - 64);
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247 | b8076a74 | bellard | } else {
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248 | b8076a74 | bellard | m0 = mask << shift; m1 = mask >> (64 - shift);
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249 | b8076a74 | bellard | v0 = val << shift; v1 = val >> (64 - shift);
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250 | b8076a74 | bellard | b[0] = (b0 & ~m0) | (v0 & m0);
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251 | b8076a74 | bellard | } |
252 | b8076a74 | bellard | b[1] = (b1 & ~m1) | (v1 & m1);
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253 | b8076a74 | bellard | } |
254 | b8076a74 | bellard | |
255 | b8076a74 | bellard | static inline void ia64_patch_imm60 (uint64_t insn_addr, uint64_t val) |
256 | b8076a74 | bellard | { |
257 | b8076a74 | bellard | ia64_patch(insn_addr, |
258 | b8076a74 | bellard | 0x011ffffe000UL,
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259 | b8076a74 | bellard | ( ((val & 0x0800000000000000UL) >> 23) /* bit 59 -> 36 */ |
260 | b8076a74 | bellard | | ((val & 0x00000000000fffffUL) << 13) /* bit 0 -> 13 */)); |
261 | b8076a74 | bellard | ia64_patch(insn_addr - 1, 0x1fffffffffcUL, val >> 18); |
262 | b8076a74 | bellard | } |
263 | b8076a74 | bellard | |
264 | b8076a74 | bellard | static inline void ia64_imm64 (void *insn, uint64_t val) |
265 | b8076a74 | bellard | { |
266 | b8076a74 | bellard | /* Ignore the slot number of the relocation; GCC and Intel
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267 | b8076a74 | bellard | toolchains differed for some time on whether IMM64 relocs are
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268 | b8076a74 | bellard | against slot 1 (Intel) or slot 2 (GCC). */
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269 | b8076a74 | bellard | uint64_t insn_addr = (uint64_t) insn & ~3UL;
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270 | b8076a74 | bellard | |
271 | b8076a74 | bellard | ia64_patch(insn_addr + 2,
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272 | b8076a74 | bellard | 0x01fffefe000UL,
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273 | b8076a74 | bellard | ( ((val & 0x8000000000000000UL) >> 27) /* bit 63 -> 36 */ |
274 | b8076a74 | bellard | | ((val & 0x0000000000200000UL) << 0) /* bit 21 -> 21 */ |
275 | b8076a74 | bellard | | ((val & 0x00000000001f0000UL) << 6) /* bit 16 -> 22 */ |
276 | b8076a74 | bellard | | ((val & 0x000000000000ff80UL) << 20) /* bit 7 -> 27 */ |
277 | b8076a74 | bellard | | ((val & 0x000000000000007fUL) << 13) /* bit 0 -> 13 */) |
278 | b8076a74 | bellard | ); |
279 | b8076a74 | bellard | ia64_patch(insn_addr + 1, 0x1ffffffffffUL, val >> 22); |
280 | b8076a74 | bellard | } |
281 | b8076a74 | bellard | |
282 | b8076a74 | bellard | static inline void ia64_imm60b (void *insn, uint64_t val) |
283 | b8076a74 | bellard | { |
284 | b8076a74 | bellard | /* Ignore the slot number of the relocation; GCC and Intel
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285 | b8076a74 | bellard | toolchains differed for some time on whether IMM64 relocs are
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286 | b8076a74 | bellard | against slot 1 (Intel) or slot 2 (GCC). */
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287 | b8076a74 | bellard | uint64_t insn_addr = (uint64_t) insn & ~3UL;
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288 | b8076a74 | bellard | |
289 | b8076a74 | bellard | if (val + ((uint64_t) 1 << 59) >= (1UL << 60)) |
290 | b8076a74 | bellard | fprintf(stderr, "%s: value %ld out of IMM60 range\n",
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291 | b8076a74 | bellard | __FUNCTION__, (int64_t) val); |
292 | b8076a74 | bellard | ia64_patch_imm60(insn_addr + 2, val);
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293 | b8076a74 | bellard | } |
294 | b8076a74 | bellard | |
295 | b8076a74 | bellard | static inline void ia64_imm22 (void *insn, uint64_t val) |
296 | b8076a74 | bellard | { |
297 | b8076a74 | bellard | if (val + (1 << 21) >= (1 << 22)) |
298 | b8076a74 | bellard | fprintf(stderr, "%s: value %li out of IMM22 range\n",
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299 | b8076a74 | bellard | __FUNCTION__, (int64_t)val); |
300 | b8076a74 | bellard | ia64_patch((uint64_t) insn, 0x01fffcfe000UL,
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301 | b8076a74 | bellard | ( ((val & 0x200000UL) << 15) /* bit 21 -> 36 */ |
302 | b8076a74 | bellard | | ((val & 0x1f0000UL) << 6) /* bit 16 -> 22 */ |
303 | b8076a74 | bellard | | ((val & 0x00ff80UL) << 20) /* bit 7 -> 27 */ |
304 | b8076a74 | bellard | | ((val & 0x00007fUL) << 13) /* bit 0 -> 13 */)); |
305 | b8076a74 | bellard | } |
306 | b8076a74 | bellard | |
307 | b8076a74 | bellard | /* Like ia64_imm22(), but also clear bits 20-21. For addl, this has
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308 | b8076a74 | bellard | the effect of turning "addl rX=imm22,rY" into "addl
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309 | b8076a74 | bellard | rX=imm22,r0". */
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310 | b8076a74 | bellard | static inline void ia64_imm22_r0 (void *insn, uint64_t val) |
311 | b8076a74 | bellard | { |
312 | b8076a74 | bellard | if (val + (1 << 21) >= (1 << 22)) |
313 | b8076a74 | bellard | fprintf(stderr, "%s: value %li out of IMM22 range\n",
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314 | b8076a74 | bellard | __FUNCTION__, (int64_t)val); |
315 | b8076a74 | bellard | ia64_patch((uint64_t) insn, 0x01fffcfe000UL | (0x3UL << 20), |
316 | b8076a74 | bellard | ( ((val & 0x200000UL) << 15) /* bit 21 -> 36 */ |
317 | b8076a74 | bellard | | ((val & 0x1f0000UL) << 6) /* bit 16 -> 22 */ |
318 | b8076a74 | bellard | | ((val & 0x00ff80UL) << 20) /* bit 7 -> 27 */ |
319 | b8076a74 | bellard | | ((val & 0x00007fUL) << 13) /* bit 0 -> 13 */)); |
320 | b8076a74 | bellard | } |
321 | b8076a74 | bellard | |
322 | b8076a74 | bellard | static inline void ia64_imm21b (void *insn, uint64_t val) |
323 | b8076a74 | bellard | { |
324 | b8076a74 | bellard | if (val + (1 << 20) >= (1 << 21)) |
325 | b8076a74 | bellard | fprintf(stderr, "%s: value %li out of IMM21b range\n",
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326 | b8076a74 | bellard | __FUNCTION__, (int64_t)val); |
327 | b8076a74 | bellard | ia64_patch((uint64_t) insn, 0x11ffffe000UL,
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328 | b8076a74 | bellard | ( ((val & 0x100000UL) << 16) /* bit 20 -> 36 */ |
329 | b8076a74 | bellard | | ((val & 0x0fffffUL) << 13) /* bit 0 -> 13 */)); |
330 | b8076a74 | bellard | } |
331 | b8076a74 | bellard | |
332 | b8076a74 | bellard | static inline void ia64_nop_b (void *insn) |
333 | b8076a74 | bellard | { |
334 | b8076a74 | bellard | ia64_patch((uint64_t) insn, (1UL << 41) - 1, 2UL << 37); |
335 | b8076a74 | bellard | } |
336 | b8076a74 | bellard | |
337 | b8076a74 | bellard | static inline void ia64_ldxmov(void *insn, uint64_t val) |
338 | b8076a74 | bellard | { |
339 | b8076a74 | bellard | if (val + (1 << 21) < (1 << 22)) |
340 | b8076a74 | bellard | ia64_patch((uint64_t) insn, 0x1fff80fe000UL, 8UL << 37); |
341 | b8076a74 | bellard | } |
342 | b8076a74 | bellard | |
343 | b8076a74 | bellard | static inline int ia64_patch_ltoff(void *insn, uint64_t val, |
344 | b8076a74 | bellard | int relaxable)
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345 | b8076a74 | bellard | { |
346 | b8076a74 | bellard | if (relaxable && (val + (1 << 21) < (1 << 22))) { |
347 | b8076a74 | bellard | ia64_imm22_r0(insn, val); |
348 | b8076a74 | bellard | return 0; |
349 | b8076a74 | bellard | } |
350 | b8076a74 | bellard | return 1; |
351 | b8076a74 | bellard | } |
352 | b8076a74 | bellard | |
353 | b8076a74 | bellard | struct ia64_fixup {
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354 | b8076a74 | bellard | struct ia64_fixup *next;
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355 | b8076a74 | bellard | void *addr; /* address that needs to be patched */ |
356 | b8076a74 | bellard | long value;
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357 | b8076a74 | bellard | }; |
358 | b8076a74 | bellard | |
359 | b8076a74 | bellard | #define IA64_PLT(insn, plt_index) \
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360 | b8076a74 | bellard | do { \
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361 | b8076a74 | bellard | struct ia64_fixup *fixup = alloca(sizeof(*fixup)); \ |
362 | b8076a74 | bellard | fixup->next = plt_fixes; \ |
363 | b8076a74 | bellard | plt_fixes = fixup; \ |
364 | b8076a74 | bellard | fixup->addr = (insn); \ |
365 | b8076a74 | bellard | fixup->value = (plt_index); \ |
366 | b8076a74 | bellard | plt_offset[(plt_index)] = 1; \
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367 | b8076a74 | bellard | } while (0) |
368 | b8076a74 | bellard | |
369 | b8076a74 | bellard | #define IA64_LTOFF(insn, val, relaxable) \
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370 | b8076a74 | bellard | do { \
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371 | b8076a74 | bellard | if (ia64_patch_ltoff(insn, val, relaxable)) { \
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372 | b8076a74 | bellard | struct ia64_fixup *fixup = alloca(sizeof(*fixup)); \ |
373 | b8076a74 | bellard | fixup->next = ltoff_fixes; \ |
374 | b8076a74 | bellard | ltoff_fixes = fixup; \ |
375 | b8076a74 | bellard | fixup->addr = (insn); \ |
376 | b8076a74 | bellard | fixup->value = (val); \ |
377 | b8076a74 | bellard | } \ |
378 | b8076a74 | bellard | } while (0) |
379 | b8076a74 | bellard | |
380 | b8076a74 | bellard | static inline void ia64_apply_fixes (uint8_t **gen_code_pp, |
381 | b8076a74 | bellard | struct ia64_fixup *ltoff_fixes,
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382 | b8076a74 | bellard | uint64_t gp, |
383 | b8076a74 | bellard | struct ia64_fixup *plt_fixes,
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384 | b8076a74 | bellard | int num_plts,
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385 | b8076a74 | bellard | unsigned long *plt_target, |
386 | b8076a74 | bellard | unsigned int *plt_offset) |
387 | b8076a74 | bellard | { |
388 | b8076a74 | bellard | static const uint8_t plt_bundle[] = { |
389 | b8076a74 | bellard | 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, /* nop 0; movl r1=GP */ |
390 | b8076a74 | bellard | 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x60, |
391 | b8076a74 | bellard | |
392 | b8076a74 | bellard | 0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, /* nop 0; brl IP */ |
393 | b8076a74 | bellard | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0 |
394 | b8076a74 | bellard | }; |
395 | 6d8aa3bf | balrog | uint8_t *gen_code_ptr = *gen_code_pp, *plt_start, *got_start; |
396 | 6d8aa3bf | balrog | uint64_t *vp; |
397 | b8076a74 | bellard | struct ia64_fixup *fixup;
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398 | b8076a74 | bellard | unsigned int offset = 0; |
399 | b8076a74 | bellard | struct fdesc {
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400 | b8076a74 | bellard | long ip;
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401 | b8076a74 | bellard | long gp;
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402 | b8076a74 | bellard | } *fdesc; |
403 | b8076a74 | bellard | int i;
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404 | b8076a74 | bellard | |
405 | b8076a74 | bellard | if (plt_fixes) {
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406 | b8076a74 | bellard | plt_start = gen_code_ptr; |
407 | b8076a74 | bellard | |
408 | b8076a74 | bellard | for (i = 0; i < num_plts; ++i) { |
409 | b8076a74 | bellard | if (plt_offset[i]) {
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410 | b8076a74 | bellard | plt_offset[i] = offset; |
411 | b8076a74 | bellard | offset += sizeof(plt_bundle);
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412 | b8076a74 | bellard | |
413 | b8076a74 | bellard | fdesc = (struct fdesc *) plt_target[i];
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414 | b8076a74 | bellard | memcpy(gen_code_ptr, plt_bundle, sizeof(plt_bundle));
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415 | b8076a74 | bellard | ia64_imm64 (gen_code_ptr + 0x02, fdesc->gp);
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416 | b8076a74 | bellard | ia64_imm60b(gen_code_ptr + 0x12,
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417 | b8076a74 | bellard | (fdesc->ip - (long) (gen_code_ptr + 0x10)) >> 4); |
418 | b8076a74 | bellard | gen_code_ptr += sizeof(plt_bundle);
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419 | b8076a74 | bellard | } |
420 | b8076a74 | bellard | } |
421 | b8076a74 | bellard | |
422 | b8076a74 | bellard | for (fixup = plt_fixes; fixup; fixup = fixup->next)
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423 | b8076a74 | bellard | ia64_imm21b(fixup->addr, |
424 | b8076a74 | bellard | ((long) plt_start + plt_offset[fixup->value]
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425 | b8076a74 | bellard | - ((long) fixup->addr & ~0xf)) >> 4); |
426 | b8076a74 | bellard | } |
427 | b8076a74 | bellard | |
428 | b8076a74 | bellard | got_start = gen_code_ptr; |
429 | b8076a74 | bellard | |
430 | b8076a74 | bellard | /* First, create the GOT: */
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431 | b8076a74 | bellard | for (fixup = ltoff_fixes; fixup; fixup = fixup->next) {
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432 | b8076a74 | bellard | /* first check if we already have this value in the GOT: */
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433 | 6d8aa3bf | balrog | for (vp = (uint64_t *) got_start; vp < (uint64_t *) gen_code_ptr; ++vp)
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434 | 6d8aa3bf | balrog | if (*vp == fixup->value)
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435 | b8076a74 | bellard | break;
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436 | 6d8aa3bf | balrog | if (vp == (uint64_t *) gen_code_ptr) {
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437 | b8076a74 | bellard | /* Nope, we need to put the value in the GOT: */
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438 | 6d8aa3bf | balrog | *vp = fixup->value; |
439 | b8076a74 | bellard | gen_code_ptr += 8;
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440 | b8076a74 | bellard | } |
441 | b8076a74 | bellard | ia64_imm22(fixup->addr, (long) vp - gp);
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442 | b8076a74 | bellard | } |
443 | fd4a43e4 | bellard | /* Keep code ptr aligned. */
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444 | fd4a43e4 | bellard | if ((long) gen_code_ptr & 15) |
445 | fd4a43e4 | bellard | gen_code_ptr += 8;
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446 | b8076a74 | bellard | *gen_code_pp = gen_code_ptr; |
447 | b8076a74 | bellard | } |
448 | b8076a74 | bellard | |
449 | b8076a74 | bellard | #endif |