root / hw / mc146818rtc.c @ 5fafdf24
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1 | 80cabfad | bellard | /*
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2 | 80cabfad | bellard | * QEMU MC146818 RTC emulation
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3 | 5fafdf24 | ths | *
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4 | 80cabfad | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 80cabfad | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 80cabfad | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 80cabfad | bellard | * in the Software without restriction, including without limitation the rights
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9 | 80cabfad | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 80cabfad | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 80cabfad | bellard | * furnished to do so, subject to the following conditions:
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12 | 80cabfad | bellard | *
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13 | 80cabfad | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 80cabfad | bellard | * all copies or substantial portions of the Software.
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15 | 80cabfad | bellard | *
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16 | 80cabfad | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 80cabfad | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 80cabfad | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 80cabfad | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 80cabfad | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 80cabfad | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 80cabfad | bellard | * THE SOFTWARE.
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23 | 80cabfad | bellard | */
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24 | 80cabfad | bellard | #include "vl.h" |
25 | 80cabfad | bellard | |
26 | 80cabfad | bellard | //#define DEBUG_CMOS
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27 | 80cabfad | bellard | |
28 | 80cabfad | bellard | #define RTC_SECONDS 0 |
29 | 80cabfad | bellard | #define RTC_SECONDS_ALARM 1 |
30 | 80cabfad | bellard | #define RTC_MINUTES 2 |
31 | 80cabfad | bellard | #define RTC_MINUTES_ALARM 3 |
32 | 80cabfad | bellard | #define RTC_HOURS 4 |
33 | 80cabfad | bellard | #define RTC_HOURS_ALARM 5 |
34 | 80cabfad | bellard | #define RTC_ALARM_DONT_CARE 0xC0 |
35 | 80cabfad | bellard | |
36 | 80cabfad | bellard | #define RTC_DAY_OF_WEEK 6 |
37 | 80cabfad | bellard | #define RTC_DAY_OF_MONTH 7 |
38 | 80cabfad | bellard | #define RTC_MONTH 8 |
39 | 80cabfad | bellard | #define RTC_YEAR 9 |
40 | 80cabfad | bellard | |
41 | 80cabfad | bellard | #define RTC_REG_A 10 |
42 | 80cabfad | bellard | #define RTC_REG_B 11 |
43 | 80cabfad | bellard | #define RTC_REG_C 12 |
44 | 80cabfad | bellard | #define RTC_REG_D 13 |
45 | 80cabfad | bellard | |
46 | dff38e7b | bellard | #define REG_A_UIP 0x80 |
47 | 80cabfad | bellard | |
48 | dff38e7b | bellard | #define REG_B_SET 0x80 |
49 | dff38e7b | bellard | #define REG_B_PIE 0x40 |
50 | dff38e7b | bellard | #define REG_B_AIE 0x20 |
51 | dff38e7b | bellard | #define REG_B_UIE 0x10 |
52 | dff38e7b | bellard | |
53 | dff38e7b | bellard | struct RTCState {
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54 | dff38e7b | bellard | uint8_t cmos_data[128];
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55 | dff38e7b | bellard | uint8_t cmos_index; |
56 | 43f493af | bellard | struct tm current_tm;
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57 | d537cf6c | pbrook | qemu_irq irq; |
58 | 2ca9d013 | ths | target_phys_addr_t base; |
59 | 18c6e2ff | ths | int it_shift;
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60 | dff38e7b | bellard | /* periodic timer */
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61 | dff38e7b | bellard | QEMUTimer *periodic_timer; |
62 | dff38e7b | bellard | int64_t next_periodic_time; |
63 | dff38e7b | bellard | /* second update */
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64 | dff38e7b | bellard | int64_t next_second_time; |
65 | dff38e7b | bellard | QEMUTimer *second_timer; |
66 | dff38e7b | bellard | QEMUTimer *second_timer2; |
67 | dff38e7b | bellard | }; |
68 | dff38e7b | bellard | |
69 | dff38e7b | bellard | static void rtc_set_time(RTCState *s); |
70 | dff38e7b | bellard | static void rtc_copy_date(RTCState *s); |
71 | dff38e7b | bellard | |
72 | dff38e7b | bellard | static void rtc_timer_update(RTCState *s, int64_t current_time) |
73 | dff38e7b | bellard | { |
74 | dff38e7b | bellard | int period_code, period;
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75 | dff38e7b | bellard | int64_t cur_clock, next_irq_clock; |
76 | dff38e7b | bellard | |
77 | dff38e7b | bellard | period_code = s->cmos_data[RTC_REG_A] & 0x0f;
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78 | 5fafdf24 | ths | if (period_code != 0 && |
79 | dff38e7b | bellard | (s->cmos_data[RTC_REG_B] & REG_B_PIE)) { |
80 | dff38e7b | bellard | if (period_code <= 2) |
81 | dff38e7b | bellard | period_code += 7;
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82 | dff38e7b | bellard | /* period in 32 Khz cycles */
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83 | dff38e7b | bellard | period = 1 << (period_code - 1); |
84 | dff38e7b | bellard | /* compute 32 khz clock */
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85 | dff38e7b | bellard | cur_clock = muldiv64(current_time, 32768, ticks_per_sec);
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86 | dff38e7b | bellard | next_irq_clock = (cur_clock & ~(period - 1)) + period;
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87 | dff38e7b | bellard | s->next_periodic_time = muldiv64(next_irq_clock, ticks_per_sec, 32768) + 1; |
88 | dff38e7b | bellard | qemu_mod_timer(s->periodic_timer, s->next_periodic_time); |
89 | dff38e7b | bellard | } else {
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90 | dff38e7b | bellard | qemu_del_timer(s->periodic_timer); |
91 | dff38e7b | bellard | } |
92 | dff38e7b | bellard | } |
93 | dff38e7b | bellard | |
94 | dff38e7b | bellard | static void rtc_periodic_timer(void *opaque) |
95 | dff38e7b | bellard | { |
96 | dff38e7b | bellard | RTCState *s = opaque; |
97 | dff38e7b | bellard | |
98 | dff38e7b | bellard | rtc_timer_update(s, s->next_periodic_time); |
99 | dff38e7b | bellard | s->cmos_data[RTC_REG_C] |= 0xc0;
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100 | d537cf6c | pbrook | qemu_irq_raise(s->irq); |
101 | dff38e7b | bellard | } |
102 | 80cabfad | bellard | |
103 | b41a2cd1 | bellard | static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) |
104 | 80cabfad | bellard | { |
105 | b41a2cd1 | bellard | RTCState *s = opaque; |
106 | 80cabfad | bellard | |
107 | 80cabfad | bellard | if ((addr & 1) == 0) { |
108 | 80cabfad | bellard | s->cmos_index = data & 0x7f;
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109 | 80cabfad | bellard | } else {
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110 | 80cabfad | bellard | #ifdef DEBUG_CMOS
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111 | 80cabfad | bellard | printf("cmos: write index=0x%02x val=0x%02x\n",
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112 | 80cabfad | bellard | s->cmos_index, data); |
113 | 5fafdf24 | ths | #endif
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114 | dff38e7b | bellard | switch(s->cmos_index) {
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115 | 80cabfad | bellard | case RTC_SECONDS_ALARM:
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116 | 80cabfad | bellard | case RTC_MINUTES_ALARM:
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117 | 80cabfad | bellard | case RTC_HOURS_ALARM:
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118 | 80cabfad | bellard | /* XXX: not supported */
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119 | 80cabfad | bellard | s->cmos_data[s->cmos_index] = data; |
120 | 80cabfad | bellard | break;
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121 | 80cabfad | bellard | case RTC_SECONDS:
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122 | 80cabfad | bellard | case RTC_MINUTES:
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123 | 80cabfad | bellard | case RTC_HOURS:
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124 | 80cabfad | bellard | case RTC_DAY_OF_WEEK:
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125 | 80cabfad | bellard | case RTC_DAY_OF_MONTH:
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126 | 80cabfad | bellard | case RTC_MONTH:
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127 | 80cabfad | bellard | case RTC_YEAR:
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128 | 80cabfad | bellard | s->cmos_data[s->cmos_index] = data; |
129 | dff38e7b | bellard | /* if in set mode, do not update the time */
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130 | dff38e7b | bellard | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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131 | dff38e7b | bellard | rtc_set_time(s); |
132 | dff38e7b | bellard | } |
133 | 80cabfad | bellard | break;
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134 | 80cabfad | bellard | case RTC_REG_A:
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135 | dff38e7b | bellard | /* UIP bit is read only */
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136 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | |
137 | dff38e7b | bellard | (s->cmos_data[RTC_REG_A] & REG_A_UIP); |
138 | dff38e7b | bellard | rtc_timer_update(s, qemu_get_clock(vm_clock)); |
139 | dff38e7b | bellard | break;
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140 | 80cabfad | bellard | case RTC_REG_B:
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141 | dff38e7b | bellard | if (data & REG_B_SET) {
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142 | dff38e7b | bellard | /* set mode: reset UIP mode */
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143 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
144 | dff38e7b | bellard | data &= ~REG_B_UIE; |
145 | dff38e7b | bellard | } else {
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146 | dff38e7b | bellard | /* if disabling set mode, update the time */
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147 | dff38e7b | bellard | if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
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148 | dff38e7b | bellard | rtc_set_time(s); |
149 | dff38e7b | bellard | } |
150 | dff38e7b | bellard | } |
151 | dff38e7b | bellard | s->cmos_data[RTC_REG_B] = data; |
152 | dff38e7b | bellard | rtc_timer_update(s, qemu_get_clock(vm_clock)); |
153 | 80cabfad | bellard | break;
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154 | 80cabfad | bellard | case RTC_REG_C:
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155 | 80cabfad | bellard | case RTC_REG_D:
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156 | 80cabfad | bellard | /* cannot write to them */
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157 | 80cabfad | bellard | break;
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158 | 80cabfad | bellard | default:
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159 | 80cabfad | bellard | s->cmos_data[s->cmos_index] = data; |
160 | 80cabfad | bellard | break;
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161 | 80cabfad | bellard | } |
162 | 80cabfad | bellard | } |
163 | 80cabfad | bellard | } |
164 | 80cabfad | bellard | |
165 | dff38e7b | bellard | static inline int to_bcd(RTCState *s, int a) |
166 | 80cabfad | bellard | { |
167 | dff38e7b | bellard | if (s->cmos_data[RTC_REG_B] & 0x04) { |
168 | dff38e7b | bellard | return a;
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169 | dff38e7b | bellard | } else {
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170 | dff38e7b | bellard | return ((a / 10) << 4) | (a % 10); |
171 | dff38e7b | bellard | } |
172 | 80cabfad | bellard | } |
173 | 80cabfad | bellard | |
174 | dff38e7b | bellard | static inline int from_bcd(RTCState *s, int a) |
175 | 80cabfad | bellard | { |
176 | dff38e7b | bellard | if (s->cmos_data[RTC_REG_B] & 0x04) { |
177 | dff38e7b | bellard | return a;
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178 | dff38e7b | bellard | } else {
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179 | dff38e7b | bellard | return ((a >> 4) * 10) + (a & 0x0f); |
180 | dff38e7b | bellard | } |
181 | dff38e7b | bellard | } |
182 | dff38e7b | bellard | |
183 | dff38e7b | bellard | static void rtc_set_time(RTCState *s) |
184 | dff38e7b | bellard | { |
185 | 43f493af | bellard | struct tm *tm = &s->current_tm;
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186 | dff38e7b | bellard | |
187 | dff38e7b | bellard | tm->tm_sec = from_bcd(s, s->cmos_data[RTC_SECONDS]); |
188 | dff38e7b | bellard | tm->tm_min = from_bcd(s, s->cmos_data[RTC_MINUTES]); |
189 | 43f493af | bellard | tm->tm_hour = from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
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190 | 43f493af | bellard | if (!(s->cmos_data[RTC_REG_B] & 0x02) && |
191 | 43f493af | bellard | (s->cmos_data[RTC_HOURS] & 0x80)) {
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192 | 43f493af | bellard | tm->tm_hour += 12;
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193 | 43f493af | bellard | } |
194 | dff38e7b | bellard | tm->tm_wday = from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]); |
195 | dff38e7b | bellard | tm->tm_mday = from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]); |
196 | dff38e7b | bellard | tm->tm_mon = from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
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197 | dff38e7b | bellard | tm->tm_year = from_bcd(s, s->cmos_data[RTC_YEAR]) + 100;
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198 | 43f493af | bellard | } |
199 | 43f493af | bellard | |
200 | 43f493af | bellard | static void rtc_copy_date(RTCState *s) |
201 | 43f493af | bellard | { |
202 | 43f493af | bellard | const struct tm *tm = &s->current_tm; |
203 | dff38e7b | bellard | |
204 | 43f493af | bellard | s->cmos_data[RTC_SECONDS] = to_bcd(s, tm->tm_sec); |
205 | 43f493af | bellard | s->cmos_data[RTC_MINUTES] = to_bcd(s, tm->tm_min); |
206 | 43f493af | bellard | if (s->cmos_data[RTC_REG_B] & 0x02) { |
207 | 43f493af | bellard | /* 24 hour format */
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208 | 43f493af | bellard | s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour); |
209 | 43f493af | bellard | } else {
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210 | 43f493af | bellard | /* 12 hour format */
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211 | 43f493af | bellard | s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour % 12);
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212 | 43f493af | bellard | if (tm->tm_hour >= 12) |
213 | 43f493af | bellard | s->cmos_data[RTC_HOURS] |= 0x80;
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214 | 43f493af | bellard | } |
215 | 43f493af | bellard | s->cmos_data[RTC_DAY_OF_WEEK] = to_bcd(s, tm->tm_wday); |
216 | 43f493af | bellard | s->cmos_data[RTC_DAY_OF_MONTH] = to_bcd(s, tm->tm_mday); |
217 | 43f493af | bellard | s->cmos_data[RTC_MONTH] = to_bcd(s, tm->tm_mon + 1);
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218 | 43f493af | bellard | s->cmos_data[RTC_YEAR] = to_bcd(s, tm->tm_year % 100);
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219 | 43f493af | bellard | } |
220 | 43f493af | bellard | |
221 | 43f493af | bellard | /* month is between 0 and 11. */
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222 | 43f493af | bellard | static int get_days_in_month(int month, int year) |
223 | 43f493af | bellard | { |
224 | 5fafdf24 | ths | static const int days_tab[12] = { |
225 | 5fafdf24 | ths | 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 |
226 | 43f493af | bellard | }; |
227 | 43f493af | bellard | int d;
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228 | 43f493af | bellard | if ((unsigned )month >= 12) |
229 | 43f493af | bellard | return 31; |
230 | 43f493af | bellard | d = days_tab[month]; |
231 | 43f493af | bellard | if (month == 1) { |
232 | 43f493af | bellard | if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0)) |
233 | 43f493af | bellard | d++; |
234 | 43f493af | bellard | } |
235 | 43f493af | bellard | return d;
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236 | 43f493af | bellard | } |
237 | 43f493af | bellard | |
238 | 43f493af | bellard | /* update 'tm' to the next second */
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239 | 43f493af | bellard | static void rtc_next_second(struct tm *tm) |
240 | 43f493af | bellard | { |
241 | 43f493af | bellard | int days_in_month;
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242 | 43f493af | bellard | |
243 | 43f493af | bellard | tm->tm_sec++; |
244 | 43f493af | bellard | if ((unsigned)tm->tm_sec >= 60) { |
245 | 43f493af | bellard | tm->tm_sec = 0;
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246 | 43f493af | bellard | tm->tm_min++; |
247 | 43f493af | bellard | if ((unsigned)tm->tm_min >= 60) { |
248 | 43f493af | bellard | tm->tm_min = 0;
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249 | 43f493af | bellard | tm->tm_hour++; |
250 | 43f493af | bellard | if ((unsigned)tm->tm_hour >= 24) { |
251 | 43f493af | bellard | tm->tm_hour = 0;
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252 | 43f493af | bellard | /* next day */
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253 | 43f493af | bellard | tm->tm_wday++; |
254 | 43f493af | bellard | if ((unsigned)tm->tm_wday >= 7) |
255 | 43f493af | bellard | tm->tm_wday = 0;
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256 | 5fafdf24 | ths | days_in_month = get_days_in_month(tm->tm_mon, |
257 | 43f493af | bellard | tm->tm_year + 1900);
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258 | 43f493af | bellard | tm->tm_mday++; |
259 | 43f493af | bellard | if (tm->tm_mday < 1) { |
260 | 43f493af | bellard | tm->tm_mday = 1;
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261 | 43f493af | bellard | } else if (tm->tm_mday > days_in_month) { |
262 | 43f493af | bellard | tm->tm_mday = 1;
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263 | 43f493af | bellard | tm->tm_mon++; |
264 | 43f493af | bellard | if (tm->tm_mon >= 12) { |
265 | 43f493af | bellard | tm->tm_mon = 0;
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266 | 43f493af | bellard | tm->tm_year++; |
267 | 43f493af | bellard | } |
268 | 43f493af | bellard | } |
269 | 43f493af | bellard | } |
270 | 43f493af | bellard | } |
271 | 43f493af | bellard | } |
272 | dff38e7b | bellard | } |
273 | dff38e7b | bellard | |
274 | 43f493af | bellard | |
275 | dff38e7b | bellard | static void rtc_update_second(void *opaque) |
276 | dff38e7b | bellard | { |
277 | dff38e7b | bellard | RTCState *s = opaque; |
278 | 4721c457 | bellard | int64_t delay; |
279 | dff38e7b | bellard | |
280 | dff38e7b | bellard | /* if the oscillator is not in normal operation, we do not update */
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281 | dff38e7b | bellard | if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) { |
282 | dff38e7b | bellard | s->next_second_time += ticks_per_sec; |
283 | dff38e7b | bellard | qemu_mod_timer(s->second_timer, s->next_second_time); |
284 | dff38e7b | bellard | } else {
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285 | 43f493af | bellard | rtc_next_second(&s->current_tm); |
286 | 5fafdf24 | ths | |
287 | dff38e7b | bellard | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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288 | dff38e7b | bellard | /* update in progress bit */
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289 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] |= REG_A_UIP; |
290 | dff38e7b | bellard | } |
291 | 4721c457 | bellard | /* should be 244 us = 8 / 32768 seconds, but currently the
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292 | 4721c457 | bellard | timers do not have the necessary resolution. */
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293 | 4721c457 | bellard | delay = (ticks_per_sec * 1) / 100; |
294 | 4721c457 | bellard | if (delay < 1) |
295 | 4721c457 | bellard | delay = 1;
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296 | 5fafdf24 | ths | qemu_mod_timer(s->second_timer2, |
297 | 4721c457 | bellard | s->next_second_time + delay); |
298 | dff38e7b | bellard | } |
299 | dff38e7b | bellard | } |
300 | dff38e7b | bellard | |
301 | dff38e7b | bellard | static void rtc_update_second2(void *opaque) |
302 | dff38e7b | bellard | { |
303 | dff38e7b | bellard | RTCState *s = opaque; |
304 | dff38e7b | bellard | |
305 | dff38e7b | bellard | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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306 | dff38e7b | bellard | rtc_copy_date(s); |
307 | dff38e7b | bellard | } |
308 | dff38e7b | bellard | |
309 | dff38e7b | bellard | /* check alarm */
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310 | dff38e7b | bellard | if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
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311 | dff38e7b | bellard | if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 || |
312 | 43f493af | bellard | s->cmos_data[RTC_SECONDS_ALARM] == s->current_tm.tm_sec) && |
313 | dff38e7b | bellard | ((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 || |
314 | 43f493af | bellard | s->cmos_data[RTC_MINUTES_ALARM] == s->current_tm.tm_mon) && |
315 | dff38e7b | bellard | ((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 || |
316 | 43f493af | bellard | s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) { |
317 | dff38e7b | bellard | |
318 | 5fafdf24 | ths | s->cmos_data[RTC_REG_C] |= 0xa0;
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319 | d537cf6c | pbrook | qemu_irq_raise(s->irq); |
320 | dff38e7b | bellard | } |
321 | dff38e7b | bellard | } |
322 | dff38e7b | bellard | |
323 | dff38e7b | bellard | /* update ended interrupt */
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324 | dff38e7b | bellard | if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
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325 | 5fafdf24 | ths | s->cmos_data[RTC_REG_C] |= 0x90;
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326 | d537cf6c | pbrook | qemu_irq_raise(s->irq); |
327 | dff38e7b | bellard | } |
328 | dff38e7b | bellard | |
329 | dff38e7b | bellard | /* clear update in progress bit */
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330 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
331 | dff38e7b | bellard | |
332 | dff38e7b | bellard | s->next_second_time += ticks_per_sec; |
333 | dff38e7b | bellard | qemu_mod_timer(s->second_timer, s->next_second_time); |
334 | 80cabfad | bellard | } |
335 | 80cabfad | bellard | |
336 | b41a2cd1 | bellard | static uint32_t cmos_ioport_read(void *opaque, uint32_t addr) |
337 | 80cabfad | bellard | { |
338 | b41a2cd1 | bellard | RTCState *s = opaque; |
339 | 80cabfad | bellard | int ret;
|
340 | 80cabfad | bellard | if ((addr & 1) == 0) { |
341 | 80cabfad | bellard | return 0xff; |
342 | 80cabfad | bellard | } else {
|
343 | 80cabfad | bellard | switch(s->cmos_index) {
|
344 | 80cabfad | bellard | case RTC_SECONDS:
|
345 | 80cabfad | bellard | case RTC_MINUTES:
|
346 | 80cabfad | bellard | case RTC_HOURS:
|
347 | 80cabfad | bellard | case RTC_DAY_OF_WEEK:
|
348 | 80cabfad | bellard | case RTC_DAY_OF_MONTH:
|
349 | 80cabfad | bellard | case RTC_MONTH:
|
350 | 80cabfad | bellard | case RTC_YEAR:
|
351 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
352 | 80cabfad | bellard | break;
|
353 | 80cabfad | bellard | case RTC_REG_A:
|
354 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
355 | 80cabfad | bellard | break;
|
356 | 80cabfad | bellard | case RTC_REG_C:
|
357 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
358 | d537cf6c | pbrook | qemu_irq_lower(s->irq); |
359 | 5fafdf24 | ths | s->cmos_data[RTC_REG_C] = 0x00;
|
360 | 80cabfad | bellard | break;
|
361 | 80cabfad | bellard | default:
|
362 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
363 | 80cabfad | bellard | break;
|
364 | 80cabfad | bellard | } |
365 | 80cabfad | bellard | #ifdef DEBUG_CMOS
|
366 | 80cabfad | bellard | printf("cmos: read index=0x%02x val=0x%02x\n",
|
367 | 80cabfad | bellard | s->cmos_index, ret); |
368 | 80cabfad | bellard | #endif
|
369 | 80cabfad | bellard | return ret;
|
370 | 80cabfad | bellard | } |
371 | 80cabfad | bellard | } |
372 | 80cabfad | bellard | |
373 | dff38e7b | bellard | void rtc_set_memory(RTCState *s, int addr, int val) |
374 | dff38e7b | bellard | { |
375 | dff38e7b | bellard | if (addr >= 0 && addr <= 127) |
376 | dff38e7b | bellard | s->cmos_data[addr] = val; |
377 | dff38e7b | bellard | } |
378 | dff38e7b | bellard | |
379 | dff38e7b | bellard | void rtc_set_date(RTCState *s, const struct tm *tm) |
380 | dff38e7b | bellard | { |
381 | 43f493af | bellard | s->current_tm = *tm; |
382 | dff38e7b | bellard | rtc_copy_date(s); |
383 | dff38e7b | bellard | } |
384 | dff38e7b | bellard | |
385 | ea55ffb3 | ths | /* PC cmos mappings */
|
386 | ea55ffb3 | ths | #define REG_IBM_CENTURY_BYTE 0x32 |
387 | ea55ffb3 | ths | #define REG_IBM_PS2_CENTURY_BYTE 0x37 |
388 | ea55ffb3 | ths | |
389 | ea55ffb3 | ths | void rtc_set_date_from_host(RTCState *s)
|
390 | ea55ffb3 | ths | { |
391 | ea55ffb3 | ths | time_t ti; |
392 | ea55ffb3 | ths | struct tm *tm;
|
393 | ea55ffb3 | ths | int val;
|
394 | ea55ffb3 | ths | |
395 | ea55ffb3 | ths | /* set the CMOS date */
|
396 | ea55ffb3 | ths | time(&ti); |
397 | ea55ffb3 | ths | if (rtc_utc)
|
398 | ea55ffb3 | ths | tm = gmtime(&ti); |
399 | ea55ffb3 | ths | else
|
400 | ea55ffb3 | ths | tm = localtime(&ti); |
401 | ea55ffb3 | ths | rtc_set_date(s, tm); |
402 | ea55ffb3 | ths | |
403 | ea55ffb3 | ths | val = to_bcd(s, (tm->tm_year / 100) + 19); |
404 | ea55ffb3 | ths | rtc_set_memory(s, REG_IBM_CENTURY_BYTE, val); |
405 | ea55ffb3 | ths | rtc_set_memory(s, REG_IBM_PS2_CENTURY_BYTE, val); |
406 | ea55ffb3 | ths | } |
407 | ea55ffb3 | ths | |
408 | dff38e7b | bellard | static void rtc_save(QEMUFile *f, void *opaque) |
409 | dff38e7b | bellard | { |
410 | dff38e7b | bellard | RTCState *s = opaque; |
411 | dff38e7b | bellard | |
412 | dff38e7b | bellard | qemu_put_buffer(f, s->cmos_data, 128);
|
413 | dff38e7b | bellard | qemu_put_8s(f, &s->cmos_index); |
414 | 5fafdf24 | ths | |
415 | 43f493af | bellard | qemu_put_be32s(f, &s->current_tm.tm_sec); |
416 | 43f493af | bellard | qemu_put_be32s(f, &s->current_tm.tm_min); |
417 | 43f493af | bellard | qemu_put_be32s(f, &s->current_tm.tm_hour); |
418 | 43f493af | bellard | qemu_put_be32s(f, &s->current_tm.tm_wday); |
419 | 43f493af | bellard | qemu_put_be32s(f, &s->current_tm.tm_mday); |
420 | 43f493af | bellard | qemu_put_be32s(f, &s->current_tm.tm_mon); |
421 | 43f493af | bellard | qemu_put_be32s(f, &s->current_tm.tm_year); |
422 | dff38e7b | bellard | |
423 | dff38e7b | bellard | qemu_put_timer(f, s->periodic_timer); |
424 | dff38e7b | bellard | qemu_put_be64s(f, &s->next_periodic_time); |
425 | dff38e7b | bellard | |
426 | dff38e7b | bellard | qemu_put_be64s(f, &s->next_second_time); |
427 | dff38e7b | bellard | qemu_put_timer(f, s->second_timer); |
428 | dff38e7b | bellard | qemu_put_timer(f, s->second_timer2); |
429 | 80cabfad | bellard | } |
430 | 80cabfad | bellard | |
431 | dff38e7b | bellard | static int rtc_load(QEMUFile *f, void *opaque, int version_id) |
432 | 80cabfad | bellard | { |
433 | dff38e7b | bellard | RTCState *s = opaque; |
434 | dff38e7b | bellard | |
435 | dff38e7b | bellard | if (version_id != 1) |
436 | dff38e7b | bellard | return -EINVAL;
|
437 | 80cabfad | bellard | |
438 | dff38e7b | bellard | qemu_get_buffer(f, s->cmos_data, 128);
|
439 | dff38e7b | bellard | qemu_get_8s(f, &s->cmos_index); |
440 | 43f493af | bellard | |
441 | 43f493af | bellard | qemu_get_be32s(f, &s->current_tm.tm_sec); |
442 | 43f493af | bellard | qemu_get_be32s(f, &s->current_tm.tm_min); |
443 | 43f493af | bellard | qemu_get_be32s(f, &s->current_tm.tm_hour); |
444 | 43f493af | bellard | qemu_get_be32s(f, &s->current_tm.tm_wday); |
445 | 43f493af | bellard | qemu_get_be32s(f, &s->current_tm.tm_mday); |
446 | 43f493af | bellard | qemu_get_be32s(f, &s->current_tm.tm_mon); |
447 | 43f493af | bellard | qemu_get_be32s(f, &s->current_tm.tm_year); |
448 | dff38e7b | bellard | |
449 | dff38e7b | bellard | qemu_get_timer(f, s->periodic_timer); |
450 | dff38e7b | bellard | qemu_get_be64s(f, &s->next_periodic_time); |
451 | dff38e7b | bellard | |
452 | dff38e7b | bellard | qemu_get_be64s(f, &s->next_second_time); |
453 | dff38e7b | bellard | qemu_get_timer(f, s->second_timer); |
454 | dff38e7b | bellard | qemu_get_timer(f, s->second_timer2); |
455 | dff38e7b | bellard | return 0; |
456 | dff38e7b | bellard | } |
457 | dff38e7b | bellard | |
458 | d537cf6c | pbrook | RTCState *rtc_init(int base, qemu_irq irq)
|
459 | dff38e7b | bellard | { |
460 | dff38e7b | bellard | RTCState *s; |
461 | dff38e7b | bellard | |
462 | dff38e7b | bellard | s = qemu_mallocz(sizeof(RTCState));
|
463 | dff38e7b | bellard | if (!s)
|
464 | dff38e7b | bellard | return NULL; |
465 | 80cabfad | bellard | |
466 | 80cabfad | bellard | s->irq = irq; |
467 | 80cabfad | bellard | s->cmos_data[RTC_REG_A] = 0x26;
|
468 | 80cabfad | bellard | s->cmos_data[RTC_REG_B] = 0x02;
|
469 | 80cabfad | bellard | s->cmos_data[RTC_REG_C] = 0x00;
|
470 | 80cabfad | bellard | s->cmos_data[RTC_REG_D] = 0x80;
|
471 | 80cabfad | bellard | |
472 | ea55ffb3 | ths | rtc_set_date_from_host(s); |
473 | ea55ffb3 | ths | |
474 | 5fafdf24 | ths | s->periodic_timer = qemu_new_timer(vm_clock, |
475 | dff38e7b | bellard | rtc_periodic_timer, s); |
476 | 5fafdf24 | ths | s->second_timer = qemu_new_timer(vm_clock, |
477 | dff38e7b | bellard | rtc_update_second, s); |
478 | 5fafdf24 | ths | s->second_timer2 = qemu_new_timer(vm_clock, |
479 | dff38e7b | bellard | rtc_update_second2, s); |
480 | dff38e7b | bellard | |
481 | dff38e7b | bellard | s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100; |
482 | dff38e7b | bellard | qemu_mod_timer(s->second_timer2, s->next_second_time); |
483 | dff38e7b | bellard | |
484 | b41a2cd1 | bellard | register_ioport_write(base, 2, 1, cmos_ioport_write, s); |
485 | b41a2cd1 | bellard | register_ioport_read(base, 2, 1, cmos_ioport_read, s); |
486 | dff38e7b | bellard | |
487 | dff38e7b | bellard | register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s); |
488 | dff38e7b | bellard | return s;
|
489 | 80cabfad | bellard | } |
490 | 80cabfad | bellard | |
491 | 2ca9d013 | ths | /* Memory mapped interface */
|
492 | 2ca9d013 | ths | uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr)
|
493 | 2ca9d013 | ths | { |
494 | 2ca9d013 | ths | RTCState *s = opaque; |
495 | 2ca9d013 | ths | |
496 | 18c6e2ff | ths | return cmos_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF; |
497 | 2ca9d013 | ths | } |
498 | 2ca9d013 | ths | |
499 | 2ca9d013 | ths | void cmos_mm_writeb (void *opaque, |
500 | 2ca9d013 | ths | target_phys_addr_t addr, uint32_t value) |
501 | 2ca9d013 | ths | { |
502 | 2ca9d013 | ths | RTCState *s = opaque; |
503 | 2ca9d013 | ths | |
504 | 18c6e2ff | ths | cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
|
505 | 2ca9d013 | ths | } |
506 | 2ca9d013 | ths | |
507 | 2ca9d013 | ths | uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr)
|
508 | 2ca9d013 | ths | { |
509 | 2ca9d013 | ths | RTCState *s = opaque; |
510 | 18c6e2ff | ths | uint32_t val; |
511 | 2ca9d013 | ths | |
512 | 18c6e2ff | ths | val = cmos_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
|
513 | 18c6e2ff | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
514 | 18c6e2ff | ths | val = bswap16(val); |
515 | 18c6e2ff | ths | #endif
|
516 | 18c6e2ff | ths | return val;
|
517 | 2ca9d013 | ths | } |
518 | 2ca9d013 | ths | |
519 | 2ca9d013 | ths | void cmos_mm_writew (void *opaque, |
520 | 2ca9d013 | ths | target_phys_addr_t addr, uint32_t value) |
521 | 2ca9d013 | ths | { |
522 | 2ca9d013 | ths | RTCState *s = opaque; |
523 | 18c6e2ff | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
524 | 18c6e2ff | ths | value = bswap16(value); |
525 | 18c6e2ff | ths | #endif
|
526 | 18c6e2ff | ths | cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
|
527 | 2ca9d013 | ths | } |
528 | 2ca9d013 | ths | |
529 | 2ca9d013 | ths | uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr)
|
530 | 2ca9d013 | ths | { |
531 | 2ca9d013 | ths | RTCState *s = opaque; |
532 | 18c6e2ff | ths | uint32_t val; |
533 | 2ca9d013 | ths | |
534 | 18c6e2ff | ths | val = cmos_ioport_read(s, (addr - s->base) >> s->it_shift); |
535 | 18c6e2ff | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
536 | 18c6e2ff | ths | val = bswap32(val); |
537 | 18c6e2ff | ths | #endif
|
538 | 18c6e2ff | ths | return val;
|
539 | 2ca9d013 | ths | } |
540 | 2ca9d013 | ths | |
541 | 2ca9d013 | ths | void cmos_mm_writel (void *opaque, |
542 | 2ca9d013 | ths | target_phys_addr_t addr, uint32_t value) |
543 | 2ca9d013 | ths | { |
544 | 2ca9d013 | ths | RTCState *s = opaque; |
545 | 18c6e2ff | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
546 | 18c6e2ff | ths | value = bswap32(value); |
547 | 18c6e2ff | ths | #endif
|
548 | 18c6e2ff | ths | cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value); |
549 | 2ca9d013 | ths | } |
550 | 2ca9d013 | ths | |
551 | 2ca9d013 | ths | static CPUReadMemoryFunc *rtc_mm_read[] = {
|
552 | 2ca9d013 | ths | &cmos_mm_readb, |
553 | 2ca9d013 | ths | &cmos_mm_readw, |
554 | 2ca9d013 | ths | &cmos_mm_readl, |
555 | 2ca9d013 | ths | }; |
556 | 2ca9d013 | ths | |
557 | 2ca9d013 | ths | static CPUWriteMemoryFunc *rtc_mm_write[] = {
|
558 | 2ca9d013 | ths | &cmos_mm_writeb, |
559 | 2ca9d013 | ths | &cmos_mm_writew, |
560 | 2ca9d013 | ths | &cmos_mm_writel, |
561 | 2ca9d013 | ths | }; |
562 | 2ca9d013 | ths | |
563 | 18c6e2ff | ths | RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq)
|
564 | 2ca9d013 | ths | { |
565 | 2ca9d013 | ths | RTCState *s; |
566 | 2ca9d013 | ths | int io_memory;
|
567 | 2ca9d013 | ths | |
568 | 2ca9d013 | ths | s = qemu_mallocz(sizeof(RTCState));
|
569 | 2ca9d013 | ths | if (!s)
|
570 | 2ca9d013 | ths | return NULL; |
571 | 2ca9d013 | ths | |
572 | 2ca9d013 | ths | s->irq = irq; |
573 | 2ca9d013 | ths | s->cmos_data[RTC_REG_A] = 0x26;
|
574 | 2ca9d013 | ths | s->cmos_data[RTC_REG_B] = 0x02;
|
575 | 2ca9d013 | ths | s->cmos_data[RTC_REG_C] = 0x00;
|
576 | 2ca9d013 | ths | s->cmos_data[RTC_REG_D] = 0x80;
|
577 | 2ca9d013 | ths | s->base = base; |
578 | 2ca9d013 | ths | |
579 | 2ca9d013 | ths | rtc_set_date_from_host(s); |
580 | 2ca9d013 | ths | |
581 | 2ca9d013 | ths | s->periodic_timer = qemu_new_timer(vm_clock, |
582 | 2ca9d013 | ths | rtc_periodic_timer, s); |
583 | 2ca9d013 | ths | s->second_timer = qemu_new_timer(vm_clock, |
584 | 2ca9d013 | ths | rtc_update_second, s); |
585 | 2ca9d013 | ths | s->second_timer2 = qemu_new_timer(vm_clock, |
586 | 2ca9d013 | ths | rtc_update_second2, s); |
587 | 2ca9d013 | ths | |
588 | 2ca9d013 | ths | s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100; |
589 | 2ca9d013 | ths | qemu_mod_timer(s->second_timer2, s->next_second_time); |
590 | 2ca9d013 | ths | |
591 | 2ca9d013 | ths | io_memory = cpu_register_io_memory(0, rtc_mm_read, rtc_mm_write, s);
|
592 | 18c6e2ff | ths | cpu_register_physical_memory(base, 2 << it_shift, io_memory);
|
593 | 2ca9d013 | ths | |
594 | 2ca9d013 | ths | register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s); |
595 | 2ca9d013 | ths | return s;
|
596 | 2ca9d013 | ths | } |