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/*
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 *  Software MMU support
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 *
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 *  Copyright (c) 2003 Fabrice Bellard
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#define DATA_SIZE (1 << SHIFT)
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#if DATA_SIZE == 8
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#define SUFFIX q
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#define USUFFIX q
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#define DATA_TYPE uint64_t
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#elif DATA_SIZE == 4
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#define SUFFIX l
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#define USUFFIX l
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#define DATA_TYPE uint32_t
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#elif DATA_SIZE == 2
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#define SUFFIX w
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#define USUFFIX uw
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#define DATA_TYPE uint16_t
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#elif DATA_SIZE == 1
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#define SUFFIX b
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#define USUFFIX ub
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#define DATA_TYPE uint8_t
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#else
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#error unsupported data size
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#endif
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#ifdef SOFTMMU_CODE_ACCESS
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#define READ_ACCESS_TYPE 2
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#define ADDR_READ addr_code
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#else
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#define READ_ACCESS_TYPE 0
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#define ADDR_READ addr_read
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#endif
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static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
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                                                        int is_user,
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                                                        void *retaddr);
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static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
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                                              target_ulong tlb_addr)
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{
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    DATA_TYPE res;
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    int index;
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    index = (tlb_addr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
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#if SHIFT <= 2
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    res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr);
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#else
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#ifdef TARGET_WORDS_BIGENDIAN
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    res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32;
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    res |= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4);
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#else
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    res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
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    res |= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32;
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#endif
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#endif /* SHIFT > 2 */
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#ifdef USE_KQEMU
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    env->last_io_time = cpu_get_time_fast();
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#endif
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    return res;
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}
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/* handle all cases except unaligned access which span two pages */
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DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
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                                                         int is_user)
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{
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    DATA_TYPE res;
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    int index;
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    target_ulong tlb_addr;
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    target_phys_addr_t physaddr;
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    void *retaddr;
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    /* test if there is match for unaligned or IO access */
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    /* XXX: could done more in memory macro in a non portable way */
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    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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 redo:
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    tlb_addr = env->tlb_table[is_user][index].ADDR_READ;
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    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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        physaddr = addr + env->tlb_table[is_user][index].addend;
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        if (tlb_addr & ~TARGET_PAGE_MASK) {
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            /* IO access */
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            if ((addr & (DATA_SIZE - 1)) != 0)
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                goto do_unaligned_access;
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            res = glue(io_read, SUFFIX)(physaddr, tlb_addr);
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        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
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            /* slow unaligned access (it spans two pages or IO) */
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        do_unaligned_access:
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            retaddr = GETPC();
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#ifdef ALIGNED_ONLY
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            do_unaligned_access(addr, READ_ACCESS_TYPE, is_user, retaddr);
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#endif
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            res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr,
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                                                         is_user, retaddr);
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        } else {
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            /* unaligned/aligned access in the same page */
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#ifdef ALIGNED_ONLY
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            if ((addr & (DATA_SIZE - 1)) != 0) {
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                retaddr = GETPC();
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                do_unaligned_access(addr, READ_ACCESS_TYPE, is_user, retaddr);
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            }
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#endif
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            res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)physaddr);
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        }
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    } else {
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        /* the page is not in the TLB : fill it */
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        retaddr = GETPC();
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#ifdef ALIGNED_ONLY
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        if ((addr & (DATA_SIZE - 1)) != 0)
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            do_unaligned_access(addr, READ_ACCESS_TYPE, is_user, retaddr);
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#endif
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        tlb_fill(addr, READ_ACCESS_TYPE, is_user, retaddr);
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        goto redo;
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    }
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    return res;
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}
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/* handle all unaligned cases */
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static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
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                                                        int is_user,
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                                                        void *retaddr)
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{
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    DATA_TYPE res, res1, res2;
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    int index, shift;
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    target_phys_addr_t physaddr;
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    target_ulong tlb_addr, addr1, addr2;
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    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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 redo:
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    tlb_addr = env->tlb_table[is_user][index].ADDR_READ;
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    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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        physaddr = addr + env->tlb_table[is_user][index].addend;
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        if (tlb_addr & ~TARGET_PAGE_MASK) {
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            /* IO access */
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            if ((addr & (DATA_SIZE - 1)) != 0)
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                goto do_unaligned_access;
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            res = glue(io_read, SUFFIX)(physaddr, tlb_addr);
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        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
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        do_unaligned_access:
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            /* slow unaligned access (it spans two pages) */
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            addr1 = addr & ~(DATA_SIZE - 1);
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            addr2 = addr1 + DATA_SIZE;
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            res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1,
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                                                          is_user, retaddr);
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            res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2,
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                                                          is_user, retaddr);
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            shift = (addr & (DATA_SIZE - 1)) * 8;
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#ifdef TARGET_WORDS_BIGENDIAN
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            res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
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#else
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            res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
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#endif
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            res = (DATA_TYPE)res;
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        } else {
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            /* unaligned/aligned access in the same page */
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            res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)physaddr);
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        }
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    } else {
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        /* the page is not in the TLB : fill it */
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        tlb_fill(addr, READ_ACCESS_TYPE, is_user, retaddr);
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        goto redo;
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    }
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    return res;
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}
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#ifndef SOFTMMU_CODE_ACCESS
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static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
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                                                   DATA_TYPE val,
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                                                   int is_user,
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                                                   void *retaddr);
185 b769d8fe bellard
186 5fafdf24 ths
static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
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                                          DATA_TYPE val,
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                                          target_ulong tlb_addr,
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                                          void *retaddr)
190 b769d8fe bellard
{
191 b769d8fe bellard
    int index;
192 b769d8fe bellard
193 b769d8fe bellard
    index = (tlb_addr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
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    env->mem_write_vaddr = tlb_addr;
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    env->mem_write_pc = (unsigned long)retaddr;
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#if SHIFT <= 2
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    io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val);
198 b769d8fe bellard
#else
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#ifdef TARGET_WORDS_BIGENDIAN
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    io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32);
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    io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val);
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#else
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    io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
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    io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32);
205 b769d8fe bellard
#endif
206 b769d8fe bellard
#endif /* SHIFT > 2 */
207 f1c85677 bellard
#ifdef USE_KQEMU
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    env->last_io_time = cpu_get_time_fast();
209 f1c85677 bellard
#endif
210 b769d8fe bellard
}
211 b92e5a22 bellard
212 5fafdf24 ths
void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
213 61382a50 bellard
                                                    DATA_TYPE val,
214 61382a50 bellard
                                                    int is_user)
215 b92e5a22 bellard
{
216 108c49b8 bellard
    target_phys_addr_t physaddr;
217 c27004ec bellard
    target_ulong tlb_addr;
218 b92e5a22 bellard
    void *retaddr;
219 61382a50 bellard
    int index;
220 5fafdf24 ths
   
221 b92e5a22 bellard
    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
222 b92e5a22 bellard
 redo:
223 84b7b8e7 bellard
    tlb_addr = env->tlb_table[is_user][index].addr_write;
224 b92e5a22 bellard
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
225 84b7b8e7 bellard
        physaddr = addr + env->tlb_table[is_user][index].addend;
226 b92e5a22 bellard
        if (tlb_addr & ~TARGET_PAGE_MASK) {
227 b92e5a22 bellard
            /* IO access */
228 b92e5a22 bellard
            if ((addr & (DATA_SIZE - 1)) != 0)
229 b92e5a22 bellard
                goto do_unaligned_access;
230 d720b93d bellard
            retaddr = GETPC();
231 d720b93d bellard
            glue(io_write, SUFFIX)(physaddr, val, tlb_addr, retaddr);
232 98699967 bellard
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
233 b92e5a22 bellard
        do_unaligned_access:
234 61382a50 bellard
            retaddr = GETPC();
235 a64d4718 bellard
#ifdef ALIGNED_ONLY
236 a64d4718 bellard
            do_unaligned_access(addr, 1, is_user, retaddr);
237 a64d4718 bellard
#endif
238 5fafdf24 ths
            glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val,
239 61382a50 bellard
                                                   is_user, retaddr);
240 b92e5a22 bellard
        } else {
241 b92e5a22 bellard
            /* aligned/unaligned access in the same page */
242 a64d4718 bellard
#ifdef ALIGNED_ONLY
243 a64d4718 bellard
            if ((addr & (DATA_SIZE - 1)) != 0) {
244 a64d4718 bellard
                retaddr = GETPC();
245 a64d4718 bellard
                do_unaligned_access(addr, 1, is_user, retaddr);
246 a64d4718 bellard
            }
247 a64d4718 bellard
#endif
248 108c49b8 bellard
            glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)physaddr, val);
249 b92e5a22 bellard
        }
250 b92e5a22 bellard
    } else {
251 b92e5a22 bellard
        /* the page is not in the TLB : fill it */
252 61382a50 bellard
        retaddr = GETPC();
253 a64d4718 bellard
#ifdef ALIGNED_ONLY
254 a64d4718 bellard
        if ((addr & (DATA_SIZE - 1)) != 0)
255 a64d4718 bellard
            do_unaligned_access(addr, 1, is_user, retaddr);
256 a64d4718 bellard
#endif
257 61382a50 bellard
        tlb_fill(addr, 1, is_user, retaddr);
258 b92e5a22 bellard
        goto redo;
259 b92e5a22 bellard
    }
260 b92e5a22 bellard
}
261 b92e5a22 bellard
262 b92e5a22 bellard
/* handles all unaligned cases */
263 5fafdf24 ths
static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
264 61382a50 bellard
                                                   DATA_TYPE val,
265 61382a50 bellard
                                                   int is_user,
266 61382a50 bellard
                                                   void *retaddr)
267 b92e5a22 bellard
{
268 108c49b8 bellard
    target_phys_addr_t physaddr;
269 c27004ec bellard
    target_ulong tlb_addr;
270 61382a50 bellard
    int index, i;
271 b92e5a22 bellard
272 b92e5a22 bellard
    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
273 b92e5a22 bellard
 redo:
274 84b7b8e7 bellard
    tlb_addr = env->tlb_table[is_user][index].addr_write;
275 b92e5a22 bellard
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
276 84b7b8e7 bellard
        physaddr = addr + env->tlb_table[is_user][index].addend;
277 b92e5a22 bellard
        if (tlb_addr & ~TARGET_PAGE_MASK) {
278 b92e5a22 bellard
            /* IO access */
279 b92e5a22 bellard
            if ((addr & (DATA_SIZE - 1)) != 0)
280 b92e5a22 bellard
                goto do_unaligned_access;
281 d720b93d bellard
            glue(io_write, SUFFIX)(physaddr, val, tlb_addr, retaddr);
282 98699967 bellard
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
283 b92e5a22 bellard
        do_unaligned_access:
284 b92e5a22 bellard
            /* XXX: not efficient, but simple */
285 b92e5a22 bellard
            for(i = 0;i < DATA_SIZE; i++) {
286 b92e5a22 bellard
#ifdef TARGET_WORDS_BIGENDIAN
287 5fafdf24 ths
                glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
288 61382a50 bellard
                                          is_user, retaddr);
289 b92e5a22 bellard
#else
290 5fafdf24 ths
                glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8),
291 61382a50 bellard
                                          is_user, retaddr);
292 b92e5a22 bellard
#endif
293 b92e5a22 bellard
            }
294 b92e5a22 bellard
        } else {
295 b92e5a22 bellard
            /* aligned/unaligned access in the same page */
296 108c49b8 bellard
            glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)physaddr, val);
297 b92e5a22 bellard
        }
298 b92e5a22 bellard
    } else {
299 b92e5a22 bellard
        /* the page is not in the TLB : fill it */
300 61382a50 bellard
        tlb_fill(addr, 1, is_user, retaddr);
301 b92e5a22 bellard
        goto redo;
302 b92e5a22 bellard
    }
303 b92e5a22 bellard
}
304 b92e5a22 bellard
305 b769d8fe bellard
#endif /* !defined(SOFTMMU_CODE_ACCESS) */
306 b769d8fe bellard
307 b769d8fe bellard
#undef READ_ACCESS_TYPE
308 b92e5a22 bellard
#undef SHIFT
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#undef DATA_TYPE
310 b92e5a22 bellard
#undef SUFFIX
311 61382a50 bellard
#undef USUFFIX
312 b92e5a22 bellard
#undef DATA_SIZE
313 84b7b8e7 bellard
#undef ADDR_READ