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1 | 2c0262af | bellard | /*
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2 | 2c0262af | bellard | * ARM virtual CPU header
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3 | 5fafdf24 | ths | *
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4 | 2c0262af | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 2c0262af | bellard | *
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6 | 2c0262af | bellard | * This library is free software; you can redistribute it and/or
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7 | 2c0262af | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 2c0262af | bellard | * License as published by the Free Software Foundation; either
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9 | 2c0262af | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 2c0262af | bellard | *
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11 | 2c0262af | bellard | * This library is distributed in the hope that it will be useful,
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12 | 2c0262af | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 2c0262af | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 2c0262af | bellard | * Lesser General Public License for more details.
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15 | 2c0262af | bellard | *
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16 | 2c0262af | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 2c0262af | bellard | * License along with this library; if not, write to the Free Software
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18 | 2c0262af | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 2c0262af | bellard | */
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20 | 2c0262af | bellard | #ifndef CPU_ARM_H
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21 | 2c0262af | bellard | #define CPU_ARM_H
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22 | 2c0262af | bellard | |
23 | 3cf1e035 | bellard | #define TARGET_LONG_BITS 32 |
24 | 3cf1e035 | bellard | |
25 | 9042c0e2 | ths | #define ELF_MACHINE EM_ARM
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26 | 9042c0e2 | ths | |
27 | 2c0262af | bellard | #include "cpu-defs.h" |
28 | 2c0262af | bellard | |
29 | 53cd6637 | bellard | #include "softfloat.h" |
30 | 53cd6637 | bellard | |
31 | 1fddef4b | bellard | #define TARGET_HAS_ICE 1 |
32 | 1fddef4b | bellard | |
33 | b8a9e8f1 | bellard | #define EXCP_UDEF 1 /* undefined instruction */ |
34 | b8a9e8f1 | bellard | #define EXCP_SWI 2 /* software interrupt */ |
35 | b8a9e8f1 | bellard | #define EXCP_PREFETCH_ABORT 3 |
36 | b8a9e8f1 | bellard | #define EXCP_DATA_ABORT 4 |
37 | b5ff1b31 | bellard | #define EXCP_IRQ 5 |
38 | b5ff1b31 | bellard | #define EXCP_FIQ 6 |
39 | 06c949e6 | pbrook | #define EXCP_BKPT 7 |
40 | 2c0262af | bellard | |
41 | c1713132 | balrog | typedef void ARMWriteCPFunc(void *opaque, int cp_info, |
42 | c1713132 | balrog | int srcreg, int operand, uint32_t value); |
43 | c1713132 | balrog | typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info, |
44 | c1713132 | balrog | int dstreg, int operand); |
45 | c1713132 | balrog | |
46 | b7bcbe95 | bellard | /* We currently assume float and double are IEEE single and double
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47 | b7bcbe95 | bellard | precision respectively.
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48 | b7bcbe95 | bellard | Doing runtime conversions is tricky because VFP registers may contain
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49 | b7bcbe95 | bellard | integer values (eg. as the result of a FTOSI instruction).
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50 | 8e96005d | bellard | s<2n> maps to the least significant half of d<n>
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51 | 8e96005d | bellard | s<2n+1> maps to the most significant half of d<n>
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52 | 8e96005d | bellard | */
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53 | b7bcbe95 | bellard | |
54 | 2c0262af | bellard | typedef struct CPUARMState { |
55 | b5ff1b31 | bellard | /* Regs for current mode. */
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56 | 2c0262af | bellard | uint32_t regs[16];
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57 | b5ff1b31 | bellard | /* Frequently accessed CPSR bits are stored separately for efficiently.
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58 | d37aca66 | pbrook | This contains all the other bits. Use cpsr_{read,write} to access
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59 | b5ff1b31 | bellard | the whole CPSR. */
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60 | b5ff1b31 | bellard | uint32_t uncached_cpsr; |
61 | b5ff1b31 | bellard | uint32_t spsr; |
62 | b5ff1b31 | bellard | |
63 | b5ff1b31 | bellard | /* Banked registers. */
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64 | b5ff1b31 | bellard | uint32_t banked_spsr[6];
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65 | b5ff1b31 | bellard | uint32_t banked_r13[6];
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66 | b5ff1b31 | bellard | uint32_t banked_r14[6];
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67 | 5fafdf24 | ths | |
68 | b5ff1b31 | bellard | /* These hold r8-r12. */
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69 | b5ff1b31 | bellard | uint32_t usr_regs[5];
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70 | b5ff1b31 | bellard | uint32_t fiq_regs[5];
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71 | 5fafdf24 | ths | |
72 | 2c0262af | bellard | /* cpsr flag cache for faster execution */
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73 | 2c0262af | bellard | uint32_t CF; /* 0 or 1 */
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74 | 2c0262af | bellard | uint32_t VF; /* V is the bit 31. All other bits are undefined */
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75 | 2c0262af | bellard | uint32_t NZF; /* N is bit 31. Z is computed from NZF */
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76 | 99c475ab | bellard | uint32_t QF; /* 0 or 1 */
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77 | 99c475ab | bellard | |
78 | 99c475ab | bellard | int thumb; /* 0 = arm mode, 1 = thumb mode */ |
79 | 2c0262af | bellard | |
80 | b5ff1b31 | bellard | /* System control coprocessor (cp15) */
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81 | b5ff1b31 | bellard | struct {
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82 | 40f137e1 | pbrook | uint32_t c0_cpuid; |
83 | c1713132 | balrog | uint32_t c0_cachetype; |
84 | b5ff1b31 | bellard | uint32_t c1_sys; /* System control register. */
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85 | b5ff1b31 | bellard | uint32_t c1_coproc; /* Coprocessor access register. */
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86 | 610c3c8a | balrog | uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
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87 | ce819861 | pbrook | uint32_t c2_base; /* MMU translation table base. */
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88 | ce819861 | pbrook | uint32_t c2_data; /* MPU data cachable bits. */
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89 | ce819861 | pbrook | uint32_t c2_insn; /* MPU instruction cachable bits. */
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90 | ce819861 | pbrook | uint32_t c3; /* MMU domain access control register
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91 | ce819861 | pbrook | MPU write buffer control. */
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92 | b5ff1b31 | bellard | uint32_t c5_insn; /* Fault status registers. */
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93 | b5ff1b31 | bellard | uint32_t c5_data; |
94 | ce819861 | pbrook | uint32_t c6_region[8]; /* MPU base/size registers. */ |
95 | b5ff1b31 | bellard | uint32_t c6_insn; /* Fault address registers. */
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96 | b5ff1b31 | bellard | uint32_t c6_data; |
97 | b5ff1b31 | bellard | uint32_t c9_insn; /* Cache lockdown registers. */
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98 | b5ff1b31 | bellard | uint32_t c9_data; |
99 | b5ff1b31 | bellard | uint32_t c13_fcse; /* FCSE PID. */
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100 | b5ff1b31 | bellard | uint32_t c13_context; /* Context ID. */
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101 | c1713132 | balrog | uint32_t c15_cpar; /* XScale Coprocessor Access Register */
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102 | c3d2689d | balrog | uint32_t c15_ticonfig; /* TI925T configuration byte. */
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103 | c3d2689d | balrog | uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
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104 | c3d2689d | balrog | uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
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105 | c3d2689d | balrog | uint32_t c15_threadid; /* TI debugger thread-ID. */
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106 | b5ff1b31 | bellard | } cp15; |
107 | 40f137e1 | pbrook | |
108 | c1713132 | balrog | /* Coprocessor IO used by peripherals */
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109 | c1713132 | balrog | struct {
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110 | c1713132 | balrog | ARMReadCPFunc *cp_read; |
111 | c1713132 | balrog | ARMWriteCPFunc *cp_write; |
112 | c1713132 | balrog | void *opaque;
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113 | c1713132 | balrog | } cp[15];
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114 | c1713132 | balrog | |
115 | 40f137e1 | pbrook | /* Internal CPU feature flags. */
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116 | 40f137e1 | pbrook | uint32_t features; |
117 | 40f137e1 | pbrook | |
118 | 2c0262af | bellard | /* exception/interrupt handling */
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119 | 2c0262af | bellard | jmp_buf jmp_env; |
120 | 2c0262af | bellard | int exception_index;
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121 | 2c0262af | bellard | int interrupt_request;
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122 | 2c0262af | bellard | int user_mode_only;
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123 | 9332f9da | bellard | int halted;
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124 | 2c0262af | bellard | |
125 | b7bcbe95 | bellard | /* VFP coprocessor state. */
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126 | b7bcbe95 | bellard | struct {
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127 | 8e96005d | bellard | float64 regs[16];
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128 | b7bcbe95 | bellard | |
129 | 40f137e1 | pbrook | uint32_t xregs[16];
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130 | b7bcbe95 | bellard | /* We store these fpcsr fields separately for convenience. */
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131 | b7bcbe95 | bellard | int vec_len;
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132 | b7bcbe95 | bellard | int vec_stride;
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133 | b7bcbe95 | bellard | |
134 | b7bcbe95 | bellard | /* Temporary variables if we don't have spare fp regs. */
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135 | 53cd6637 | bellard | float32 tmp0s, tmp1s; |
136 | 53cd6637 | bellard | float64 tmp0d, tmp1d; |
137 | 5fafdf24 | ths | |
138 | 53cd6637 | bellard | float_status fp_status; |
139 | b7bcbe95 | bellard | } vfp; |
140 | b7bcbe95 | bellard | |
141 | 18c9b560 | balrog | /* iwMMXt coprocessor state. */
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142 | 18c9b560 | balrog | struct {
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143 | 18c9b560 | balrog | uint64_t regs[16];
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144 | 18c9b560 | balrog | uint64_t val; |
145 | 18c9b560 | balrog | |
146 | 18c9b560 | balrog | uint32_t cregs[16];
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147 | 18c9b560 | balrog | } iwmmxt; |
148 | 18c9b560 | balrog | |
149 | ce4defa0 | pbrook | #if defined(CONFIG_USER_ONLY)
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150 | ce4defa0 | pbrook | /* For usermode syscall translation. */
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151 | ce4defa0 | pbrook | int eabi;
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152 | ce4defa0 | pbrook | #endif
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153 | ce4defa0 | pbrook | |
154 | a316d335 | bellard | CPU_COMMON |
155 | a316d335 | bellard | |
156 | 9d551997 | balrog | /* These fields after the common ones so they are preserved on reset. */
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157 | f3d6b95e | pbrook | int ram_size;
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158 | f3d6b95e | pbrook | const char *kernel_filename; |
159 | f3d6b95e | pbrook | const char *kernel_cmdline; |
160 | f3d6b95e | pbrook | const char *initrd_filename; |
161 | f3d6b95e | pbrook | int board_id;
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162 | 9d551997 | balrog | target_phys_addr_t loader_start; |
163 | 2c0262af | bellard | } CPUARMState; |
164 | 2c0262af | bellard | |
165 | 2c0262af | bellard | CPUARMState *cpu_arm_init(void);
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166 | 2c0262af | bellard | int cpu_arm_exec(CPUARMState *s);
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167 | 2c0262af | bellard | void cpu_arm_close(CPUARMState *s);
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168 | b5ff1b31 | bellard | void do_interrupt(CPUARMState *);
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169 | b5ff1b31 | bellard | void switch_mode(CPUARMState *, int); |
170 | b5ff1b31 | bellard | |
171 | 2c0262af | bellard | /* you can call this signal handler from your SIGBUS and SIGSEGV
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172 | 2c0262af | bellard | signal handlers to inform the virtual CPU of exceptions. non zero
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173 | 2c0262af | bellard | is returned if the signal was handled by the virtual CPU. */
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174 | 5fafdf24 | ths | int cpu_arm_signal_handler(int host_signum, void *pinfo, |
175 | 2c0262af | bellard | void *puc);
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176 | 2c0262af | bellard | |
177 | b5ff1b31 | bellard | #define CPSR_M (0x1f) |
178 | b5ff1b31 | bellard | #define CPSR_T (1 << 5) |
179 | b5ff1b31 | bellard | #define CPSR_F (1 << 6) |
180 | b5ff1b31 | bellard | #define CPSR_I (1 << 7) |
181 | b5ff1b31 | bellard | #define CPSR_A (1 << 8) |
182 | b5ff1b31 | bellard | #define CPSR_E (1 << 9) |
183 | b5ff1b31 | bellard | #define CPSR_IT_2_7 (0xfc00) |
184 | b5ff1b31 | bellard | /* Bits 20-23 reserved. */
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185 | b5ff1b31 | bellard | #define CPSR_J (1 << 24) |
186 | b5ff1b31 | bellard | #define CPSR_IT_0_1 (3 << 25) |
187 | b5ff1b31 | bellard | #define CPSR_Q (1 << 27) |
188 | b5ff1b31 | bellard | #define CPSR_NZCV (0xf << 28) |
189 | b5ff1b31 | bellard | |
190 | b5ff1b31 | bellard | #define CACHED_CPSR_BITS (CPSR_T | CPSR_Q | CPSR_NZCV)
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191 | b5ff1b31 | bellard | /* Return the current CPSR value. */
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192 | b5ff1b31 | bellard | static inline uint32_t cpsr_read(CPUARMState *env) |
193 | b5ff1b31 | bellard | { |
194 | b5ff1b31 | bellard | int ZF;
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195 | b5ff1b31 | bellard | ZF = (env->NZF == 0);
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196 | 5fafdf24 | ths | return env->uncached_cpsr | (env->NZF & 0x80000000) | (ZF << 30) | |
197 | b5ff1b31 | bellard | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
198 | b5ff1b31 | bellard | | (env->thumb << 5);
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199 | b5ff1b31 | bellard | } |
200 | b5ff1b31 | bellard | |
201 | b5ff1b31 | bellard | /* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */
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202 | b5ff1b31 | bellard | static inline void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) |
203 | b5ff1b31 | bellard | { |
204 | b5ff1b31 | bellard | /* NOTE: N = 1 and Z = 1 cannot be stored currently */
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205 | b5ff1b31 | bellard | if (mask & CPSR_NZCV) {
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206 | b5ff1b31 | bellard | env->NZF = (val & 0xc0000000) ^ 0x40000000; |
207 | b5ff1b31 | bellard | env->CF = (val >> 29) & 1; |
208 | b5ff1b31 | bellard | env->VF = (val << 3) & 0x80000000; |
209 | b5ff1b31 | bellard | } |
210 | b5ff1b31 | bellard | if (mask & CPSR_Q)
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211 | b5ff1b31 | bellard | env->QF = ((val & CPSR_Q) != 0);
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212 | b5ff1b31 | bellard | if (mask & CPSR_T)
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213 | b5ff1b31 | bellard | env->thumb = ((val & CPSR_T) != 0);
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214 | b5ff1b31 | bellard | |
215 | b5ff1b31 | bellard | if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
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216 | b5ff1b31 | bellard | switch_mode(env, val & CPSR_M); |
217 | b5ff1b31 | bellard | } |
218 | b5ff1b31 | bellard | mask &= ~CACHED_CPSR_BITS; |
219 | b5ff1b31 | bellard | env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); |
220 | b5ff1b31 | bellard | } |
221 | b5ff1b31 | bellard | |
222 | b5ff1b31 | bellard | enum arm_cpu_mode {
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223 | b5ff1b31 | bellard | ARM_CPU_MODE_USR = 0x10,
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224 | b5ff1b31 | bellard | ARM_CPU_MODE_FIQ = 0x11,
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225 | b5ff1b31 | bellard | ARM_CPU_MODE_IRQ = 0x12,
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226 | b5ff1b31 | bellard | ARM_CPU_MODE_SVC = 0x13,
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227 | b5ff1b31 | bellard | ARM_CPU_MODE_ABT = 0x17,
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228 | b5ff1b31 | bellard | ARM_CPU_MODE_UND = 0x1b,
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229 | b5ff1b31 | bellard | ARM_CPU_MODE_SYS = 0x1f
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230 | b5ff1b31 | bellard | }; |
231 | b5ff1b31 | bellard | |
232 | 40f137e1 | pbrook | /* VFP system registers. */
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233 | 40f137e1 | pbrook | #define ARM_VFP_FPSID 0 |
234 | 40f137e1 | pbrook | #define ARM_VFP_FPSCR 1 |
235 | 40f137e1 | pbrook | #define ARM_VFP_FPEXC 8 |
236 | 40f137e1 | pbrook | #define ARM_VFP_FPINST 9 |
237 | 40f137e1 | pbrook | #define ARM_VFP_FPINST2 10 |
238 | 40f137e1 | pbrook | |
239 | 18c9b560 | balrog | /* iwMMXt coprocessor control registers. */
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240 | 18c9b560 | balrog | #define ARM_IWMMXT_wCID 0 |
241 | 18c9b560 | balrog | #define ARM_IWMMXT_wCon 1 |
242 | 18c9b560 | balrog | #define ARM_IWMMXT_wCSSF 2 |
243 | 18c9b560 | balrog | #define ARM_IWMMXT_wCASF 3 |
244 | 18c9b560 | balrog | #define ARM_IWMMXT_wCGR0 8 |
245 | 18c9b560 | balrog | #define ARM_IWMMXT_wCGR1 9 |
246 | 18c9b560 | balrog | #define ARM_IWMMXT_wCGR2 10 |
247 | 18c9b560 | balrog | #define ARM_IWMMXT_wCGR3 11 |
248 | 18c9b560 | balrog | |
249 | 40f137e1 | pbrook | enum arm_features {
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250 | 40f137e1 | pbrook | ARM_FEATURE_VFP, |
251 | c1713132 | balrog | ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
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252 | c1713132 | balrog | ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
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253 | ce819861 | pbrook | ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
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254 | c3d2689d | balrog | ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */
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255 | c3d2689d | balrog | ARM_FEATURE_OMAPCP /* OMAP specific CP15 ops handling. */
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256 | 40f137e1 | pbrook | }; |
257 | 40f137e1 | pbrook | |
258 | 40f137e1 | pbrook | static inline int arm_feature(CPUARMState *env, int feature) |
259 | 40f137e1 | pbrook | { |
260 | 40f137e1 | pbrook | return (env->features & (1u << feature)) != 0; |
261 | 40f137e1 | pbrook | } |
262 | 40f137e1 | pbrook | |
263 | 5adb4839 | pbrook | void arm_cpu_list(void); |
264 | 3371d272 | pbrook | void cpu_arm_set_model(CPUARMState *env, const char *name); |
265 | 40f137e1 | pbrook | |
266 | c1713132 | balrog | void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, |
267 | c1713132 | balrog | ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write, |
268 | c1713132 | balrog | void *opaque);
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269 | c1713132 | balrog | |
270 | c1713132 | balrog | #define ARM_CPUID_ARM1026 0x4106a262 |
271 | c1713132 | balrog | #define ARM_CPUID_ARM926 0x41069265 |
272 | ce819861 | pbrook | #define ARM_CPUID_ARM946 0x41059461 |
273 | c3d2689d | balrog | #define ARM_CPUID_TI915T 0x54029152 |
274 | c3d2689d | balrog | #define ARM_CPUID_TI925T 0x54029252 |
275 | c1713132 | balrog | #define ARM_CPUID_PXA250 0x69052100 |
276 | c1713132 | balrog | #define ARM_CPUID_PXA255 0x69052d00 |
277 | c1713132 | balrog | #define ARM_CPUID_PXA260 0x69052903 |
278 | c1713132 | balrog | #define ARM_CPUID_PXA261 0x69052d05 |
279 | c1713132 | balrog | #define ARM_CPUID_PXA262 0x69052d06 |
280 | c1713132 | balrog | #define ARM_CPUID_PXA270 0x69054110 |
281 | c1713132 | balrog | #define ARM_CPUID_PXA270_A0 0x69054110 |
282 | c1713132 | balrog | #define ARM_CPUID_PXA270_A1 0x69054111 |
283 | c1713132 | balrog | #define ARM_CPUID_PXA270_B0 0x69054112 |
284 | c1713132 | balrog | #define ARM_CPUID_PXA270_B1 0x69054113 |
285 | c1713132 | balrog | #define ARM_CPUID_PXA270_C0 0x69054114 |
286 | c1713132 | balrog | #define ARM_CPUID_PXA270_C5 0x69054117 |
287 | 40f137e1 | pbrook | |
288 | b5ff1b31 | bellard | #if defined(CONFIG_USER_ONLY)
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289 | 2c0262af | bellard | #define TARGET_PAGE_BITS 12 |
290 | b5ff1b31 | bellard | #else
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291 | b5ff1b31 | bellard | /* The ARM MMU allows 1k pages. */
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292 | b5ff1b31 | bellard | /* ??? Linux doesn't actually use these, and they're deprecated in recent
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293 | 82d17978 | balrog | architecture revisions. Maybe a configure option to disable them. */
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294 | b5ff1b31 | bellard | #define TARGET_PAGE_BITS 10 |
295 | b5ff1b31 | bellard | #endif
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296 | 9467d44c | ths | |
297 | 9467d44c | ths | #define CPUState CPUARMState
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298 | 9467d44c | ths | #define cpu_init cpu_arm_init
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299 | 9467d44c | ths | #define cpu_exec cpu_arm_exec
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300 | 9467d44c | ths | #define cpu_gen_code cpu_arm_gen_code
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301 | 9467d44c | ths | #define cpu_signal_handler cpu_arm_signal_handler
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302 | 9467d44c | ths | |
303 | 2c0262af | bellard | #include "cpu-all.h" |
304 | 2c0262af | bellard | |
305 | 2c0262af | bellard | #endif |