Statistics
| Branch: | Revision:

root / target-arm / op_helper.c @ 5fafdf24

History | View | Annotate | Download (5.9 kB)

1 b7bcbe95 bellard
/*
2 b7bcbe95 bellard
 *  ARM helper routines
3 5fafdf24 ths
 *
4 b7bcbe95 bellard
 *  Copyright (c) 2005 CodeSourcery, LLC
5 b7bcbe95 bellard
 *
6 b7bcbe95 bellard
 * This library is free software; you can redistribute it and/or
7 b7bcbe95 bellard
 * modify it under the terms of the GNU Lesser General Public
8 b7bcbe95 bellard
 * License as published by the Free Software Foundation; either
9 b7bcbe95 bellard
 * version 2 of the License, or (at your option) any later version.
10 b7bcbe95 bellard
 *
11 b7bcbe95 bellard
 * This library is distributed in the hope that it will be useful,
12 b7bcbe95 bellard
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 b7bcbe95 bellard
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14 b7bcbe95 bellard
 * Lesser General Public License for more details.
15 b7bcbe95 bellard
 *
16 b7bcbe95 bellard
 * You should have received a copy of the GNU Lesser General Public
17 b7bcbe95 bellard
 * License along with this library; if not, write to the Free Software
18 b7bcbe95 bellard
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19 b7bcbe95 bellard
 */
20 b7bcbe95 bellard
#include "exec.h"
21 b7bcbe95 bellard
22 b7bcbe95 bellard
void raise_exception(int tt)
23 b7bcbe95 bellard
{
24 b7bcbe95 bellard
    env->exception_index = tt;
25 b7bcbe95 bellard
    cpu_loop_exit();
26 b7bcbe95 bellard
}
27 b7bcbe95 bellard
28 b7bcbe95 bellard
/* thread support */
29 b7bcbe95 bellard
30 b7bcbe95 bellard
spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
31 b7bcbe95 bellard
32 b7bcbe95 bellard
void cpu_lock(void)
33 b7bcbe95 bellard
{
34 b7bcbe95 bellard
    spin_lock(&global_cpu_lock);
35 b7bcbe95 bellard
}
36 b7bcbe95 bellard
37 b7bcbe95 bellard
void cpu_unlock(void)
38 b7bcbe95 bellard
{
39 b7bcbe95 bellard
    spin_unlock(&global_cpu_lock);
40 b7bcbe95 bellard
}
41 b7bcbe95 bellard
42 b7bcbe95 bellard
/* VFP support.  */
43 b7bcbe95 bellard
44 b7bcbe95 bellard
void do_vfp_abss(void)
45 b7bcbe95 bellard
{
46 53cd6637 bellard
    FT0s = float32_abs(FT0s);
47 b7bcbe95 bellard
}
48 b7bcbe95 bellard
49 b7bcbe95 bellard
void do_vfp_absd(void)
50 b7bcbe95 bellard
{
51 53cd6637 bellard
    FT0d = float64_abs(FT0d);
52 b7bcbe95 bellard
}
53 b7bcbe95 bellard
54 b7bcbe95 bellard
void do_vfp_sqrts(void)
55 b7bcbe95 bellard
{
56 53cd6637 bellard
    FT0s = float32_sqrt(FT0s, &env->vfp.fp_status);
57 b7bcbe95 bellard
}
58 b7bcbe95 bellard
59 b7bcbe95 bellard
void do_vfp_sqrtd(void)
60 b7bcbe95 bellard
{
61 53cd6637 bellard
    FT0d = float64_sqrt(FT0d, &env->vfp.fp_status);
62 b7bcbe95 bellard
}
63 b7bcbe95 bellard
64 53cd6637 bellard
/* XXX: check quiet/signaling case */
65 53cd6637 bellard
#define DO_VFP_cmp(p, size)               \
66 b7bcbe95 bellard
void do_vfp_cmp##p(void)                  \
67 b7bcbe95 bellard
{                                         \
68 b7bcbe95 bellard
    uint32_t flags;                       \
69 53cd6637 bellard
    switch(float ## size ## _compare_quiet(FT0##p, FT1##p, &env->vfp.fp_status)) {\
70 89344d5a bellard
    case 0: flags = 0x6; break;\
71 53cd6637 bellard
    case -1: flags = 0x8; break;\
72 53cd6637 bellard
    case 1: flags = 0x2; break;\
73 53cd6637 bellard
    default: case 2: flags = 0x3; break;\
74 53cd6637 bellard
    }\
75 40f137e1 pbrook
    env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28)\
76 40f137e1 pbrook
        | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
77 b7bcbe95 bellard
    FORCE_RET();                          \
78 53cd6637 bellard
}\
79 53cd6637 bellard
\
80 b7bcbe95 bellard
void do_vfp_cmpe##p(void)                   \
81 b7bcbe95 bellard
{                                           \
82 53cd6637 bellard
    uint32_t flags;                       \
83 53cd6637 bellard
    switch(float ## size ## _compare(FT0##p, FT1##p, &env->vfp.fp_status)) {\
84 89344d5a bellard
    case 0: flags = 0x6; break;\
85 53cd6637 bellard
    case -1: flags = 0x8; break;\
86 53cd6637 bellard
    case 1: flags = 0x2; break;\
87 53cd6637 bellard
    default: case 2: flags = 0x3; break;\
88 53cd6637 bellard
    }\
89 40f137e1 pbrook
    env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28)\
90 40f137e1 pbrook
        | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
91 53cd6637 bellard
    FORCE_RET();                          \
92 b7bcbe95 bellard
}
93 53cd6637 bellard
DO_VFP_cmp(s, 32)
94 53cd6637 bellard
DO_VFP_cmp(d, 64)
95 53cd6637 bellard
#undef DO_VFP_cmp
96 b7bcbe95 bellard
97 b7bcbe95 bellard
/* Convert host exception flags to vfp form.  */
98 53cd6637 bellard
static inline int vfp_exceptbits_from_host(int host_bits)
99 b7bcbe95 bellard
{
100 b7bcbe95 bellard
    int target_bits = 0;
101 b7bcbe95 bellard
102 53cd6637 bellard
    if (host_bits & float_flag_invalid)
103 b7bcbe95 bellard
        target_bits |= 1;
104 53cd6637 bellard
    if (host_bits & float_flag_divbyzero)
105 b7bcbe95 bellard
        target_bits |= 2;
106 53cd6637 bellard
    if (host_bits & float_flag_overflow)
107 b7bcbe95 bellard
        target_bits |= 4;
108 53cd6637 bellard
    if (host_bits & float_flag_underflow)
109 b7bcbe95 bellard
        target_bits |= 8;
110 53cd6637 bellard
    if (host_bits & float_flag_inexact)
111 b7bcbe95 bellard
        target_bits |= 0x10;
112 b7bcbe95 bellard
    return target_bits;
113 b7bcbe95 bellard
}
114 b7bcbe95 bellard
115 b7bcbe95 bellard
/* Convert vfp exception flags to target form.  */
116 53cd6637 bellard
static inline int vfp_exceptbits_to_host(int target_bits)
117 b7bcbe95 bellard
{
118 b7bcbe95 bellard
    int host_bits = 0;
119 b7bcbe95 bellard
120 b7bcbe95 bellard
    if (target_bits & 1)
121 53cd6637 bellard
        host_bits |= float_flag_invalid;
122 b7bcbe95 bellard
    if (target_bits & 2)
123 53cd6637 bellard
        host_bits |= float_flag_divbyzero;
124 b7bcbe95 bellard
    if (target_bits & 4)
125 53cd6637 bellard
        host_bits |= float_flag_overflow;
126 b7bcbe95 bellard
    if (target_bits & 8)
127 53cd6637 bellard
        host_bits |= float_flag_underflow;
128 b7bcbe95 bellard
    if (target_bits & 0x10)
129 53cd6637 bellard
        host_bits |= float_flag_inexact;
130 b7bcbe95 bellard
    return host_bits;
131 b7bcbe95 bellard
}
132 b7bcbe95 bellard
133 b7bcbe95 bellard
void do_vfp_set_fpscr(void)
134 b7bcbe95 bellard
{
135 b7bcbe95 bellard
    int i;
136 b7bcbe95 bellard
    uint32_t changed;
137 b7bcbe95 bellard
138 40f137e1 pbrook
    changed = env->vfp.xregs[ARM_VFP_FPSCR];
139 40f137e1 pbrook
    env->vfp.xregs[ARM_VFP_FPSCR] = (T0 & 0xffc8ffff);
140 b7bcbe95 bellard
    env->vfp.vec_len = (T0 >> 16) & 7;
141 b7bcbe95 bellard
    env->vfp.vec_stride = (T0 >> 20) & 3;
142 b7bcbe95 bellard
143 b7bcbe95 bellard
    changed ^= T0;
144 b7bcbe95 bellard
    if (changed & (3 << 22)) {
145 b7bcbe95 bellard
        i = (T0 >> 22) & 3;
146 b7bcbe95 bellard
        switch (i) {
147 b7bcbe95 bellard
        case 0:
148 53cd6637 bellard
            i = float_round_nearest_even;
149 b7bcbe95 bellard
            break;
150 b7bcbe95 bellard
        case 1:
151 53cd6637 bellard
            i = float_round_up;
152 b7bcbe95 bellard
            break;
153 b7bcbe95 bellard
        case 2:
154 53cd6637 bellard
            i = float_round_down;
155 b7bcbe95 bellard
            break;
156 b7bcbe95 bellard
        case 3:
157 53cd6637 bellard
            i = float_round_to_zero;
158 b7bcbe95 bellard
            break;
159 b7bcbe95 bellard
        }
160 53cd6637 bellard
        set_float_rounding_mode(i, &env->vfp.fp_status);
161 b7bcbe95 bellard
    }
162 b7bcbe95 bellard
163 53cd6637 bellard
    i = vfp_exceptbits_to_host((T0 >> 8) & 0x1f);
164 53cd6637 bellard
    set_float_exception_flags(i, &env->vfp.fp_status);
165 b7bcbe95 bellard
    /* XXX: FZ and DN are not implemented.  */
166 b7bcbe95 bellard
}
167 b7bcbe95 bellard
168 b7bcbe95 bellard
void do_vfp_get_fpscr(void)
169 b7bcbe95 bellard
{
170 b7bcbe95 bellard
    int i;
171 b7bcbe95 bellard
172 40f137e1 pbrook
    T0 = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff) | (env->vfp.vec_len << 16)
173 b7bcbe95 bellard
          | (env->vfp.vec_stride << 20);
174 53cd6637 bellard
    i = get_float_exception_flags(&env->vfp.fp_status);
175 b7bcbe95 bellard
    T0 |= vfp_exceptbits_from_host(i);
176 b7bcbe95 bellard
}
177 b5ff1b31 bellard
178 b5ff1b31 bellard
#if !defined(CONFIG_USER_ONLY)
179 b5ff1b31 bellard
180 b5ff1b31 bellard
#define MMUSUFFIX _mmu
181 b5ff1b31 bellard
#define GETPC() (__builtin_return_address(0))
182 b5ff1b31 bellard
183 b5ff1b31 bellard
#define SHIFT 0
184 b5ff1b31 bellard
#include "softmmu_template.h"
185 b5ff1b31 bellard
186 b5ff1b31 bellard
#define SHIFT 1
187 b5ff1b31 bellard
#include "softmmu_template.h"
188 b5ff1b31 bellard
189 b5ff1b31 bellard
#define SHIFT 2
190 b5ff1b31 bellard
#include "softmmu_template.h"
191 b5ff1b31 bellard
192 b5ff1b31 bellard
#define SHIFT 3
193 b5ff1b31 bellard
#include "softmmu_template.h"
194 b5ff1b31 bellard
195 b5ff1b31 bellard
/* try to fill the TLB and return an exception if error. If retaddr is
196 b5ff1b31 bellard
   NULL, it means that the function was called in C code (i.e. not
197 b5ff1b31 bellard
   from generated code or from helper.c) */
198 b5ff1b31 bellard
/* XXX: fix it to restore all registers */
199 b5ff1b31 bellard
void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
200 b5ff1b31 bellard
{
201 b5ff1b31 bellard
    TranslationBlock *tb;
202 b5ff1b31 bellard
    CPUState *saved_env;
203 b5ff1b31 bellard
    target_phys_addr_t pc;
204 b5ff1b31 bellard
    int ret;
205 b5ff1b31 bellard
206 b5ff1b31 bellard
    /* XXX: hack to restore env in all cases, even if not called from
207 b5ff1b31 bellard
       generated code */
208 b5ff1b31 bellard
    saved_env = env;
209 b5ff1b31 bellard
    env = cpu_single_env;
210 b5ff1b31 bellard
    ret = cpu_arm_handle_mmu_fault(env, addr, is_write, is_user, 1);
211 b5ff1b31 bellard
    if (__builtin_expect(ret, 0)) {
212 b5ff1b31 bellard
        if (retaddr) {
213 b5ff1b31 bellard
            /* now we have a real cpu fault */
214 b5ff1b31 bellard
            pc = (target_phys_addr_t)retaddr;
215 b5ff1b31 bellard
            tb = tb_find_pc(pc);
216 b5ff1b31 bellard
            if (tb) {
217 b5ff1b31 bellard
                /* the PC is inside the translated code. It means that we have
218 b5ff1b31 bellard
                   a virtual CPU fault */
219 b5ff1b31 bellard
                cpu_restore_state(tb, env, pc, NULL);
220 b5ff1b31 bellard
            }
221 b5ff1b31 bellard
        }
222 b5ff1b31 bellard
        raise_exception(env->exception_index);
223 b5ff1b31 bellard
    }
224 b5ff1b31 bellard
    env = saved_env;
225 b5ff1b31 bellard
}
226 b5ff1b31 bellard
227 b5ff1b31 bellard
#endif