root / target-mips / exec.h @ 5fafdf24
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1 | 6af0bf9c | bellard | #if !defined(__QEMU_MIPS_EXEC_H__)
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2 | 6af0bf9c | bellard | #define __QEMU_MIPS_EXEC_H__
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3 | 6af0bf9c | bellard | |
4 | 01dbbdf1 | bellard | //#define DEBUG_OP
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5 | 6af0bf9c | bellard | |
6 | c570fd16 | ths | #include "config.h" |
7 | 6af0bf9c | bellard | #include "mips-defs.h" |
8 | 6af0bf9c | bellard | #include "dyngen-exec.h" |
9 | 01179c38 | ths | #include "cpu-defs.h" |
10 | 6af0bf9c | bellard | |
11 | 6af0bf9c | bellard | register struct CPUMIPSState *env asm(AREG0); |
12 | 6af0bf9c | bellard | |
13 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
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14 | c570fd16 | ths | #define T0 (env->t0)
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15 | c570fd16 | ths | #define T1 (env->t1)
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16 | c570fd16 | ths | #define T2 (env->t2)
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17 | c570fd16 | ths | #else
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18 | 01179c38 | ths | register target_ulong T0 asm(AREG1); |
19 | 01179c38 | ths | register target_ulong T1 asm(AREG2); |
20 | 01179c38 | ths | register target_ulong T2 asm(AREG3); |
21 | c570fd16 | ths | #endif
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22 | 6af0bf9c | bellard | |
23 | 6af0bf9c | bellard | #if defined (USE_HOST_FLOAT_REGS)
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24 | 6ea83fed | bellard | #error "implement me." |
25 | 6af0bf9c | bellard | #else
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26 | ead9360e | ths | #define FDT0 (env->fpu->ft0.fd)
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27 | ead9360e | ths | #define FDT1 (env->fpu->ft1.fd)
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28 | ead9360e | ths | #define FDT2 (env->fpu->ft2.fd)
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29 | ead9360e | ths | #define FST0 (env->fpu->ft0.fs[FP_ENDIAN_IDX])
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30 | ead9360e | ths | #define FST1 (env->fpu->ft1.fs[FP_ENDIAN_IDX])
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31 | ead9360e | ths | #define FST2 (env->fpu->ft2.fs[FP_ENDIAN_IDX])
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32 | ead9360e | ths | #define FSTH0 (env->fpu->ft0.fs[!FP_ENDIAN_IDX])
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33 | ead9360e | ths | #define FSTH1 (env->fpu->ft1.fs[!FP_ENDIAN_IDX])
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34 | ead9360e | ths | #define FSTH2 (env->fpu->ft2.fs[!FP_ENDIAN_IDX])
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35 | ead9360e | ths | #define DT0 (env->fpu->ft0.d)
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36 | ead9360e | ths | #define DT1 (env->fpu->ft1.d)
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37 | ead9360e | ths | #define DT2 (env->fpu->ft2.d)
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38 | ead9360e | ths | #define WT0 (env->fpu->ft0.w[FP_ENDIAN_IDX])
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39 | ead9360e | ths | #define WT1 (env->fpu->ft1.w[FP_ENDIAN_IDX])
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40 | ead9360e | ths | #define WT2 (env->fpu->ft2.w[FP_ENDIAN_IDX])
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41 | ead9360e | ths | #define WTH0 (env->fpu->ft0.w[!FP_ENDIAN_IDX])
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42 | ead9360e | ths | #define WTH1 (env->fpu->ft1.w[!FP_ENDIAN_IDX])
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43 | ead9360e | ths | #define WTH2 (env->fpu->ft2.w[!FP_ENDIAN_IDX])
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44 | 6af0bf9c | bellard | #endif
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45 | 6af0bf9c | bellard | |
46 | 6af0bf9c | bellard | #if defined (DEBUG_OP)
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47 | 70ead434 | ths | # define RETURN() __asm__ __volatile__("nop" : : : "memory"); |
48 | 6af0bf9c | bellard | #else
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49 | 70ead434 | ths | # define RETURN() __asm__ __volatile__("" : : : "memory"); |
50 | 6af0bf9c | bellard | #endif
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51 | 6af0bf9c | bellard | |
52 | 6af0bf9c | bellard | #include "cpu.h" |
53 | 6af0bf9c | bellard | #include "exec-all.h" |
54 | 6af0bf9c | bellard | |
55 | 6af0bf9c | bellard | #if !defined(CONFIG_USER_ONLY)
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56 | a9049a07 | bellard | #include "softmmu_exec.h" |
57 | 6af0bf9c | bellard | #endif /* !defined(CONFIG_USER_ONLY) */ |
58 | 6af0bf9c | bellard | |
59 | 60aa19ab | ths | #ifdef TARGET_MIPS64
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60 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
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61 | c570fd16 | ths | void do_dsll (void); |
62 | c570fd16 | ths | void do_dsll32 (void); |
63 | c570fd16 | ths | void do_dsra (void); |
64 | c570fd16 | ths | void do_dsra32 (void); |
65 | c570fd16 | ths | void do_dsrl (void); |
66 | c570fd16 | ths | void do_dsrl32 (void); |
67 | c570fd16 | ths | void do_drotr (void); |
68 | c570fd16 | ths | void do_drotr32 (void); |
69 | c570fd16 | ths | void do_dsllv (void); |
70 | c570fd16 | ths | void do_dsrav (void); |
71 | c570fd16 | ths | void do_dsrlv (void); |
72 | c570fd16 | ths | void do_drotrv (void); |
73 | c570fd16 | ths | #endif
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74 | c570fd16 | ths | #endif
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75 | c570fd16 | ths | |
76 | 80c27194 | ths | #if HOST_LONG_BITS < 64 |
77 | 80c27194 | ths | void do_div (void); |
78 | 80c27194 | ths | #endif
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79 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
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80 | 6af0bf9c | bellard | void do_mult (void); |
81 | 6af0bf9c | bellard | void do_multu (void); |
82 | 6af0bf9c | bellard | void do_madd (void); |
83 | 6af0bf9c | bellard | void do_maddu (void); |
84 | 6af0bf9c | bellard | void do_msub (void); |
85 | 6af0bf9c | bellard | void do_msubu (void); |
86 | 80c27194 | ths | #endif
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87 | 80c27194 | ths | #ifdef TARGET_MIPS64
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88 | c570fd16 | ths | void do_ddiv (void); |
89 | 80c27194 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
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90 | c570fd16 | ths | void do_ddivu (void); |
91 | c570fd16 | ths | #endif
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92 | 6af0bf9c | bellard | #endif
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93 | 873eb012 | ths | void do_mfc0_random(void); |
94 | 873eb012 | ths | void do_mfc0_count(void); |
95 | 7a387fff | ths | void do_mtc0_entryhi(uint32_t in);
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96 | 8c0fdd85 | ths | void do_mtc0_status_debug(uint32_t old, uint32_t val);
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97 | 8c0fdd85 | ths | void do_mtc0_status_irqraise_debug(void); |
98 | 6ea83fed | bellard | void dump_fpu(CPUState *env);
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99 | 5fafdf24 | ths | void fpu_dump_state(CPUState *env, FILE *f,
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100 | 6ea83fed | bellard | int (*fpu_fprintf)(FILE *f, const char *fmt, ...), |
101 | 6ea83fed | bellard | int flags);
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102 | 6ea83fed | bellard | void dump_sc (void); |
103 | 4ad40f36 | bellard | void do_lwl_raw (uint32_t);
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104 | 4ad40f36 | bellard | void do_lwr_raw (uint32_t);
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105 | 4ad40f36 | bellard | uint32_t do_swl_raw (uint32_t); |
106 | 4ad40f36 | bellard | uint32_t do_swr_raw (uint32_t); |
107 | 60aa19ab | ths | #ifdef TARGET_MIPS64
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108 | c570fd16 | ths | void do_ldl_raw (uint64_t);
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109 | c570fd16 | ths | void do_ldr_raw (uint64_t);
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110 | c570fd16 | ths | uint64_t do_sdl_raw (uint64_t); |
111 | c570fd16 | ths | uint64_t do_sdr_raw (uint64_t); |
112 | c570fd16 | ths | #endif
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113 | 6af0bf9c | bellard | #if !defined(CONFIG_USER_ONLY)
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114 | 4ad40f36 | bellard | void do_lwl_user (uint32_t);
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115 | 4ad40f36 | bellard | void do_lwl_kernel (uint32_t);
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116 | 4ad40f36 | bellard | void do_lwr_user (uint32_t);
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117 | 4ad40f36 | bellard | void do_lwr_kernel (uint32_t);
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118 | 4ad40f36 | bellard | uint32_t do_swl_user (uint32_t); |
119 | 4ad40f36 | bellard | uint32_t do_swl_kernel (uint32_t); |
120 | 4ad40f36 | bellard | uint32_t do_swr_user (uint32_t); |
121 | 4ad40f36 | bellard | uint32_t do_swr_kernel (uint32_t); |
122 | 60aa19ab | ths | #ifdef TARGET_MIPS64
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123 | c570fd16 | ths | void do_ldl_user (uint64_t);
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124 | c570fd16 | ths | void do_ldl_kernel (uint64_t);
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125 | c570fd16 | ths | void do_ldr_user (uint64_t);
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126 | c570fd16 | ths | void do_ldr_kernel (uint64_t);
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127 | c570fd16 | ths | uint64_t do_sdl_user (uint64_t); |
128 | c570fd16 | ths | uint64_t do_sdl_kernel (uint64_t); |
129 | c570fd16 | ths | uint64_t do_sdr_user (uint64_t); |
130 | c570fd16 | ths | uint64_t do_sdr_kernel (uint64_t); |
131 | c570fd16 | ths | #endif
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132 | 6af0bf9c | bellard | #endif
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133 | 6af0bf9c | bellard | void do_pmon (int function); |
134 | 6af0bf9c | bellard | |
135 | d2ec1774 | pbrook | void dump_sc (void); |
136 | d2ec1774 | pbrook | |
137 | 6af0bf9c | bellard | int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
138 | 6af0bf9c | bellard | int is_user, int is_softmmu); |
139 | 6af0bf9c | bellard | void do_interrupt (CPUState *env);
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140 | 29929e34 | ths | void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra); |
141 | 6af0bf9c | bellard | |
142 | 6af0bf9c | bellard | void cpu_loop_exit(void); |
143 | 6af0bf9c | bellard | void do_raise_exception_err (uint32_t exception, int error_code); |
144 | 6af0bf9c | bellard | void do_raise_exception (uint32_t exception);
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145 | e397ee33 | ths | void do_raise_exception_direct_err (uint32_t exception, int error_code); |
146 | 4ad40f36 | bellard | void do_raise_exception_direct (uint32_t exception);
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147 | 6af0bf9c | bellard | |
148 | 5fafdf24 | ths | void cpu_dump_state(CPUState *env, FILE *f,
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149 | 6af0bf9c | bellard | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
150 | 6af0bf9c | bellard | int flags);
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151 | 6af0bf9c | bellard | void cpu_mips_irqctrl_init (void); |
152 | 6af0bf9c | bellard | uint32_t cpu_mips_get_random (CPUState *env); |
153 | 6af0bf9c | bellard | uint32_t cpu_mips_get_count (CPUState *env); |
154 | 6af0bf9c | bellard | void cpu_mips_store_count (CPUState *env, uint32_t value);
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155 | 6af0bf9c | bellard | void cpu_mips_store_compare (CPUState *env, uint32_t value);
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156 | a4bc3afc | ths | void cpu_mips_update_irq (CPUState *env);
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157 | 6af0bf9c | bellard | void cpu_mips_clock_init (CPUState *env);
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158 | 814b9a47 | ths | void cpu_mips_tlb_flush (CPUState *env, int flush_global); |
159 | 6af0bf9c | bellard | |
160 | ead9360e | ths | void do_cfc1 (int reg); |
161 | ead9360e | ths | void do_ctc1 (int reg); |
162 | 57fa1fb3 | ths | |
163 | 57fa1fb3 | ths | #define FOP_PROTO(op) \
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164 | 57fa1fb3 | ths | void do_float_ ## op ## _s(void); \ |
165 | 57fa1fb3 | ths | void do_float_ ## op ## _d(void); |
166 | 57fa1fb3 | ths | FOP_PROTO(roundl) |
167 | 57fa1fb3 | ths | FOP_PROTO(roundw) |
168 | 57fa1fb3 | ths | FOP_PROTO(truncl) |
169 | 57fa1fb3 | ths | FOP_PROTO(truncw) |
170 | 57fa1fb3 | ths | FOP_PROTO(ceill) |
171 | 57fa1fb3 | ths | FOP_PROTO(ceilw) |
172 | 57fa1fb3 | ths | FOP_PROTO(floorl) |
173 | 57fa1fb3 | ths | FOP_PROTO(floorw) |
174 | 57fa1fb3 | ths | FOP_PROTO(rsqrt) |
175 | 57fa1fb3 | ths | FOP_PROTO(recip) |
176 | 57fa1fb3 | ths | #undef FOP_PROTO
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177 | 57fa1fb3 | ths | |
178 | 57fa1fb3 | ths | #define FOP_PROTO(op) \
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179 | 57fa1fb3 | ths | void do_float_ ## op ## _s(void); \ |
180 | 57fa1fb3 | ths | void do_float_ ## op ## _d(void); \ |
181 | 57fa1fb3 | ths | void do_float_ ## op ## _ps(void); |
182 | 57fa1fb3 | ths | FOP_PROTO(add) |
183 | 57fa1fb3 | ths | FOP_PROTO(sub) |
184 | 57fa1fb3 | ths | FOP_PROTO(mul) |
185 | 57fa1fb3 | ths | FOP_PROTO(div) |
186 | 57fa1fb3 | ths | FOP_PROTO(recip1) |
187 | 57fa1fb3 | ths | FOP_PROTO(recip2) |
188 | 57fa1fb3 | ths | FOP_PROTO(rsqrt1) |
189 | 57fa1fb3 | ths | FOP_PROTO(rsqrt2) |
190 | 57fa1fb3 | ths | #undef FOP_PROTO
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191 | 57fa1fb3 | ths | |
192 | fd4a04eb | ths | void do_float_cvtd_s(void); |
193 | fd4a04eb | ths | void do_float_cvtd_w(void); |
194 | fd4a04eb | ths | void do_float_cvtd_l(void); |
195 | fd4a04eb | ths | void do_float_cvtl_d(void); |
196 | fd4a04eb | ths | void do_float_cvtl_s(void); |
197 | fd4a04eb | ths | void do_float_cvtps_pw(void); |
198 | fd4a04eb | ths | void do_float_cvtpw_ps(void); |
199 | fd4a04eb | ths | void do_float_cvts_d(void); |
200 | fd4a04eb | ths | void do_float_cvts_w(void); |
201 | fd4a04eb | ths | void do_float_cvts_l(void); |
202 | fd4a04eb | ths | void do_float_cvts_pl(void); |
203 | fd4a04eb | ths | void do_float_cvts_pu(void); |
204 | fd4a04eb | ths | void do_float_cvtw_s(void); |
205 | fd4a04eb | ths | void do_float_cvtw_d(void); |
206 | 57fa1fb3 | ths | |
207 | fd4a04eb | ths | void do_float_addr_ps(void); |
208 | 57fa1fb3 | ths | void do_float_mulr_ps(void); |
209 | fd4a04eb | ths | |
210 | 57fa1fb3 | ths | #define FOP_PROTO(op) \
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211 | fd4a04eb | ths | void do_cmp_d_ ## op(long cc); \ |
212 | fd4a04eb | ths | void do_cmpabs_d_ ## op(long cc); \ |
213 | fd4a04eb | ths | void do_cmp_s_ ## op(long cc); \ |
214 | fd4a04eb | ths | void do_cmpabs_s_ ## op(long cc); \ |
215 | fd4a04eb | ths | void do_cmp_ps_ ## op(long cc); \ |
216 | fd4a04eb | ths | void do_cmpabs_ps_ ## op(long cc); |
217 | fd4a04eb | ths | |
218 | 57fa1fb3 | ths | FOP_PROTO(f) |
219 | 57fa1fb3 | ths | FOP_PROTO(un) |
220 | 57fa1fb3 | ths | FOP_PROTO(eq) |
221 | 57fa1fb3 | ths | FOP_PROTO(ueq) |
222 | 57fa1fb3 | ths | FOP_PROTO(olt) |
223 | 57fa1fb3 | ths | FOP_PROTO(ult) |
224 | 57fa1fb3 | ths | FOP_PROTO(ole) |
225 | 57fa1fb3 | ths | FOP_PROTO(ule) |
226 | 57fa1fb3 | ths | FOP_PROTO(sf) |
227 | 57fa1fb3 | ths | FOP_PROTO(ngle) |
228 | 57fa1fb3 | ths | FOP_PROTO(seq) |
229 | 57fa1fb3 | ths | FOP_PROTO(ngl) |
230 | 57fa1fb3 | ths | FOP_PROTO(lt) |
231 | 57fa1fb3 | ths | FOP_PROTO(nge) |
232 | 57fa1fb3 | ths | FOP_PROTO(le) |
233 | 57fa1fb3 | ths | FOP_PROTO(ngt) |
234 | 57fa1fb3 | ths | #undef FOP_PROTO
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235 | fd4a04eb | ths | |
236 | bfed01fc | ths | static inline void env_to_regs(void) |
237 | bfed01fc | ths | { |
238 | bfed01fc | ths | } |
239 | bfed01fc | ths | |
240 | bfed01fc | ths | static inline void regs_to_env(void) |
241 | bfed01fc | ths | { |
242 | bfed01fc | ths | } |
243 | bfed01fc | ths | |
244 | bfed01fc | ths | static inline int cpu_halted(CPUState *env) { |
245 | bfed01fc | ths | if (!env->halted)
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246 | bfed01fc | ths | return 0; |
247 | bfed01fc | ths | if (env->interrupt_request &
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248 | bfed01fc | ths | (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) { |
249 | bfed01fc | ths | env->halted = 0;
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250 | bfed01fc | ths | return 0; |
251 | bfed01fc | ths | } |
252 | bfed01fc | ths | return EXCP_HALTED;
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253 | bfed01fc | ths | } |
254 | bfed01fc | ths | |
255 | 6af0bf9c | bellard | #endif /* !defined(__QEMU_MIPS_EXEC_H__) */ |