root / target-mips / op.c @ 5fafdf24
History | View | Annotate | Download (59.3 kB)
1 | 6af0bf9c | bellard | /*
|
---|---|---|---|
2 | 6af0bf9c | bellard | * MIPS emulation micro-operations for qemu.
|
3 | 5fafdf24 | ths | *
|
4 | 6af0bf9c | bellard | * Copyright (c) 2004-2005 Jocelyn Mayer
|
5 | 6ea83fed | bellard | * Copyright (c) 2006 Marius Groeger (FPU operations)
|
6 | 93b12ccc | ths | * Copyright (c) 2007 Thiemo Seufer (64-bit FPU support)
|
7 | 6af0bf9c | bellard | *
|
8 | 6af0bf9c | bellard | * This library is free software; you can redistribute it and/or
|
9 | 6af0bf9c | bellard | * modify it under the terms of the GNU Lesser General Public
|
10 | 6af0bf9c | bellard | * License as published by the Free Software Foundation; either
|
11 | 6af0bf9c | bellard | * version 2 of the License, or (at your option) any later version.
|
12 | 6af0bf9c | bellard | *
|
13 | 6af0bf9c | bellard | * This library is distributed in the hope that it will be useful,
|
14 | 6af0bf9c | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
15 | 6af0bf9c | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
16 | 6af0bf9c | bellard | * Lesser General Public License for more details.
|
17 | 6af0bf9c | bellard | *
|
18 | 6af0bf9c | bellard | * You should have received a copy of the GNU Lesser General Public
|
19 | 6af0bf9c | bellard | * License along with this library; if not, write to the Free Software
|
20 | 6af0bf9c | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
21 | 6af0bf9c | bellard | */
|
22 | 6af0bf9c | bellard | |
23 | 6af0bf9c | bellard | #include "config.h" |
24 | 6af0bf9c | bellard | #include "exec.h" |
25 | 6af0bf9c | bellard | |
26 | 1b351e52 | bellard | #ifndef CALL_FROM_TB0
|
27 | 5a5012ec | ths | #define CALL_FROM_TB0(func) func()
|
28 | 1b351e52 | bellard | #endif
|
29 | 1b351e52 | bellard | #ifndef CALL_FROM_TB1
|
30 | 5a5012ec | ths | #define CALL_FROM_TB1(func, arg0) func(arg0)
|
31 | 1b351e52 | bellard | #endif
|
32 | 1b351e52 | bellard | #ifndef CALL_FROM_TB1_CONST16
|
33 | 5a5012ec | ths | #define CALL_FROM_TB1_CONST16(func, arg0) CALL_FROM_TB1(func, arg0)
|
34 | 1b351e52 | bellard | #endif
|
35 | 1b351e52 | bellard | #ifndef CALL_FROM_TB2
|
36 | 5a5012ec | ths | #define CALL_FROM_TB2(func, arg0, arg1) func(arg0, arg1)
|
37 | 1b351e52 | bellard | #endif
|
38 | 1b351e52 | bellard | #ifndef CALL_FROM_TB2_CONST16
|
39 | 1b351e52 | bellard | #define CALL_FROM_TB2_CONST16(func, arg0, arg1) \
|
40 | 5a5012ec | ths | CALL_FROM_TB2(func, arg0, arg1) |
41 | 1b351e52 | bellard | #endif
|
42 | 1b351e52 | bellard | #ifndef CALL_FROM_TB3
|
43 | 5a5012ec | ths | #define CALL_FROM_TB3(func, arg0, arg1, arg2) func(arg0, arg1, arg2)
|
44 | 1b351e52 | bellard | #endif
|
45 | 1b351e52 | bellard | #ifndef CALL_FROM_TB4
|
46 | 1b351e52 | bellard | #define CALL_FROM_TB4(func, arg0, arg1, arg2, arg3) \
|
47 | 5a5012ec | ths | func(arg0, arg1, arg2, arg3) |
48 | 1b351e52 | bellard | #endif
|
49 | 1b351e52 | bellard | |
50 | 6af0bf9c | bellard | #define REG 1 |
51 | 6af0bf9c | bellard | #include "op_template.c" |
52 | 6af0bf9c | bellard | #undef REG
|
53 | 6af0bf9c | bellard | #define REG 2 |
54 | 6af0bf9c | bellard | #include "op_template.c" |
55 | 6af0bf9c | bellard | #undef REG
|
56 | 6af0bf9c | bellard | #define REG 3 |
57 | 6af0bf9c | bellard | #include "op_template.c" |
58 | 6af0bf9c | bellard | #undef REG
|
59 | 6af0bf9c | bellard | #define REG 4 |
60 | 6af0bf9c | bellard | #include "op_template.c" |
61 | 6af0bf9c | bellard | #undef REG
|
62 | 6af0bf9c | bellard | #define REG 5 |
63 | 6af0bf9c | bellard | #include "op_template.c" |
64 | 6af0bf9c | bellard | #undef REG
|
65 | 6af0bf9c | bellard | #define REG 6 |
66 | 6af0bf9c | bellard | #include "op_template.c" |
67 | 6af0bf9c | bellard | #undef REG
|
68 | 6af0bf9c | bellard | #define REG 7 |
69 | 6af0bf9c | bellard | #include "op_template.c" |
70 | 6af0bf9c | bellard | #undef REG
|
71 | 6af0bf9c | bellard | #define REG 8 |
72 | 6af0bf9c | bellard | #include "op_template.c" |
73 | 6af0bf9c | bellard | #undef REG
|
74 | 6af0bf9c | bellard | #define REG 9 |
75 | 6af0bf9c | bellard | #include "op_template.c" |
76 | 6af0bf9c | bellard | #undef REG
|
77 | 6af0bf9c | bellard | #define REG 10 |
78 | 6af0bf9c | bellard | #include "op_template.c" |
79 | 6af0bf9c | bellard | #undef REG
|
80 | 6af0bf9c | bellard | #define REG 11 |
81 | 6af0bf9c | bellard | #include "op_template.c" |
82 | 6af0bf9c | bellard | #undef REG
|
83 | 6af0bf9c | bellard | #define REG 12 |
84 | 6af0bf9c | bellard | #include "op_template.c" |
85 | 6af0bf9c | bellard | #undef REG
|
86 | 6af0bf9c | bellard | #define REG 13 |
87 | 6af0bf9c | bellard | #include "op_template.c" |
88 | 6af0bf9c | bellard | #undef REG
|
89 | 6af0bf9c | bellard | #define REG 14 |
90 | 6af0bf9c | bellard | #include "op_template.c" |
91 | 6af0bf9c | bellard | #undef REG
|
92 | 6af0bf9c | bellard | #define REG 15 |
93 | 6af0bf9c | bellard | #include "op_template.c" |
94 | 6af0bf9c | bellard | #undef REG
|
95 | 6af0bf9c | bellard | #define REG 16 |
96 | 6af0bf9c | bellard | #include "op_template.c" |
97 | 6af0bf9c | bellard | #undef REG
|
98 | 6af0bf9c | bellard | #define REG 17 |
99 | 6af0bf9c | bellard | #include "op_template.c" |
100 | 6af0bf9c | bellard | #undef REG
|
101 | 6af0bf9c | bellard | #define REG 18 |
102 | 6af0bf9c | bellard | #include "op_template.c" |
103 | 6af0bf9c | bellard | #undef REG
|
104 | 6af0bf9c | bellard | #define REG 19 |
105 | 6af0bf9c | bellard | #include "op_template.c" |
106 | 6af0bf9c | bellard | #undef REG
|
107 | 6af0bf9c | bellard | #define REG 20 |
108 | 6af0bf9c | bellard | #include "op_template.c" |
109 | 6af0bf9c | bellard | #undef REG
|
110 | 6af0bf9c | bellard | #define REG 21 |
111 | 6af0bf9c | bellard | #include "op_template.c" |
112 | 6af0bf9c | bellard | #undef REG
|
113 | 6af0bf9c | bellard | #define REG 22 |
114 | 6af0bf9c | bellard | #include "op_template.c" |
115 | 6af0bf9c | bellard | #undef REG
|
116 | 6af0bf9c | bellard | #define REG 23 |
117 | 6af0bf9c | bellard | #include "op_template.c" |
118 | 6af0bf9c | bellard | #undef REG
|
119 | 6af0bf9c | bellard | #define REG 24 |
120 | 6af0bf9c | bellard | #include "op_template.c" |
121 | 6af0bf9c | bellard | #undef REG
|
122 | 6af0bf9c | bellard | #define REG 25 |
123 | 6af0bf9c | bellard | #include "op_template.c" |
124 | 6af0bf9c | bellard | #undef REG
|
125 | 6af0bf9c | bellard | #define REG 26 |
126 | 6af0bf9c | bellard | #include "op_template.c" |
127 | 6af0bf9c | bellard | #undef REG
|
128 | 6af0bf9c | bellard | #define REG 27 |
129 | 6af0bf9c | bellard | #include "op_template.c" |
130 | 6af0bf9c | bellard | #undef REG
|
131 | 6af0bf9c | bellard | #define REG 28 |
132 | 6af0bf9c | bellard | #include "op_template.c" |
133 | 6af0bf9c | bellard | #undef REG
|
134 | 6af0bf9c | bellard | #define REG 29 |
135 | 6af0bf9c | bellard | #include "op_template.c" |
136 | 6af0bf9c | bellard | #undef REG
|
137 | 6af0bf9c | bellard | #define REG 30 |
138 | 6af0bf9c | bellard | #include "op_template.c" |
139 | 6af0bf9c | bellard | #undef REG
|
140 | 6af0bf9c | bellard | #define REG 31 |
141 | 6af0bf9c | bellard | #include "op_template.c" |
142 | 6af0bf9c | bellard | #undef REG
|
143 | 6af0bf9c | bellard | |
144 | c570fd16 | ths | #define TN
|
145 | 6af0bf9c | bellard | #include "op_template.c" |
146 | 6af0bf9c | bellard | #undef TN
|
147 | 6af0bf9c | bellard | |
148 | 5a5012ec | ths | #define FREG 0 |
149 | 6ea83fed | bellard | #include "fop_template.c" |
150 | 5a5012ec | ths | #undef FREG
|
151 | 5a5012ec | ths | #define FREG 1 |
152 | 6ea83fed | bellard | #include "fop_template.c" |
153 | 5a5012ec | ths | #undef FREG
|
154 | 5a5012ec | ths | #define FREG 2 |
155 | 6ea83fed | bellard | #include "fop_template.c" |
156 | 5a5012ec | ths | #undef FREG
|
157 | 5a5012ec | ths | #define FREG 3 |
158 | 6ea83fed | bellard | #include "fop_template.c" |
159 | 5a5012ec | ths | #undef FREG
|
160 | 5a5012ec | ths | #define FREG 4 |
161 | 6ea83fed | bellard | #include "fop_template.c" |
162 | 5a5012ec | ths | #undef FREG
|
163 | 5a5012ec | ths | #define FREG 5 |
164 | 6ea83fed | bellard | #include "fop_template.c" |
165 | 5a5012ec | ths | #undef FREG
|
166 | 5a5012ec | ths | #define FREG 6 |
167 | 6ea83fed | bellard | #include "fop_template.c" |
168 | 5a5012ec | ths | #undef FREG
|
169 | 5a5012ec | ths | #define FREG 7 |
170 | 6ea83fed | bellard | #include "fop_template.c" |
171 | 5a5012ec | ths | #undef FREG
|
172 | 5a5012ec | ths | #define FREG 8 |
173 | 6ea83fed | bellard | #include "fop_template.c" |
174 | 5a5012ec | ths | #undef FREG
|
175 | 5a5012ec | ths | #define FREG 9 |
176 | 6ea83fed | bellard | #include "fop_template.c" |
177 | 5a5012ec | ths | #undef FREG
|
178 | 5a5012ec | ths | #define FREG 10 |
179 | 6ea83fed | bellard | #include "fop_template.c" |
180 | 5a5012ec | ths | #undef FREG
|
181 | 5a5012ec | ths | #define FREG 11 |
182 | 6ea83fed | bellard | #include "fop_template.c" |
183 | 5a5012ec | ths | #undef FREG
|
184 | 5a5012ec | ths | #define FREG 12 |
185 | 6ea83fed | bellard | #include "fop_template.c" |
186 | 5a5012ec | ths | #undef FREG
|
187 | 5a5012ec | ths | #define FREG 13 |
188 | 6ea83fed | bellard | #include "fop_template.c" |
189 | 5a5012ec | ths | #undef FREG
|
190 | 5a5012ec | ths | #define FREG 14 |
191 | 6ea83fed | bellard | #include "fop_template.c" |
192 | 5a5012ec | ths | #undef FREG
|
193 | 5a5012ec | ths | #define FREG 15 |
194 | 6ea83fed | bellard | #include "fop_template.c" |
195 | 5a5012ec | ths | #undef FREG
|
196 | 5a5012ec | ths | #define FREG 16 |
197 | 6ea83fed | bellard | #include "fop_template.c" |
198 | 5a5012ec | ths | #undef FREG
|
199 | 5a5012ec | ths | #define FREG 17 |
200 | 6ea83fed | bellard | #include "fop_template.c" |
201 | 5a5012ec | ths | #undef FREG
|
202 | 5a5012ec | ths | #define FREG 18 |
203 | 6ea83fed | bellard | #include "fop_template.c" |
204 | 5a5012ec | ths | #undef FREG
|
205 | 5a5012ec | ths | #define FREG 19 |
206 | 6ea83fed | bellard | #include "fop_template.c" |
207 | 5a5012ec | ths | #undef FREG
|
208 | 5a5012ec | ths | #define FREG 20 |
209 | 6ea83fed | bellard | #include "fop_template.c" |
210 | 5a5012ec | ths | #undef FREG
|
211 | 5a5012ec | ths | #define FREG 21 |
212 | 6ea83fed | bellard | #include "fop_template.c" |
213 | 5a5012ec | ths | #undef FREG
|
214 | 5a5012ec | ths | #define FREG 22 |
215 | 6ea83fed | bellard | #include "fop_template.c" |
216 | 5a5012ec | ths | #undef FREG
|
217 | 5a5012ec | ths | #define FREG 23 |
218 | 6ea83fed | bellard | #include "fop_template.c" |
219 | 5a5012ec | ths | #undef FREG
|
220 | 5a5012ec | ths | #define FREG 24 |
221 | 6ea83fed | bellard | #include "fop_template.c" |
222 | 5a5012ec | ths | #undef FREG
|
223 | 5a5012ec | ths | #define FREG 25 |
224 | 6ea83fed | bellard | #include "fop_template.c" |
225 | 5a5012ec | ths | #undef FREG
|
226 | 5a5012ec | ths | #define FREG 26 |
227 | 6ea83fed | bellard | #include "fop_template.c" |
228 | 5a5012ec | ths | #undef FREG
|
229 | 5a5012ec | ths | #define FREG 27 |
230 | 6ea83fed | bellard | #include "fop_template.c" |
231 | 5a5012ec | ths | #undef FREG
|
232 | 5a5012ec | ths | #define FREG 28 |
233 | 6ea83fed | bellard | #include "fop_template.c" |
234 | 5a5012ec | ths | #undef FREG
|
235 | 5a5012ec | ths | #define FREG 29 |
236 | 6ea83fed | bellard | #include "fop_template.c" |
237 | 5a5012ec | ths | #undef FREG
|
238 | 5a5012ec | ths | #define FREG 30 |
239 | 6ea83fed | bellard | #include "fop_template.c" |
240 | 5a5012ec | ths | #undef FREG
|
241 | 5a5012ec | ths | #define FREG 31 |
242 | 6ea83fed | bellard | #include "fop_template.c" |
243 | 5a5012ec | ths | #undef FREG
|
244 | 6ea83fed | bellard | |
245 | 6ea83fed | bellard | #define FTN
|
246 | 6ea83fed | bellard | #include "fop_template.c" |
247 | 6ea83fed | bellard | #undef FTN
|
248 | 6ea83fed | bellard | |
249 | 6af0bf9c | bellard | void op_dup_T0 (void) |
250 | 6af0bf9c | bellard | { |
251 | 6af0bf9c | bellard | T2 = T0; |
252 | 6af0bf9c | bellard | RETURN(); |
253 | 6af0bf9c | bellard | } |
254 | 6af0bf9c | bellard | |
255 | 6af0bf9c | bellard | void op_load_HI (void) |
256 | 6af0bf9c | bellard | { |
257 | ead9360e | ths | T0 = env->HI[PARAM1][env->current_tc]; |
258 | 6af0bf9c | bellard | RETURN(); |
259 | 6af0bf9c | bellard | } |
260 | 6af0bf9c | bellard | |
261 | 6af0bf9c | bellard | void op_store_HI (void) |
262 | 6af0bf9c | bellard | { |
263 | ead9360e | ths | env->HI[PARAM1][env->current_tc] = T0; |
264 | 6af0bf9c | bellard | RETURN(); |
265 | 6af0bf9c | bellard | } |
266 | 6af0bf9c | bellard | |
267 | 6af0bf9c | bellard | void op_load_LO (void) |
268 | 6af0bf9c | bellard | { |
269 | ead9360e | ths | T0 = env->LO[PARAM1][env->current_tc]; |
270 | 6af0bf9c | bellard | RETURN(); |
271 | 6af0bf9c | bellard | } |
272 | 6af0bf9c | bellard | |
273 | 6af0bf9c | bellard | void op_store_LO (void) |
274 | 6af0bf9c | bellard | { |
275 | ead9360e | ths | env->LO[PARAM1][env->current_tc] = T0; |
276 | 6af0bf9c | bellard | RETURN(); |
277 | 6af0bf9c | bellard | } |
278 | 6af0bf9c | bellard | |
279 | 6af0bf9c | bellard | /* Load and store */
|
280 | 6af0bf9c | bellard | #define MEMSUFFIX _raw
|
281 | 6af0bf9c | bellard | #include "op_mem.c" |
282 | 6af0bf9c | bellard | #undef MEMSUFFIX
|
283 | 6af0bf9c | bellard | #if !defined(CONFIG_USER_ONLY)
|
284 | 6af0bf9c | bellard | #define MEMSUFFIX _user
|
285 | 6af0bf9c | bellard | #include "op_mem.c" |
286 | 6af0bf9c | bellard | #undef MEMSUFFIX
|
287 | 6af0bf9c | bellard | |
288 | 6af0bf9c | bellard | #define MEMSUFFIX _kernel
|
289 | 6af0bf9c | bellard | #include "op_mem.c" |
290 | 6af0bf9c | bellard | #undef MEMSUFFIX
|
291 | 6af0bf9c | bellard | #endif
|
292 | 6af0bf9c | bellard | |
293 | a6763a58 | ths | /* Addresses computation */
|
294 | a6763a58 | ths | void op_addr_add (void) |
295 | a6763a58 | ths | { |
296 | a6763a58 | ths | /* For compatibility with 32-bit code, data reference in user mode
|
297 | a6763a58 | ths | with Status_UX = 0 should be casted to 32-bit and sign extended.
|
298 | a6763a58 | ths | See the MIPS64 PRA manual, section 4.10. */
|
299 | a6763a58 | ths | #ifdef TARGET_MIPS64
|
300 | 996ba2cc | ths | if ((env->hflags & MIPS_HFLAG_UM) &&
|
301 | a6763a58 | ths | !(env->CP0_Status & (1 << CP0St_UX)))
|
302 | a6763a58 | ths | T0 = (int64_t)(int32_t)(T0 + T1); |
303 | a6763a58 | ths | else
|
304 | a6763a58 | ths | #endif
|
305 | a6763a58 | ths | T0 += T1; |
306 | a6763a58 | ths | RETURN(); |
307 | a6763a58 | ths | } |
308 | a6763a58 | ths | |
309 | 6af0bf9c | bellard | /* Arithmetic */
|
310 | 6af0bf9c | bellard | void op_add (void) |
311 | 6af0bf9c | bellard | { |
312 | 5dc4b744 | ths | T0 = (int32_t)((int32_t)T0 + (int32_t)T1); |
313 | 6af0bf9c | bellard | RETURN(); |
314 | 6af0bf9c | bellard | } |
315 | 6af0bf9c | bellard | |
316 | 6af0bf9c | bellard | void op_addo (void) |
317 | 6af0bf9c | bellard | { |
318 | 6af0bf9c | bellard | target_ulong tmp; |
319 | 6af0bf9c | bellard | |
320 | c570fd16 | ths | tmp = (int32_t)T0; |
321 | c570fd16 | ths | T0 = (int32_t)T0 + (int32_t)T1; |
322 | 76e050c2 | bellard | if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 31) { |
323 | c570fd16 | ths | /* operands of same sign, result different sign */
|
324 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW); |
325 | 6af0bf9c | bellard | } |
326 | 5dc4b744 | ths | T0 = (int32_t)T0; |
327 | 6af0bf9c | bellard | RETURN(); |
328 | 6af0bf9c | bellard | } |
329 | 6af0bf9c | bellard | |
330 | 6af0bf9c | bellard | void op_sub (void) |
331 | 6af0bf9c | bellard | { |
332 | 5dc4b744 | ths | T0 = (int32_t)((int32_t)T0 - (int32_t)T1); |
333 | 6af0bf9c | bellard | RETURN(); |
334 | 6af0bf9c | bellard | } |
335 | 6af0bf9c | bellard | |
336 | 6af0bf9c | bellard | void op_subo (void) |
337 | 6af0bf9c | bellard | { |
338 | 6af0bf9c | bellard | target_ulong tmp; |
339 | 6af0bf9c | bellard | |
340 | c570fd16 | ths | tmp = (int32_t)T0; |
341 | 6af0bf9c | bellard | T0 = (int32_t)T0 - (int32_t)T1; |
342 | 76e050c2 | bellard | if (((tmp ^ T1) & (tmp ^ T0)) >> 31) { |
343 | c570fd16 | ths | /* operands of different sign, first operand and result different sign */
|
344 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW); |
345 | 6af0bf9c | bellard | } |
346 | 5dc4b744 | ths | T0 = (int32_t)T0; |
347 | 6af0bf9c | bellard | RETURN(); |
348 | 6af0bf9c | bellard | } |
349 | 6af0bf9c | bellard | |
350 | 6af0bf9c | bellard | void op_mul (void) |
351 | 6af0bf9c | bellard | { |
352 | 5dc4b744 | ths | T0 = (int32_t)((int32_t)T0 * (int32_t)T1); |
353 | 6af0bf9c | bellard | RETURN(); |
354 | 6af0bf9c | bellard | } |
355 | 6af0bf9c | bellard | |
356 | 80c27194 | ths | #if HOST_LONG_BITS < 64 |
357 | 80c27194 | ths | void op_div (void) |
358 | 80c27194 | ths | { |
359 | 80c27194 | ths | CALL_FROM_TB0(do_div); |
360 | 80c27194 | ths | RETURN(); |
361 | 80c27194 | ths | } |
362 | 80c27194 | ths | #else
|
363 | 6af0bf9c | bellard | void op_div (void) |
364 | 6af0bf9c | bellard | { |
365 | 6af0bf9c | bellard | if (T1 != 0) { |
366 | ead9360e | ths | env->LO[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1);
|
367 | ead9360e | ths | env->HI[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1);
|
368 | 6af0bf9c | bellard | } |
369 | 6af0bf9c | bellard | RETURN(); |
370 | 6af0bf9c | bellard | } |
371 | 80c27194 | ths | #endif
|
372 | 6af0bf9c | bellard | |
373 | 6af0bf9c | bellard | void op_divu (void) |
374 | 6af0bf9c | bellard | { |
375 | 6af0bf9c | bellard | if (T1 != 0) { |
376 | ead9360e | ths | env->LO[0][env->current_tc] = (int32_t)((uint32_t)T0 / (uint32_t)T1);
|
377 | ead9360e | ths | env->HI[0][env->current_tc] = (int32_t)((uint32_t)T0 % (uint32_t)T1);
|
378 | c570fd16 | ths | } |
379 | c570fd16 | ths | RETURN(); |
380 | c570fd16 | ths | } |
381 | c570fd16 | ths | |
382 | 60aa19ab | ths | #ifdef TARGET_MIPS64
|
383 | c570fd16 | ths | /* Arithmetic */
|
384 | c570fd16 | ths | void op_dadd (void) |
385 | c570fd16 | ths | { |
386 | c570fd16 | ths | T0 += T1; |
387 | c570fd16 | ths | RETURN(); |
388 | c570fd16 | ths | } |
389 | c570fd16 | ths | |
390 | c570fd16 | ths | void op_daddo (void) |
391 | c570fd16 | ths | { |
392 | c570fd16 | ths | target_long tmp; |
393 | c570fd16 | ths | |
394 | c570fd16 | ths | tmp = T0; |
395 | c570fd16 | ths | T0 += T1; |
396 | c570fd16 | ths | if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 63) { |
397 | c570fd16 | ths | /* operands of same sign, result different sign */
|
398 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW); |
399 | c570fd16 | ths | } |
400 | c570fd16 | ths | RETURN(); |
401 | c570fd16 | ths | } |
402 | c570fd16 | ths | |
403 | c570fd16 | ths | void op_dsub (void) |
404 | c570fd16 | ths | { |
405 | c570fd16 | ths | T0 -= T1; |
406 | c570fd16 | ths | RETURN(); |
407 | c570fd16 | ths | } |
408 | c570fd16 | ths | |
409 | c570fd16 | ths | void op_dsubo (void) |
410 | c570fd16 | ths | { |
411 | c570fd16 | ths | target_long tmp; |
412 | c570fd16 | ths | |
413 | c570fd16 | ths | tmp = T0; |
414 | c570fd16 | ths | T0 = (int64_t)T0 - (int64_t)T1; |
415 | c570fd16 | ths | if (((tmp ^ T1) & (tmp ^ T0)) >> 63) { |
416 | c570fd16 | ths | /* operands of different sign, first operand and result different sign */
|
417 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW); |
418 | c570fd16 | ths | } |
419 | c570fd16 | ths | RETURN(); |
420 | c570fd16 | ths | } |
421 | c570fd16 | ths | |
422 | c570fd16 | ths | void op_dmul (void) |
423 | c570fd16 | ths | { |
424 | c570fd16 | ths | T0 = (int64_t)T0 * (int64_t)T1; |
425 | c570fd16 | ths | RETURN(); |
426 | c570fd16 | ths | } |
427 | c570fd16 | ths | |
428 | c570fd16 | ths | /* Those might call libgcc functions. */
|
429 | c570fd16 | ths | void op_ddiv (void) |
430 | c570fd16 | ths | { |
431 | c570fd16 | ths | do_ddiv(); |
432 | c570fd16 | ths | RETURN(); |
433 | c570fd16 | ths | } |
434 | c570fd16 | ths | |
435 | 80c27194 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
|
436 | c570fd16 | ths | void op_ddivu (void) |
437 | c570fd16 | ths | { |
438 | c570fd16 | ths | do_ddivu(); |
439 | c570fd16 | ths | RETURN(); |
440 | c570fd16 | ths | } |
441 | c570fd16 | ths | #else
|
442 | c570fd16 | ths | void op_ddivu (void) |
443 | c570fd16 | ths | { |
444 | c570fd16 | ths | if (T1 != 0) { |
445 | ead9360e | ths | env->LO[0][env->current_tc] = T0 / T1;
|
446 | ead9360e | ths | env->HI[0][env->current_tc] = T0 % T1;
|
447 | 6af0bf9c | bellard | } |
448 | 6af0bf9c | bellard | RETURN(); |
449 | 6af0bf9c | bellard | } |
450 | c570fd16 | ths | #endif
|
451 | 60aa19ab | ths | #endif /* TARGET_MIPS64 */ |
452 | 6af0bf9c | bellard | |
453 | 6af0bf9c | bellard | /* Logical */
|
454 | 6af0bf9c | bellard | void op_and (void) |
455 | 6af0bf9c | bellard | { |
456 | 6af0bf9c | bellard | T0 &= T1; |
457 | 6af0bf9c | bellard | RETURN(); |
458 | 6af0bf9c | bellard | } |
459 | 6af0bf9c | bellard | |
460 | 6af0bf9c | bellard | void op_nor (void) |
461 | 6af0bf9c | bellard | { |
462 | 6af0bf9c | bellard | T0 = ~(T0 | T1); |
463 | 6af0bf9c | bellard | RETURN(); |
464 | 6af0bf9c | bellard | } |
465 | 6af0bf9c | bellard | |
466 | 6af0bf9c | bellard | void op_or (void) |
467 | 6af0bf9c | bellard | { |
468 | 6af0bf9c | bellard | T0 |= T1; |
469 | 6af0bf9c | bellard | RETURN(); |
470 | 6af0bf9c | bellard | } |
471 | 6af0bf9c | bellard | |
472 | 6af0bf9c | bellard | void op_xor (void) |
473 | 6af0bf9c | bellard | { |
474 | 6af0bf9c | bellard | T0 ^= T1; |
475 | 6af0bf9c | bellard | RETURN(); |
476 | 6af0bf9c | bellard | } |
477 | 6af0bf9c | bellard | |
478 | 6af0bf9c | bellard | void op_sll (void) |
479 | 6af0bf9c | bellard | { |
480 | 5a63bcb2 | ths | T0 = (int32_t)((uint32_t)T0 << T1); |
481 | 6af0bf9c | bellard | RETURN(); |
482 | 6af0bf9c | bellard | } |
483 | 6af0bf9c | bellard | |
484 | 6af0bf9c | bellard | void op_sra (void) |
485 | 6af0bf9c | bellard | { |
486 | 5a63bcb2 | ths | T0 = (int32_t)((int32_t)T0 >> T1); |
487 | 6af0bf9c | bellard | RETURN(); |
488 | 6af0bf9c | bellard | } |
489 | 6af0bf9c | bellard | |
490 | 6af0bf9c | bellard | void op_srl (void) |
491 | 6af0bf9c | bellard | { |
492 | 5a63bcb2 | ths | T0 = (int32_t)((uint32_t)T0 >> T1); |
493 | 6af0bf9c | bellard | RETURN(); |
494 | 6af0bf9c | bellard | } |
495 | 6af0bf9c | bellard | |
496 | 7a387fff | ths | void op_rotr (void) |
497 | 7a387fff | ths | { |
498 | 7a387fff | ths | target_ulong tmp; |
499 | 7a387fff | ths | |
500 | 7a387fff | ths | if (T1) {
|
501 | 5a63bcb2 | ths | tmp = (int32_t)((uint32_t)T0 << (0x20 - T1));
|
502 | 5a63bcb2 | ths | T0 = (int32_t)((uint32_t)T0 >> T1) | tmp; |
503 | 5a63bcb2 | ths | } |
504 | 7a387fff | ths | RETURN(); |
505 | 7a387fff | ths | } |
506 | 7a387fff | ths | |
507 | 6af0bf9c | bellard | void op_sllv (void) |
508 | 6af0bf9c | bellard | { |
509 | 5dc4b744 | ths | T0 = (int32_t)((uint32_t)T1 << ((uint32_t)T0 & 0x1F));
|
510 | 6af0bf9c | bellard | RETURN(); |
511 | 6af0bf9c | bellard | } |
512 | 6af0bf9c | bellard | |
513 | 6af0bf9c | bellard | void op_srav (void) |
514 | 6af0bf9c | bellard | { |
515 | 5dc4b744 | ths | T0 = (int32_t)((int32_t)T1 >> (T0 & 0x1F));
|
516 | 6af0bf9c | bellard | RETURN(); |
517 | 6af0bf9c | bellard | } |
518 | 6af0bf9c | bellard | |
519 | 6af0bf9c | bellard | void op_srlv (void) |
520 | 6af0bf9c | bellard | { |
521 | 5dc4b744 | ths | T0 = (int32_t)((uint32_t)T1 >> (T0 & 0x1F));
|
522 | 6af0bf9c | bellard | RETURN(); |
523 | 6af0bf9c | bellard | } |
524 | 6af0bf9c | bellard | |
525 | 7a387fff | ths | void op_rotrv (void) |
526 | 7a387fff | ths | { |
527 | 7a387fff | ths | target_ulong tmp; |
528 | 7a387fff | ths | |
529 | 7a387fff | ths | T0 &= 0x1F;
|
530 | 7a387fff | ths | if (T0) {
|
531 | 5dc4b744 | ths | tmp = (int32_t)((uint32_t)T1 << (0x20 - T0));
|
532 | 5dc4b744 | ths | T0 = (int32_t)((uint32_t)T1 >> T0) | tmp; |
533 | 7a387fff | ths | } else
|
534 | 7a387fff | ths | T0 = T1; |
535 | 7a387fff | ths | RETURN(); |
536 | 7a387fff | ths | } |
537 | 7a387fff | ths | |
538 | 6af0bf9c | bellard | void op_clo (void) |
539 | 6af0bf9c | bellard | { |
540 | 6af0bf9c | bellard | int n;
|
541 | 6af0bf9c | bellard | |
542 | c570fd16 | ths | if (T0 == ~((target_ulong)0)) { |
543 | 6af0bf9c | bellard | T0 = 32;
|
544 | 6af0bf9c | bellard | } else {
|
545 | 6af0bf9c | bellard | for (n = 0; n < 32; n++) { |
546 | 6af0bf9c | bellard | if (!(T0 & (1 << 31))) |
547 | 6af0bf9c | bellard | break;
|
548 | 6af0bf9c | bellard | T0 = T0 << 1;
|
549 | 6af0bf9c | bellard | } |
550 | 6af0bf9c | bellard | T0 = n; |
551 | 6af0bf9c | bellard | } |
552 | 6af0bf9c | bellard | RETURN(); |
553 | 6af0bf9c | bellard | } |
554 | 6af0bf9c | bellard | |
555 | 6af0bf9c | bellard | void op_clz (void) |
556 | 6af0bf9c | bellard | { |
557 | 6af0bf9c | bellard | int n;
|
558 | 6af0bf9c | bellard | |
559 | 6af0bf9c | bellard | if (T0 == 0) { |
560 | 6af0bf9c | bellard | T0 = 32;
|
561 | 6af0bf9c | bellard | } else {
|
562 | 6af0bf9c | bellard | for (n = 0; n < 32; n++) { |
563 | 6af0bf9c | bellard | if (T0 & (1 << 31)) |
564 | 6af0bf9c | bellard | break;
|
565 | 6af0bf9c | bellard | T0 = T0 << 1;
|
566 | 6af0bf9c | bellard | } |
567 | 6af0bf9c | bellard | T0 = n; |
568 | 6af0bf9c | bellard | } |
569 | 6af0bf9c | bellard | RETURN(); |
570 | 6af0bf9c | bellard | } |
571 | 6af0bf9c | bellard | |
572 | 60aa19ab | ths | #ifdef TARGET_MIPS64
|
573 | c570fd16 | ths | |
574 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
|
575 | c570fd16 | ths | /* Those might call libgcc functions. */
|
576 | c570fd16 | ths | void op_dsll (void) |
577 | 6af0bf9c | bellard | { |
578 | c570fd16 | ths | CALL_FROM_TB0(do_dsll); |
579 | c570fd16 | ths | RETURN(); |
580 | 6af0bf9c | bellard | } |
581 | 6af0bf9c | bellard | |
582 | c570fd16 | ths | void op_dsll32 (void) |
583 | 6af0bf9c | bellard | { |
584 | c570fd16 | ths | CALL_FROM_TB0(do_dsll32); |
585 | c570fd16 | ths | RETURN(); |
586 | 6af0bf9c | bellard | } |
587 | 6af0bf9c | bellard | |
588 | c570fd16 | ths | void op_dsra (void) |
589 | 6af0bf9c | bellard | { |
590 | c570fd16 | ths | CALL_FROM_TB0(do_dsra); |
591 | 6af0bf9c | bellard | RETURN(); |
592 | 6af0bf9c | bellard | } |
593 | 6af0bf9c | bellard | |
594 | c570fd16 | ths | void op_dsra32 (void) |
595 | 6af0bf9c | bellard | { |
596 | c570fd16 | ths | CALL_FROM_TB0(do_dsra32); |
597 | 6af0bf9c | bellard | RETURN(); |
598 | 6af0bf9c | bellard | } |
599 | 6af0bf9c | bellard | |
600 | c570fd16 | ths | void op_dsrl (void) |
601 | 6af0bf9c | bellard | { |
602 | c570fd16 | ths | CALL_FROM_TB0(do_dsrl); |
603 | c570fd16 | ths | RETURN(); |
604 | c570fd16 | ths | } |
605 | 6af0bf9c | bellard | |
606 | c570fd16 | ths | void op_dsrl32 (void) |
607 | c570fd16 | ths | { |
608 | c570fd16 | ths | CALL_FROM_TB0(do_dsrl32); |
609 | 6af0bf9c | bellard | RETURN(); |
610 | 6af0bf9c | bellard | } |
611 | 6af0bf9c | bellard | |
612 | c570fd16 | ths | void op_drotr (void) |
613 | 6af0bf9c | bellard | { |
614 | c570fd16 | ths | CALL_FROM_TB0(do_drotr); |
615 | c570fd16 | ths | RETURN(); |
616 | c570fd16 | ths | } |
617 | 6af0bf9c | bellard | |
618 | c570fd16 | ths | void op_drotr32 (void) |
619 | c570fd16 | ths | { |
620 | c570fd16 | ths | CALL_FROM_TB0(do_drotr32); |
621 | 6af0bf9c | bellard | RETURN(); |
622 | 6af0bf9c | bellard | } |
623 | 6af0bf9c | bellard | |
624 | c570fd16 | ths | void op_dsllv (void) |
625 | 6af0bf9c | bellard | { |
626 | c570fd16 | ths | CALL_FROM_TB0(do_dsllv); |
627 | c570fd16 | ths | RETURN(); |
628 | c570fd16 | ths | } |
629 | 6af0bf9c | bellard | |
630 | c570fd16 | ths | void op_dsrav (void) |
631 | c570fd16 | ths | { |
632 | c570fd16 | ths | CALL_FROM_TB0(do_dsrav); |
633 | 6af0bf9c | bellard | RETURN(); |
634 | 6af0bf9c | bellard | } |
635 | 6af0bf9c | bellard | |
636 | c570fd16 | ths | void op_dsrlv (void) |
637 | 6af0bf9c | bellard | { |
638 | c570fd16 | ths | CALL_FROM_TB0(do_dsrlv); |
639 | c570fd16 | ths | RETURN(); |
640 | c570fd16 | ths | } |
641 | 6af0bf9c | bellard | |
642 | c570fd16 | ths | void op_drotrv (void) |
643 | c570fd16 | ths | { |
644 | c570fd16 | ths | CALL_FROM_TB0(do_drotrv); |
645 | 6af0bf9c | bellard | RETURN(); |
646 | 6af0bf9c | bellard | } |
647 | c570fd16 | ths | |
648 | c570fd16 | ths | #else /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
649 | c570fd16 | ths | |
650 | c570fd16 | ths | void op_dsll (void) |
651 | c570fd16 | ths | { |
652 | c570fd16 | ths | T0 = T0 << T1; |
653 | c570fd16 | ths | RETURN(); |
654 | c570fd16 | ths | } |
655 | c570fd16 | ths | |
656 | c570fd16 | ths | void op_dsll32 (void) |
657 | c570fd16 | ths | { |
658 | c570fd16 | ths | T0 = T0 << (T1 + 32);
|
659 | c570fd16 | ths | RETURN(); |
660 | c570fd16 | ths | } |
661 | c570fd16 | ths | |
662 | c570fd16 | ths | void op_dsra (void) |
663 | c570fd16 | ths | { |
664 | c570fd16 | ths | T0 = (int64_t)T0 >> T1; |
665 | c570fd16 | ths | RETURN(); |
666 | c570fd16 | ths | } |
667 | c570fd16 | ths | |
668 | c570fd16 | ths | void op_dsra32 (void) |
669 | c570fd16 | ths | { |
670 | c570fd16 | ths | T0 = (int64_t)T0 >> (T1 + 32);
|
671 | c570fd16 | ths | RETURN(); |
672 | c570fd16 | ths | } |
673 | c570fd16 | ths | |
674 | c570fd16 | ths | void op_dsrl (void) |
675 | c570fd16 | ths | { |
676 | c570fd16 | ths | T0 = T0 >> T1; |
677 | c570fd16 | ths | RETURN(); |
678 | c570fd16 | ths | } |
679 | c570fd16 | ths | |
680 | c570fd16 | ths | void op_dsrl32 (void) |
681 | c570fd16 | ths | { |
682 | c570fd16 | ths | T0 = T0 >> (T1 + 32);
|
683 | c570fd16 | ths | RETURN(); |
684 | c570fd16 | ths | } |
685 | c570fd16 | ths | |
686 | c570fd16 | ths | void op_drotr (void) |
687 | c570fd16 | ths | { |
688 | c570fd16 | ths | target_ulong tmp; |
689 | c570fd16 | ths | |
690 | c570fd16 | ths | if (T1) {
|
691 | c570fd16 | ths | tmp = T0 << (0x40 - T1);
|
692 | c570fd16 | ths | T0 = (T0 >> T1) | tmp; |
693 | 5a63bcb2 | ths | } |
694 | c570fd16 | ths | RETURN(); |
695 | c570fd16 | ths | } |
696 | c570fd16 | ths | |
697 | c570fd16 | ths | void op_drotr32 (void) |
698 | c570fd16 | ths | { |
699 | c570fd16 | ths | target_ulong tmp; |
700 | c570fd16 | ths | |
701 | c570fd16 | ths | if (T1) {
|
702 | c570fd16 | ths | tmp = T0 << (0x40 - (32 + T1)); |
703 | c570fd16 | ths | T0 = (T0 >> (32 + T1)) | tmp;
|
704 | 5a63bcb2 | ths | } |
705 | c570fd16 | ths | RETURN(); |
706 | c570fd16 | ths | } |
707 | c570fd16 | ths | |
708 | c570fd16 | ths | void op_dsllv (void) |
709 | c570fd16 | ths | { |
710 | c570fd16 | ths | T0 = T1 << (T0 & 0x3F);
|
711 | c570fd16 | ths | RETURN(); |
712 | c570fd16 | ths | } |
713 | c570fd16 | ths | |
714 | c570fd16 | ths | void op_dsrav (void) |
715 | c570fd16 | ths | { |
716 | c570fd16 | ths | T0 = (int64_t)T1 >> (T0 & 0x3F);
|
717 | c570fd16 | ths | RETURN(); |
718 | c570fd16 | ths | } |
719 | c570fd16 | ths | |
720 | c570fd16 | ths | void op_dsrlv (void) |
721 | c570fd16 | ths | { |
722 | c570fd16 | ths | T0 = T1 >> (T0 & 0x3F);
|
723 | c570fd16 | ths | RETURN(); |
724 | c570fd16 | ths | } |
725 | c570fd16 | ths | |
726 | c570fd16 | ths | void op_drotrv (void) |
727 | c570fd16 | ths | { |
728 | c570fd16 | ths | target_ulong tmp; |
729 | c570fd16 | ths | |
730 | c570fd16 | ths | T0 &= 0x3F;
|
731 | c570fd16 | ths | if (T0) {
|
732 | c570fd16 | ths | tmp = T1 << (0x40 - T0);
|
733 | c570fd16 | ths | T0 = (T1 >> T0) | tmp; |
734 | c570fd16 | ths | } else
|
735 | c570fd16 | ths | T0 = T1; |
736 | c570fd16 | ths | RETURN(); |
737 | c570fd16 | ths | } |
738 | c570fd16 | ths | #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
739 | c570fd16 | ths | |
740 | c570fd16 | ths | void op_dclo (void) |
741 | c570fd16 | ths | { |
742 | c570fd16 | ths | int n;
|
743 | c570fd16 | ths | |
744 | c570fd16 | ths | if (T0 == ~((target_ulong)0)) { |
745 | c570fd16 | ths | T0 = 64;
|
746 | c570fd16 | ths | } else {
|
747 | c570fd16 | ths | for (n = 0; n < 64; n++) { |
748 | c570fd16 | ths | if (!(T0 & (1ULL << 63))) |
749 | c570fd16 | ths | break;
|
750 | c570fd16 | ths | T0 = T0 << 1;
|
751 | c570fd16 | ths | } |
752 | c570fd16 | ths | T0 = n; |
753 | c570fd16 | ths | } |
754 | c570fd16 | ths | RETURN(); |
755 | c570fd16 | ths | } |
756 | c570fd16 | ths | |
757 | c570fd16 | ths | void op_dclz (void) |
758 | c570fd16 | ths | { |
759 | c570fd16 | ths | int n;
|
760 | c570fd16 | ths | |
761 | c570fd16 | ths | if (T0 == 0) { |
762 | c570fd16 | ths | T0 = 64;
|
763 | c570fd16 | ths | } else {
|
764 | c570fd16 | ths | for (n = 0; n < 64; n++) { |
765 | c570fd16 | ths | if (T0 & (1ULL << 63)) |
766 | c570fd16 | ths | break;
|
767 | c570fd16 | ths | T0 = T0 << 1;
|
768 | c570fd16 | ths | } |
769 | c570fd16 | ths | T0 = n; |
770 | c570fd16 | ths | } |
771 | c570fd16 | ths | RETURN(); |
772 | c570fd16 | ths | } |
773 | c570fd16 | ths | #endif
|
774 | c570fd16 | ths | |
775 | c570fd16 | ths | /* 64 bits arithmetic */
|
776 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
|
777 | 6af0bf9c | bellard | void op_mult (void) |
778 | 6af0bf9c | bellard | { |
779 | 6af0bf9c | bellard | CALL_FROM_TB0(do_mult); |
780 | 6af0bf9c | bellard | RETURN(); |
781 | 6af0bf9c | bellard | } |
782 | 6af0bf9c | bellard | |
783 | 6af0bf9c | bellard | void op_multu (void) |
784 | 6af0bf9c | bellard | { |
785 | 6af0bf9c | bellard | CALL_FROM_TB0(do_multu); |
786 | 6af0bf9c | bellard | RETURN(); |
787 | 6af0bf9c | bellard | } |
788 | 6af0bf9c | bellard | |
789 | 6af0bf9c | bellard | void op_madd (void) |
790 | 6af0bf9c | bellard | { |
791 | 6af0bf9c | bellard | CALL_FROM_TB0(do_madd); |
792 | 6af0bf9c | bellard | RETURN(); |
793 | 6af0bf9c | bellard | } |
794 | 6af0bf9c | bellard | |
795 | 6af0bf9c | bellard | void op_maddu (void) |
796 | 6af0bf9c | bellard | { |
797 | 6af0bf9c | bellard | CALL_FROM_TB0(do_maddu); |
798 | 6af0bf9c | bellard | RETURN(); |
799 | 6af0bf9c | bellard | } |
800 | 6af0bf9c | bellard | |
801 | 6af0bf9c | bellard | void op_msub (void) |
802 | 6af0bf9c | bellard | { |
803 | 6af0bf9c | bellard | CALL_FROM_TB0(do_msub); |
804 | 6af0bf9c | bellard | RETURN(); |
805 | 6af0bf9c | bellard | } |
806 | 6af0bf9c | bellard | |
807 | 6af0bf9c | bellard | void op_msubu (void) |
808 | 6af0bf9c | bellard | { |
809 | 6af0bf9c | bellard | CALL_FROM_TB0(do_msubu); |
810 | 6af0bf9c | bellard | RETURN(); |
811 | 6af0bf9c | bellard | } |
812 | c570fd16 | ths | |
813 | c570fd16 | ths | #else /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
814 | c570fd16 | ths | |
815 | c570fd16 | ths | static inline uint64_t get_HILO (void) |
816 | c570fd16 | ths | { |
817 | ead9360e | ths | return ((uint64_t)env->HI[0][env->current_tc] << 32) | |
818 | ead9360e | ths | ((uint64_t)(uint32_t)env->LO[0][env->current_tc]);
|
819 | c570fd16 | ths | } |
820 | c570fd16 | ths | |
821 | c570fd16 | ths | static inline void set_HILO (uint64_t HILO) |
822 | c570fd16 | ths | { |
823 | ead9360e | ths | env->LO[0][env->current_tc] = (int32_t)(HILO & 0xFFFFFFFF); |
824 | ead9360e | ths | env->HI[0][env->current_tc] = (int32_t)(HILO >> 32); |
825 | c570fd16 | ths | } |
826 | c570fd16 | ths | |
827 | c570fd16 | ths | void op_mult (void) |
828 | c570fd16 | ths | { |
829 | c570fd16 | ths | set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
830 | c570fd16 | ths | RETURN(); |
831 | c570fd16 | ths | } |
832 | c570fd16 | ths | |
833 | c570fd16 | ths | void op_multu (void) |
834 | c570fd16 | ths | { |
835 | c570fd16 | ths | set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
836 | c570fd16 | ths | RETURN(); |
837 | c570fd16 | ths | } |
838 | c570fd16 | ths | |
839 | c570fd16 | ths | void op_madd (void) |
840 | c570fd16 | ths | { |
841 | c570fd16 | ths | int64_t tmp; |
842 | c570fd16 | ths | |
843 | c570fd16 | ths | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
844 | c570fd16 | ths | set_HILO((int64_t)get_HILO() + tmp); |
845 | c570fd16 | ths | RETURN(); |
846 | c570fd16 | ths | } |
847 | c570fd16 | ths | |
848 | c570fd16 | ths | void op_maddu (void) |
849 | c570fd16 | ths | { |
850 | c570fd16 | ths | uint64_t tmp; |
851 | c570fd16 | ths | |
852 | c570fd16 | ths | tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
853 | c570fd16 | ths | set_HILO(get_HILO() + tmp); |
854 | c570fd16 | ths | RETURN(); |
855 | c570fd16 | ths | } |
856 | c570fd16 | ths | |
857 | c570fd16 | ths | void op_msub (void) |
858 | c570fd16 | ths | { |
859 | c570fd16 | ths | int64_t tmp; |
860 | c570fd16 | ths | |
861 | c570fd16 | ths | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
862 | c570fd16 | ths | set_HILO((int64_t)get_HILO() - tmp); |
863 | c570fd16 | ths | RETURN(); |
864 | c570fd16 | ths | } |
865 | c570fd16 | ths | |
866 | c570fd16 | ths | void op_msubu (void) |
867 | c570fd16 | ths | { |
868 | c570fd16 | ths | uint64_t tmp; |
869 | c570fd16 | ths | |
870 | c570fd16 | ths | tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
871 | c570fd16 | ths | set_HILO(get_HILO() - tmp); |
872 | c570fd16 | ths | RETURN(); |
873 | c570fd16 | ths | } |
874 | c570fd16 | ths | #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
875 | c570fd16 | ths | |
876 | 60aa19ab | ths | #ifdef TARGET_MIPS64
|
877 | c570fd16 | ths | void op_dmult (void) |
878 | c570fd16 | ths | { |
879 | ead9360e | ths | CALL_FROM_TB4(muls64, &(env->HI[0][env->current_tc]), &(env->LO[0][env->current_tc]), T0, T1); |
880 | c570fd16 | ths | RETURN(); |
881 | c570fd16 | ths | } |
882 | c570fd16 | ths | |
883 | c570fd16 | ths | void op_dmultu (void) |
884 | c570fd16 | ths | { |
885 | ead9360e | ths | CALL_FROM_TB4(mulu64, &(env->HI[0][env->current_tc]), &(env->LO[0][env->current_tc]), T0, T1); |
886 | c570fd16 | ths | RETURN(); |
887 | c570fd16 | ths | } |
888 | 6af0bf9c | bellard | #endif
|
889 | 6af0bf9c | bellard | |
890 | 6af0bf9c | bellard | /* Conditional moves */
|
891 | 6af0bf9c | bellard | void op_movn (void) |
892 | 6af0bf9c | bellard | { |
893 | 6af0bf9c | bellard | if (T1 != 0) |
894 | ead9360e | ths | env->gpr[PARAM1][env->current_tc] = T0; |
895 | 6af0bf9c | bellard | RETURN(); |
896 | 6af0bf9c | bellard | } |
897 | 6af0bf9c | bellard | |
898 | 6af0bf9c | bellard | void op_movz (void) |
899 | 6af0bf9c | bellard | { |
900 | 6af0bf9c | bellard | if (T1 == 0) |
901 | ead9360e | ths | env->gpr[PARAM1][env->current_tc] = T0; |
902 | 6af0bf9c | bellard | RETURN(); |
903 | 6af0bf9c | bellard | } |
904 | 6af0bf9c | bellard | |
905 | 7a387fff | ths | void op_movf (void) |
906 | 7a387fff | ths | { |
907 | ead9360e | ths | if (!(env->fpu->fcr31 & PARAM1))
|
908 | 5a5012ec | ths | T0 = T1; |
909 | 7a387fff | ths | RETURN(); |
910 | 7a387fff | ths | } |
911 | 7a387fff | ths | |
912 | 7a387fff | ths | void op_movt (void) |
913 | 7a387fff | ths | { |
914 | ead9360e | ths | if (env->fpu->fcr31 & PARAM1)
|
915 | 5a5012ec | ths | T0 = T1; |
916 | 7a387fff | ths | RETURN(); |
917 | 7a387fff | ths | } |
918 | 7a387fff | ths | |
919 | 6af0bf9c | bellard | /* Tests */
|
920 | 6af0bf9c | bellard | #define OP_COND(name, cond) \
|
921 | 6af0bf9c | bellard | void glue(op_, name) (void) \ |
922 | 6af0bf9c | bellard | { \ |
923 | 6af0bf9c | bellard | if (cond) { \
|
924 | 6af0bf9c | bellard | T0 = 1; \
|
925 | 6af0bf9c | bellard | } else { \
|
926 | 6af0bf9c | bellard | T0 = 0; \
|
927 | 6af0bf9c | bellard | } \ |
928 | 6af0bf9c | bellard | RETURN(); \ |
929 | 6af0bf9c | bellard | } |
930 | 6af0bf9c | bellard | |
931 | 6af0bf9c | bellard | OP_COND(eq, T0 == T1); |
932 | 6af0bf9c | bellard | OP_COND(ne, T0 != T1); |
933 | f469b9db | ths | OP_COND(ge, (target_long)T0 >= (target_long)T1); |
934 | 6af0bf9c | bellard | OP_COND(geu, T0 >= T1); |
935 | f469b9db | ths | OP_COND(lt, (target_long)T0 < (target_long)T1); |
936 | 6af0bf9c | bellard | OP_COND(ltu, T0 < T1); |
937 | f469b9db | ths | OP_COND(gez, (target_long)T0 >= 0);
|
938 | f469b9db | ths | OP_COND(gtz, (target_long)T0 > 0);
|
939 | f469b9db | ths | OP_COND(lez, (target_long)T0 <= 0);
|
940 | f469b9db | ths | OP_COND(ltz, (target_long)T0 < 0);
|
941 | 6af0bf9c | bellard | |
942 | 7a387fff | ths | /* Branches */
|
943 | c53be334 | bellard | void OPPROTO op_goto_tb0(void) |
944 | c53be334 | bellard | { |
945 | c53be334 | bellard | GOTO_TB(op_goto_tb0, PARAM1, 0);
|
946 | 7a387fff | ths | RETURN(); |
947 | c53be334 | bellard | } |
948 | c53be334 | bellard | |
949 | c53be334 | bellard | void OPPROTO op_goto_tb1(void) |
950 | c53be334 | bellard | { |
951 | c53be334 | bellard | GOTO_TB(op_goto_tb1, PARAM1, 1);
|
952 | 7a387fff | ths | RETURN(); |
953 | c53be334 | bellard | } |
954 | 6af0bf9c | bellard | |
955 | 6af0bf9c | bellard | /* Branch to register */
|
956 | 6af0bf9c | bellard | void op_save_breg_target (void) |
957 | 6af0bf9c | bellard | { |
958 | 6af0bf9c | bellard | env->btarget = T2; |
959 | 7a387fff | ths | RETURN(); |
960 | 6af0bf9c | bellard | } |
961 | 6af0bf9c | bellard | |
962 | 6af0bf9c | bellard | void op_restore_breg_target (void) |
963 | 6af0bf9c | bellard | { |
964 | 6af0bf9c | bellard | T2 = env->btarget; |
965 | 7a387fff | ths | RETURN(); |
966 | 6af0bf9c | bellard | } |
967 | 6af0bf9c | bellard | |
968 | 6af0bf9c | bellard | void op_breg (void) |
969 | 6af0bf9c | bellard | { |
970 | ead9360e | ths | env->PC[env->current_tc] = T2; |
971 | 6af0bf9c | bellard | RETURN(); |
972 | 6af0bf9c | bellard | } |
973 | 6af0bf9c | bellard | |
974 | 6af0bf9c | bellard | void op_save_btarget (void) |
975 | 6af0bf9c | bellard | { |
976 | 6af0bf9c | bellard | env->btarget = PARAM1; |
977 | 6af0bf9c | bellard | RETURN(); |
978 | 6af0bf9c | bellard | } |
979 | 6af0bf9c | bellard | |
980 | 9b9e4393 | ths | #ifdef TARGET_MIPS64
|
981 | 9b9e4393 | ths | void op_save_btarget64 (void) |
982 | 9b9e4393 | ths | { |
983 | 9b9e4393 | ths | env->btarget = ((uint64_t)PARAM1 << 32) | (uint32_t)PARAM2;
|
984 | 9b9e4393 | ths | RETURN(); |
985 | 9b9e4393 | ths | } |
986 | 9b9e4393 | ths | #endif
|
987 | 9b9e4393 | ths | |
988 | 6af0bf9c | bellard | /* Conditional branch */
|
989 | 6af0bf9c | bellard | void op_set_bcond (void) |
990 | 6af0bf9c | bellard | { |
991 | 6af0bf9c | bellard | T2 = T0; |
992 | 6af0bf9c | bellard | RETURN(); |
993 | 6af0bf9c | bellard | } |
994 | 6af0bf9c | bellard | |
995 | 6af0bf9c | bellard | void op_save_bcond (void) |
996 | 6af0bf9c | bellard | { |
997 | 6af0bf9c | bellard | env->bcond = T2; |
998 | 6af0bf9c | bellard | RETURN(); |
999 | 6af0bf9c | bellard | } |
1000 | 6af0bf9c | bellard | |
1001 | 6af0bf9c | bellard | void op_restore_bcond (void) |
1002 | 6af0bf9c | bellard | { |
1003 | 6af0bf9c | bellard | T2 = env->bcond; |
1004 | 6af0bf9c | bellard | RETURN(); |
1005 | 6af0bf9c | bellard | } |
1006 | 6af0bf9c | bellard | |
1007 | c53be334 | bellard | void op_jnz_T2 (void) |
1008 | 6af0bf9c | bellard | { |
1009 | c53be334 | bellard | if (T2)
|
1010 | c53be334 | bellard | GOTO_LABEL_PARAM(1);
|
1011 | 6af0bf9c | bellard | RETURN(); |
1012 | 6af0bf9c | bellard | } |
1013 | 6af0bf9c | bellard | |
1014 | 6af0bf9c | bellard | /* CP0 functions */
|
1015 | 873eb012 | ths | void op_mfc0_index (void) |
1016 | 6af0bf9c | bellard | { |
1017 | 9c2149c8 | ths | T0 = env->CP0_Index; |
1018 | 873eb012 | ths | RETURN(); |
1019 | 873eb012 | ths | } |
1020 | 873eb012 | ths | |
1021 | ead9360e | ths | void op_mfc0_mvpcontrol (void) |
1022 | ead9360e | ths | { |
1023 | ead9360e | ths | T0 = env->mvp->CP0_MVPControl; |
1024 | ead9360e | ths | RETURN(); |
1025 | ead9360e | ths | } |
1026 | ead9360e | ths | |
1027 | ead9360e | ths | void op_mfc0_mvpconf0 (void) |
1028 | ead9360e | ths | { |
1029 | ead9360e | ths | T0 = env->mvp->CP0_MVPConf0; |
1030 | ead9360e | ths | RETURN(); |
1031 | ead9360e | ths | } |
1032 | ead9360e | ths | |
1033 | ead9360e | ths | void op_mfc0_mvpconf1 (void) |
1034 | ead9360e | ths | { |
1035 | ead9360e | ths | T0 = env->mvp->CP0_MVPConf1; |
1036 | ead9360e | ths | RETURN(); |
1037 | ead9360e | ths | } |
1038 | ead9360e | ths | |
1039 | 873eb012 | ths | void op_mfc0_random (void) |
1040 | 873eb012 | ths | { |
1041 | 873eb012 | ths | CALL_FROM_TB0(do_mfc0_random); |
1042 | 873eb012 | ths | RETURN(); |
1043 | 873eb012 | ths | } |
1044 | 873eb012 | ths | |
1045 | ead9360e | ths | void op_mfc0_vpecontrol (void) |
1046 | ead9360e | ths | { |
1047 | ead9360e | ths | T0 = env->CP0_VPEControl; |
1048 | ead9360e | ths | RETURN(); |
1049 | ead9360e | ths | } |
1050 | ead9360e | ths | |
1051 | ead9360e | ths | void op_mfc0_vpeconf0 (void) |
1052 | ead9360e | ths | { |
1053 | ead9360e | ths | T0 = env->CP0_VPEConf0; |
1054 | ead9360e | ths | RETURN(); |
1055 | ead9360e | ths | } |
1056 | ead9360e | ths | |
1057 | ead9360e | ths | void op_mfc0_vpeconf1 (void) |
1058 | ead9360e | ths | { |
1059 | ead9360e | ths | T0 = env->CP0_VPEConf1; |
1060 | ead9360e | ths | RETURN(); |
1061 | ead9360e | ths | } |
1062 | ead9360e | ths | |
1063 | ead9360e | ths | void op_mfc0_yqmask (void) |
1064 | ead9360e | ths | { |
1065 | ead9360e | ths | T0 = env->CP0_YQMask; |
1066 | ead9360e | ths | RETURN(); |
1067 | ead9360e | ths | } |
1068 | ead9360e | ths | |
1069 | ead9360e | ths | void op_mfc0_vpeschedule (void) |
1070 | ead9360e | ths | { |
1071 | ead9360e | ths | T0 = env->CP0_VPESchedule; |
1072 | ead9360e | ths | RETURN(); |
1073 | ead9360e | ths | } |
1074 | ead9360e | ths | |
1075 | ead9360e | ths | void op_mfc0_vpeschefback (void) |
1076 | ead9360e | ths | { |
1077 | ead9360e | ths | T0 = env->CP0_VPEScheFBack; |
1078 | ead9360e | ths | RETURN(); |
1079 | ead9360e | ths | } |
1080 | ead9360e | ths | |
1081 | ead9360e | ths | void op_mfc0_vpeopt (void) |
1082 | ead9360e | ths | { |
1083 | ead9360e | ths | T0 = env->CP0_VPEOpt; |
1084 | ead9360e | ths | RETURN(); |
1085 | ead9360e | ths | } |
1086 | ead9360e | ths | |
1087 | 873eb012 | ths | void op_mfc0_entrylo0 (void) |
1088 | 873eb012 | ths | { |
1089 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_EntryLo0; |
1090 | 873eb012 | ths | RETURN(); |
1091 | 873eb012 | ths | } |
1092 | 873eb012 | ths | |
1093 | ead9360e | ths | void op_mfc0_tcstatus (void) |
1094 | ead9360e | ths | { |
1095 | ead9360e | ths | T0 = env->CP0_TCStatus[env->current_tc]; |
1096 | ead9360e | ths | RETURN(); |
1097 | ead9360e | ths | } |
1098 | ead9360e | ths | |
1099 | ead9360e | ths | void op_mftc0_tcstatus(void) |
1100 | ead9360e | ths | { |
1101 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1102 | ead9360e | ths | |
1103 | ead9360e | ths | T0 = env->CP0_TCStatus[other_tc]; |
1104 | ead9360e | ths | RETURN(); |
1105 | ead9360e | ths | } |
1106 | ead9360e | ths | |
1107 | ead9360e | ths | void op_mfc0_tcbind (void) |
1108 | ead9360e | ths | { |
1109 | ead9360e | ths | T0 = env->CP0_TCBind[env->current_tc]; |
1110 | ead9360e | ths | RETURN(); |
1111 | ead9360e | ths | } |
1112 | ead9360e | ths | |
1113 | ead9360e | ths | void op_mftc0_tcbind(void) |
1114 | ead9360e | ths | { |
1115 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1116 | ead9360e | ths | |
1117 | ead9360e | ths | T0 = env->CP0_TCBind[other_tc]; |
1118 | ead9360e | ths | RETURN(); |
1119 | ead9360e | ths | } |
1120 | ead9360e | ths | |
1121 | ead9360e | ths | void op_mfc0_tcrestart (void) |
1122 | ead9360e | ths | { |
1123 | ead9360e | ths | T0 = env->PC[env->current_tc]; |
1124 | ead9360e | ths | RETURN(); |
1125 | ead9360e | ths | } |
1126 | ead9360e | ths | |
1127 | ead9360e | ths | void op_mftc0_tcrestart(void) |
1128 | ead9360e | ths | { |
1129 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1130 | ead9360e | ths | |
1131 | ead9360e | ths | T0 = env->PC[other_tc]; |
1132 | ead9360e | ths | RETURN(); |
1133 | ead9360e | ths | } |
1134 | ead9360e | ths | |
1135 | ead9360e | ths | void op_mfc0_tchalt (void) |
1136 | ead9360e | ths | { |
1137 | ead9360e | ths | T0 = env->CP0_TCHalt[env->current_tc]; |
1138 | ead9360e | ths | RETURN(); |
1139 | ead9360e | ths | } |
1140 | ead9360e | ths | |
1141 | ead9360e | ths | void op_mftc0_tchalt(void) |
1142 | ead9360e | ths | { |
1143 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1144 | ead9360e | ths | |
1145 | ead9360e | ths | T0 = env->CP0_TCHalt[other_tc]; |
1146 | ead9360e | ths | RETURN(); |
1147 | ead9360e | ths | } |
1148 | ead9360e | ths | |
1149 | ead9360e | ths | void op_mfc0_tccontext (void) |
1150 | ead9360e | ths | { |
1151 | ead9360e | ths | T0 = env->CP0_TCContext[env->current_tc]; |
1152 | ead9360e | ths | RETURN(); |
1153 | ead9360e | ths | } |
1154 | ead9360e | ths | |
1155 | ead9360e | ths | void op_mftc0_tccontext(void) |
1156 | ead9360e | ths | { |
1157 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1158 | ead9360e | ths | |
1159 | ead9360e | ths | T0 = env->CP0_TCContext[other_tc]; |
1160 | ead9360e | ths | RETURN(); |
1161 | ead9360e | ths | } |
1162 | ead9360e | ths | |
1163 | ead9360e | ths | void op_mfc0_tcschedule (void) |
1164 | ead9360e | ths | { |
1165 | ead9360e | ths | T0 = env->CP0_TCSchedule[env->current_tc]; |
1166 | ead9360e | ths | RETURN(); |
1167 | ead9360e | ths | } |
1168 | ead9360e | ths | |
1169 | ead9360e | ths | void op_mftc0_tcschedule(void) |
1170 | ead9360e | ths | { |
1171 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1172 | ead9360e | ths | |
1173 | ead9360e | ths | T0 = env->CP0_TCSchedule[other_tc]; |
1174 | ead9360e | ths | RETURN(); |
1175 | ead9360e | ths | } |
1176 | ead9360e | ths | |
1177 | ead9360e | ths | void op_mfc0_tcschefback (void) |
1178 | ead9360e | ths | { |
1179 | ead9360e | ths | T0 = env->CP0_TCScheFBack[env->current_tc]; |
1180 | ead9360e | ths | RETURN(); |
1181 | ead9360e | ths | } |
1182 | ead9360e | ths | |
1183 | ead9360e | ths | void op_mftc0_tcschefback(void) |
1184 | ead9360e | ths | { |
1185 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1186 | ead9360e | ths | |
1187 | ead9360e | ths | T0 = env->CP0_TCScheFBack[other_tc]; |
1188 | ead9360e | ths | RETURN(); |
1189 | ead9360e | ths | } |
1190 | ead9360e | ths | |
1191 | 873eb012 | ths | void op_mfc0_entrylo1 (void) |
1192 | 873eb012 | ths | { |
1193 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_EntryLo1; |
1194 | 873eb012 | ths | RETURN(); |
1195 | 873eb012 | ths | } |
1196 | 873eb012 | ths | |
1197 | 873eb012 | ths | void op_mfc0_context (void) |
1198 | 873eb012 | ths | { |
1199 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_Context; |
1200 | 873eb012 | ths | RETURN(); |
1201 | 873eb012 | ths | } |
1202 | 873eb012 | ths | |
1203 | 873eb012 | ths | void op_mfc0_pagemask (void) |
1204 | 873eb012 | ths | { |
1205 | 9c2149c8 | ths | T0 = env->CP0_PageMask; |
1206 | 873eb012 | ths | RETURN(); |
1207 | 873eb012 | ths | } |
1208 | 873eb012 | ths | |
1209 | 7a387fff | ths | void op_mfc0_pagegrain (void) |
1210 | 7a387fff | ths | { |
1211 | 9c2149c8 | ths | T0 = env->CP0_PageGrain; |
1212 | 7a387fff | ths | RETURN(); |
1213 | 7a387fff | ths | } |
1214 | 7a387fff | ths | |
1215 | 873eb012 | ths | void op_mfc0_wired (void) |
1216 | 873eb012 | ths | { |
1217 | 9c2149c8 | ths | T0 = env->CP0_Wired; |
1218 | 873eb012 | ths | RETURN(); |
1219 | 873eb012 | ths | } |
1220 | 873eb012 | ths | |
1221 | ead9360e | ths | void op_mfc0_srsconf0 (void) |
1222 | ead9360e | ths | { |
1223 | ead9360e | ths | T0 = env->CP0_SRSConf0; |
1224 | ead9360e | ths | RETURN(); |
1225 | ead9360e | ths | } |
1226 | ead9360e | ths | |
1227 | ead9360e | ths | void op_mfc0_srsconf1 (void) |
1228 | ead9360e | ths | { |
1229 | ead9360e | ths | T0 = env->CP0_SRSConf1; |
1230 | ead9360e | ths | RETURN(); |
1231 | ead9360e | ths | } |
1232 | ead9360e | ths | |
1233 | ead9360e | ths | void op_mfc0_srsconf2 (void) |
1234 | ead9360e | ths | { |
1235 | ead9360e | ths | T0 = env->CP0_SRSConf2; |
1236 | ead9360e | ths | RETURN(); |
1237 | ead9360e | ths | } |
1238 | ead9360e | ths | |
1239 | ead9360e | ths | void op_mfc0_srsconf3 (void) |
1240 | ead9360e | ths | { |
1241 | ead9360e | ths | T0 = env->CP0_SRSConf3; |
1242 | ead9360e | ths | RETURN(); |
1243 | ead9360e | ths | } |
1244 | ead9360e | ths | |
1245 | ead9360e | ths | void op_mfc0_srsconf4 (void) |
1246 | ead9360e | ths | { |
1247 | ead9360e | ths | T0 = env->CP0_SRSConf4; |
1248 | ead9360e | ths | RETURN(); |
1249 | ead9360e | ths | } |
1250 | ead9360e | ths | |
1251 | 7a387fff | ths | void op_mfc0_hwrena (void) |
1252 | 7a387fff | ths | { |
1253 | 9c2149c8 | ths | T0 = env->CP0_HWREna; |
1254 | 7a387fff | ths | RETURN(); |
1255 | 7a387fff | ths | } |
1256 | 7a387fff | ths | |
1257 | 873eb012 | ths | void op_mfc0_badvaddr (void) |
1258 | 873eb012 | ths | { |
1259 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_BadVAddr; |
1260 | 873eb012 | ths | RETURN(); |
1261 | 873eb012 | ths | } |
1262 | 873eb012 | ths | |
1263 | 873eb012 | ths | void op_mfc0_count (void) |
1264 | 873eb012 | ths | { |
1265 | 873eb012 | ths | CALL_FROM_TB0(do_mfc0_count); |
1266 | 873eb012 | ths | RETURN(); |
1267 | 873eb012 | ths | } |
1268 | 873eb012 | ths | |
1269 | 873eb012 | ths | void op_mfc0_entryhi (void) |
1270 | 873eb012 | ths | { |
1271 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_EntryHi; |
1272 | 873eb012 | ths | RETURN(); |
1273 | 873eb012 | ths | } |
1274 | 873eb012 | ths | |
1275 | ead9360e | ths | void op_mftc0_entryhi(void) |
1276 | ead9360e | ths | { |
1277 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1278 | ead9360e | ths | |
1279 | ead9360e | ths | T0 = (env->CP0_EntryHi & ~0xff) | (env->CP0_TCStatus[other_tc] & 0xff); |
1280 | ead9360e | ths | RETURN(); |
1281 | ead9360e | ths | } |
1282 | ead9360e | ths | |
1283 | 873eb012 | ths | void op_mfc0_compare (void) |
1284 | 873eb012 | ths | { |
1285 | 9c2149c8 | ths | T0 = env->CP0_Compare; |
1286 | 873eb012 | ths | RETURN(); |
1287 | 873eb012 | ths | } |
1288 | 873eb012 | ths | |
1289 | 873eb012 | ths | void op_mfc0_status (void) |
1290 | 873eb012 | ths | { |
1291 | 9c2149c8 | ths | T0 = env->CP0_Status; |
1292 | 873eb012 | ths | RETURN(); |
1293 | 873eb012 | ths | } |
1294 | 873eb012 | ths | |
1295 | ead9360e | ths | void op_mftc0_status(void) |
1296 | ead9360e | ths | { |
1297 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1298 | ead9360e | ths | uint32_t tcstatus = env->CP0_TCStatus[other_tc]; |
1299 | ead9360e | ths | |
1300 | ead9360e | ths | T0 = env->CP0_Status & ~0xf1000018;
|
1301 | ead9360e | ths | T0 |= tcstatus & (0xf << CP0TCSt_TCU0);
|
1302 | ead9360e | ths | T0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);
|
1303 | ead9360e | ths | T0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_R0);
|
1304 | ead9360e | ths | RETURN(); |
1305 | ead9360e | ths | } |
1306 | ead9360e | ths | |
1307 | 7a387fff | ths | void op_mfc0_intctl (void) |
1308 | 7a387fff | ths | { |
1309 | 9c2149c8 | ths | T0 = env->CP0_IntCtl; |
1310 | 7a387fff | ths | RETURN(); |
1311 | 7a387fff | ths | } |
1312 | 7a387fff | ths | |
1313 | 7a387fff | ths | void op_mfc0_srsctl (void) |
1314 | 7a387fff | ths | { |
1315 | 9c2149c8 | ths | T0 = env->CP0_SRSCtl; |
1316 | 9c2149c8 | ths | RETURN(); |
1317 | 9c2149c8 | ths | } |
1318 | 9c2149c8 | ths | |
1319 | 9c2149c8 | ths | void op_mfc0_srsmap (void) |
1320 | 9c2149c8 | ths | { |
1321 | 9c2149c8 | ths | T0 = env->CP0_SRSMap; |
1322 | 7a387fff | ths | RETURN(); |
1323 | 7a387fff | ths | } |
1324 | 7a387fff | ths | |
1325 | 873eb012 | ths | void op_mfc0_cause (void) |
1326 | 873eb012 | ths | { |
1327 | 9c2149c8 | ths | T0 = env->CP0_Cause; |
1328 | 873eb012 | ths | RETURN(); |
1329 | 873eb012 | ths | } |
1330 | 873eb012 | ths | |
1331 | 873eb012 | ths | void op_mfc0_epc (void) |
1332 | 873eb012 | ths | { |
1333 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_EPC; |
1334 | 873eb012 | ths | RETURN(); |
1335 | 873eb012 | ths | } |
1336 | 873eb012 | ths | |
1337 | 873eb012 | ths | void op_mfc0_prid (void) |
1338 | 873eb012 | ths | { |
1339 | 9c2149c8 | ths | T0 = env->CP0_PRid; |
1340 | 873eb012 | ths | RETURN(); |
1341 | 873eb012 | ths | } |
1342 | 873eb012 | ths | |
1343 | 7a387fff | ths | void op_mfc0_ebase (void) |
1344 | 7a387fff | ths | { |
1345 | b29a0341 | ths | T0 = env->CP0_EBase; |
1346 | 7a387fff | ths | RETURN(); |
1347 | 7a387fff | ths | } |
1348 | 7a387fff | ths | |
1349 | 873eb012 | ths | void op_mfc0_config0 (void) |
1350 | 873eb012 | ths | { |
1351 | 9c2149c8 | ths | T0 = env->CP0_Config0; |
1352 | 873eb012 | ths | RETURN(); |
1353 | 873eb012 | ths | } |
1354 | 873eb012 | ths | |
1355 | 873eb012 | ths | void op_mfc0_config1 (void) |
1356 | 873eb012 | ths | { |
1357 | 9c2149c8 | ths | T0 = env->CP0_Config1; |
1358 | 873eb012 | ths | RETURN(); |
1359 | 873eb012 | ths | } |
1360 | 873eb012 | ths | |
1361 | 7a387fff | ths | void op_mfc0_config2 (void) |
1362 | 7a387fff | ths | { |
1363 | 9c2149c8 | ths | T0 = env->CP0_Config2; |
1364 | 7a387fff | ths | RETURN(); |
1365 | 7a387fff | ths | } |
1366 | 7a387fff | ths | |
1367 | 7a387fff | ths | void op_mfc0_config3 (void) |
1368 | 7a387fff | ths | { |
1369 | 9c2149c8 | ths | T0 = env->CP0_Config3; |
1370 | 7a387fff | ths | RETURN(); |
1371 | 7a387fff | ths | } |
1372 | 7a387fff | ths | |
1373 | e397ee33 | ths | void op_mfc0_config6 (void) |
1374 | e397ee33 | ths | { |
1375 | e397ee33 | ths | T0 = env->CP0_Config6; |
1376 | e397ee33 | ths | RETURN(); |
1377 | e397ee33 | ths | } |
1378 | e397ee33 | ths | |
1379 | e397ee33 | ths | void op_mfc0_config7 (void) |
1380 | e397ee33 | ths | { |
1381 | e397ee33 | ths | T0 = env->CP0_Config7; |
1382 | e397ee33 | ths | RETURN(); |
1383 | e397ee33 | ths | } |
1384 | e397ee33 | ths | |
1385 | 873eb012 | ths | void op_mfc0_lladdr (void) |
1386 | 873eb012 | ths | { |
1387 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_LLAddr >> 4;
|
1388 | 873eb012 | ths | RETURN(); |
1389 | 873eb012 | ths | } |
1390 | 873eb012 | ths | |
1391 | fd88b6ab | ths | void op_mfc0_watchlo (void) |
1392 | 873eb012 | ths | { |
1393 | fd88b6ab | ths | T0 = (int32_t)env->CP0_WatchLo[PARAM1]; |
1394 | 873eb012 | ths | RETURN(); |
1395 | 873eb012 | ths | } |
1396 | 873eb012 | ths | |
1397 | fd88b6ab | ths | void op_mfc0_watchhi (void) |
1398 | 873eb012 | ths | { |
1399 | fd88b6ab | ths | T0 = env->CP0_WatchHi[PARAM1]; |
1400 | 873eb012 | ths | RETURN(); |
1401 | 873eb012 | ths | } |
1402 | 873eb012 | ths | |
1403 | 7a387fff | ths | void op_mfc0_xcontext (void) |
1404 | 7a387fff | ths | { |
1405 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_XContext; |
1406 | 7a387fff | ths | RETURN(); |
1407 | 7a387fff | ths | } |
1408 | 7a387fff | ths | |
1409 | 7a387fff | ths | void op_mfc0_framemask (void) |
1410 | 7a387fff | ths | { |
1411 | 7a387fff | ths | T0 = env->CP0_Framemask; |
1412 | 7a387fff | ths | RETURN(); |
1413 | 7a387fff | ths | } |
1414 | 7a387fff | ths | |
1415 | 873eb012 | ths | void op_mfc0_debug (void) |
1416 | 873eb012 | ths | { |
1417 | 9c2149c8 | ths | T0 = env->CP0_Debug; |
1418 | 873eb012 | ths | if (env->hflags & MIPS_HFLAG_DM)
|
1419 | 873eb012 | ths | T0 |= 1 << CP0DB_DM;
|
1420 | 873eb012 | ths | RETURN(); |
1421 | 873eb012 | ths | } |
1422 | 873eb012 | ths | |
1423 | ead9360e | ths | void op_mftc0_debug(void) |
1424 | ead9360e | ths | { |
1425 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1426 | ead9360e | ths | |
1427 | ead9360e | ths | /* XXX: Might be wrong, check with EJTAG spec. */
|
1428 | ead9360e | ths | T0 = (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | |
1429 | ead9360e | ths | (env->CP0_Debug_tcstatus[other_tc] & |
1430 | ead9360e | ths | ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); |
1431 | ead9360e | ths | RETURN(); |
1432 | ead9360e | ths | } |
1433 | ead9360e | ths | |
1434 | 873eb012 | ths | void op_mfc0_depc (void) |
1435 | 873eb012 | ths | { |
1436 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_DEPC; |
1437 | 873eb012 | ths | RETURN(); |
1438 | 873eb012 | ths | } |
1439 | 873eb012 | ths | |
1440 | 7a387fff | ths | void op_mfc0_performance0 (void) |
1441 | 7a387fff | ths | { |
1442 | 9c2149c8 | ths | T0 = env->CP0_Performance0; |
1443 | 7a387fff | ths | RETURN(); |
1444 | 7a387fff | ths | } |
1445 | 7a387fff | ths | |
1446 | 873eb012 | ths | void op_mfc0_taglo (void) |
1447 | 873eb012 | ths | { |
1448 | 9c2149c8 | ths | T0 = env->CP0_TagLo; |
1449 | 873eb012 | ths | RETURN(); |
1450 | 873eb012 | ths | } |
1451 | 873eb012 | ths | |
1452 | 873eb012 | ths | void op_mfc0_datalo (void) |
1453 | 873eb012 | ths | { |
1454 | 9c2149c8 | ths | T0 = env->CP0_DataLo; |
1455 | 873eb012 | ths | RETURN(); |
1456 | 873eb012 | ths | } |
1457 | 873eb012 | ths | |
1458 | 7a387fff | ths | void op_mfc0_taghi (void) |
1459 | 7a387fff | ths | { |
1460 | 9c2149c8 | ths | T0 = env->CP0_TagHi; |
1461 | 7a387fff | ths | RETURN(); |
1462 | 7a387fff | ths | } |
1463 | 7a387fff | ths | |
1464 | 7a387fff | ths | void op_mfc0_datahi (void) |
1465 | 7a387fff | ths | { |
1466 | 9c2149c8 | ths | T0 = env->CP0_DataHi; |
1467 | 7a387fff | ths | RETURN(); |
1468 | 7a387fff | ths | } |
1469 | 7a387fff | ths | |
1470 | 873eb012 | ths | void op_mfc0_errorepc (void) |
1471 | 873eb012 | ths | { |
1472 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_ErrorEPC; |
1473 | 873eb012 | ths | RETURN(); |
1474 | 873eb012 | ths | } |
1475 | 873eb012 | ths | |
1476 | 873eb012 | ths | void op_mfc0_desave (void) |
1477 | 873eb012 | ths | { |
1478 | 9c2149c8 | ths | T0 = env->CP0_DESAVE; |
1479 | 6af0bf9c | bellard | RETURN(); |
1480 | 6af0bf9c | bellard | } |
1481 | 6af0bf9c | bellard | |
1482 | 8c0fdd85 | ths | void op_mtc0_index (void) |
1483 | 6af0bf9c | bellard | { |
1484 | ead9360e | ths | env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 % env->tlb->nb_tlb);
|
1485 | ead9360e | ths | RETURN(); |
1486 | ead9360e | ths | } |
1487 | ead9360e | ths | |
1488 | ead9360e | ths | void op_mtc0_mvpcontrol (void) |
1489 | ead9360e | ths | { |
1490 | ead9360e | ths | uint32_t mask = 0;
|
1491 | ead9360e | ths | uint32_t newval; |
1492 | ead9360e | ths | |
1493 | ead9360e | ths | if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) |
1494 | ead9360e | ths | mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) | |
1495 | ead9360e | ths | (1 << CP0MVPCo_EVP);
|
1496 | ead9360e | ths | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
1497 | ead9360e | ths | mask |= (1 << CP0MVPCo_STLB);
|
1498 | ead9360e | ths | newval = (env->mvp->CP0_MVPControl & ~mask) | (T0 & mask); |
1499 | ead9360e | ths | |
1500 | ead9360e | ths | // TODO: Enable/disable shared TLB, enable/disable VPEs.
|
1501 | ead9360e | ths | |
1502 | ead9360e | ths | env->mvp->CP0_MVPControl = newval; |
1503 | ead9360e | ths | RETURN(); |
1504 | ead9360e | ths | } |
1505 | ead9360e | ths | |
1506 | ead9360e | ths | void op_mtc0_vpecontrol (void) |
1507 | ead9360e | ths | { |
1508 | ead9360e | ths | uint32_t mask; |
1509 | ead9360e | ths | uint32_t newval; |
1510 | ead9360e | ths | |
1511 | ead9360e | ths | mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) | |
1512 | ead9360e | ths | (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC); |
1513 | ead9360e | ths | newval = (env->CP0_VPEControl & ~mask) | (T0 & mask); |
1514 | ead9360e | ths | |
1515 | ead9360e | ths | /* Yield scheduler intercept not implemented. */
|
1516 | ead9360e | ths | /* Gating storage scheduler intercept not implemented. */
|
1517 | ead9360e | ths | |
1518 | ead9360e | ths | // TODO: Enable/disable TCs.
|
1519 | ead9360e | ths | |
1520 | ead9360e | ths | env->CP0_VPEControl = newval; |
1521 | ead9360e | ths | RETURN(); |
1522 | ead9360e | ths | } |
1523 | ead9360e | ths | |
1524 | ead9360e | ths | void op_mtc0_vpeconf0 (void) |
1525 | ead9360e | ths | { |
1526 | ead9360e | ths | uint32_t mask = 0;
|
1527 | ead9360e | ths | uint32_t newval; |
1528 | ead9360e | ths | |
1529 | ead9360e | ths | if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { |
1530 | ead9360e | ths | if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) |
1531 | ead9360e | ths | mask |= (0xff << CP0VPEC0_XTC);
|
1532 | ead9360e | ths | mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); |
1533 | ead9360e | ths | } |
1534 | ead9360e | ths | newval = (env->CP0_VPEConf0 & ~mask) | (T0 & mask); |
1535 | ead9360e | ths | |
1536 | ead9360e | ths | // TODO: TC exclusive handling due to ERL/EXL.
|
1537 | ead9360e | ths | |
1538 | ead9360e | ths | env->CP0_VPEConf0 = newval; |
1539 | ead9360e | ths | RETURN(); |
1540 | ead9360e | ths | } |
1541 | ead9360e | ths | |
1542 | ead9360e | ths | void op_mtc0_vpeconf1 (void) |
1543 | ead9360e | ths | { |
1544 | ead9360e | ths | uint32_t mask = 0;
|
1545 | ead9360e | ths | uint32_t newval; |
1546 | ead9360e | ths | |
1547 | ead9360e | ths | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
1548 | ead9360e | ths | mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) | |
1549 | ead9360e | ths | (0xff << CP0VPEC1_NCP1);
|
1550 | ead9360e | ths | newval = (env->CP0_VPEConf1 & ~mask) | (T0 & mask); |
1551 | ead9360e | ths | |
1552 | ead9360e | ths | /* UDI not implemented. */
|
1553 | ead9360e | ths | /* CP2 not implemented. */
|
1554 | ead9360e | ths | |
1555 | ead9360e | ths | // TODO: Handle FPU (CP1) binding.
|
1556 | ead9360e | ths | |
1557 | ead9360e | ths | env->CP0_VPEConf1 = newval; |
1558 | ead9360e | ths | RETURN(); |
1559 | ead9360e | ths | } |
1560 | ead9360e | ths | |
1561 | ead9360e | ths | void op_mtc0_yqmask (void) |
1562 | ead9360e | ths | { |
1563 | ead9360e | ths | /* Yield qualifier inputs not implemented. */
|
1564 | ead9360e | ths | env->CP0_YQMask = 0x00000000;
|
1565 | ead9360e | ths | RETURN(); |
1566 | ead9360e | ths | } |
1567 | ead9360e | ths | |
1568 | ead9360e | ths | void op_mtc0_vpeschedule (void) |
1569 | ead9360e | ths | { |
1570 | ead9360e | ths | env->CP0_VPESchedule = T0; |
1571 | ead9360e | ths | RETURN(); |
1572 | ead9360e | ths | } |
1573 | ead9360e | ths | |
1574 | ead9360e | ths | void op_mtc0_vpeschefback (void) |
1575 | ead9360e | ths | { |
1576 | ead9360e | ths | env->CP0_VPEScheFBack = T0; |
1577 | ead9360e | ths | RETURN(); |
1578 | ead9360e | ths | } |
1579 | ead9360e | ths | |
1580 | ead9360e | ths | void op_mtc0_vpeopt (void) |
1581 | ead9360e | ths | { |
1582 | ead9360e | ths | env->CP0_VPEOpt = T0 & 0x0000ffff;
|
1583 | 8c0fdd85 | ths | RETURN(); |
1584 | 8c0fdd85 | ths | } |
1585 | 8c0fdd85 | ths | |
1586 | 8c0fdd85 | ths | void op_mtc0_entrylo0 (void) |
1587 | 8c0fdd85 | ths | { |
1588 | 7a387fff | ths | /* Large physaddr not implemented */
|
1589 | 7a387fff | ths | /* 1k pages not implemented */
|
1590 | f1b0aa5d | ths | env->CP0_EntryLo0 = T0 & 0x3FFFFFFF;
|
1591 | 8c0fdd85 | ths | RETURN(); |
1592 | 8c0fdd85 | ths | } |
1593 | 8c0fdd85 | ths | |
1594 | ead9360e | ths | void op_mtc0_tcstatus (void) |
1595 | ead9360e | ths | { |
1596 | ead9360e | ths | uint32_t mask = env->CP0_TCStatus_rw_bitmask; |
1597 | ead9360e | ths | uint32_t newval; |
1598 | ead9360e | ths | |
1599 | ead9360e | ths | newval = (env->CP0_TCStatus[env->current_tc] & ~mask) | (T0 & mask); |
1600 | ead9360e | ths | |
1601 | ead9360e | ths | // TODO: Sync with CP0_Status.
|
1602 | ead9360e | ths | |
1603 | ead9360e | ths | env->CP0_TCStatus[env->current_tc] = newval; |
1604 | ead9360e | ths | RETURN(); |
1605 | ead9360e | ths | } |
1606 | ead9360e | ths | |
1607 | ead9360e | ths | void op_mttc0_tcstatus (void) |
1608 | ead9360e | ths | { |
1609 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1610 | ead9360e | ths | |
1611 | ead9360e | ths | // TODO: Sync with CP0_Status.
|
1612 | ead9360e | ths | |
1613 | ead9360e | ths | env->CP0_TCStatus[other_tc] = T0; |
1614 | ead9360e | ths | RETURN(); |
1615 | ead9360e | ths | } |
1616 | ead9360e | ths | |
1617 | ead9360e | ths | void op_mtc0_tcbind (void) |
1618 | ead9360e | ths | { |
1619 | ead9360e | ths | uint32_t mask = (1 << CP0TCBd_TBE);
|
1620 | ead9360e | ths | uint32_t newval; |
1621 | ead9360e | ths | |
1622 | ead9360e | ths | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
1623 | ead9360e | ths | mask |= (1 << CP0TCBd_CurVPE);
|
1624 | ead9360e | ths | newval = (env->CP0_TCBind[env->current_tc] & ~mask) | (T0 & mask); |
1625 | ead9360e | ths | env->CP0_TCBind[env->current_tc] = newval; |
1626 | ead9360e | ths | RETURN(); |
1627 | ead9360e | ths | } |
1628 | ead9360e | ths | |
1629 | ead9360e | ths | void op_mttc0_tcbind (void) |
1630 | ead9360e | ths | { |
1631 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1632 | ead9360e | ths | uint32_t mask = (1 << CP0TCBd_TBE);
|
1633 | ead9360e | ths | uint32_t newval; |
1634 | ead9360e | ths | |
1635 | ead9360e | ths | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
1636 | ead9360e | ths | mask |= (1 << CP0TCBd_CurVPE);
|
1637 | ead9360e | ths | newval = (env->CP0_TCBind[other_tc] & ~mask) | (T0 & mask); |
1638 | ead9360e | ths | env->CP0_TCBind[other_tc] = newval; |
1639 | ead9360e | ths | RETURN(); |
1640 | ead9360e | ths | } |
1641 | ead9360e | ths | |
1642 | ead9360e | ths | void op_mtc0_tcrestart (void) |
1643 | ead9360e | ths | { |
1644 | ead9360e | ths | env->PC[env->current_tc] = T0; |
1645 | ead9360e | ths | env->CP0_TCStatus[env->current_tc] &= ~(1 << CP0TCSt_TDS);
|
1646 | ead9360e | ths | env->CP0_LLAddr = 0ULL;
|
1647 | ead9360e | ths | /* MIPS16 not implemented. */
|
1648 | ead9360e | ths | RETURN(); |
1649 | ead9360e | ths | } |
1650 | ead9360e | ths | |
1651 | ead9360e | ths | void op_mttc0_tcrestart (void) |
1652 | ead9360e | ths | { |
1653 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1654 | ead9360e | ths | |
1655 | ead9360e | ths | env->PC[other_tc] = T0; |
1656 | ead9360e | ths | env->CP0_TCStatus[other_tc] &= ~(1 << CP0TCSt_TDS);
|
1657 | ead9360e | ths | env->CP0_LLAddr = 0ULL;
|
1658 | ead9360e | ths | /* MIPS16 not implemented. */
|
1659 | ead9360e | ths | RETURN(); |
1660 | ead9360e | ths | } |
1661 | ead9360e | ths | |
1662 | ead9360e | ths | void op_mtc0_tchalt (void) |
1663 | ead9360e | ths | { |
1664 | ead9360e | ths | env->CP0_TCHalt[env->current_tc] = T0 & 0x1;
|
1665 | ead9360e | ths | |
1666 | ead9360e | ths | // TODO: Halt TC / Restart (if allocated+active) TC.
|
1667 | ead9360e | ths | |
1668 | ead9360e | ths | RETURN(); |
1669 | ead9360e | ths | } |
1670 | ead9360e | ths | |
1671 | ead9360e | ths | void op_mttc0_tchalt (void) |
1672 | ead9360e | ths | { |
1673 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1674 | ead9360e | ths | |
1675 | ead9360e | ths | // TODO: Halt TC / Restart (if allocated+active) TC.
|
1676 | ead9360e | ths | |
1677 | ead9360e | ths | env->CP0_TCHalt[other_tc] = T0; |
1678 | ead9360e | ths | RETURN(); |
1679 | ead9360e | ths | } |
1680 | ead9360e | ths | |
1681 | ead9360e | ths | void op_mtc0_tccontext (void) |
1682 | ead9360e | ths | { |
1683 | ead9360e | ths | env->CP0_TCContext[env->current_tc] = T0; |
1684 | ead9360e | ths | RETURN(); |
1685 | ead9360e | ths | } |
1686 | ead9360e | ths | |
1687 | ead9360e | ths | void op_mttc0_tccontext (void) |
1688 | ead9360e | ths | { |
1689 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1690 | ead9360e | ths | |
1691 | ead9360e | ths | env->CP0_TCContext[other_tc] = T0; |
1692 | ead9360e | ths | RETURN(); |
1693 | ead9360e | ths | } |
1694 | ead9360e | ths | |
1695 | ead9360e | ths | void op_mtc0_tcschedule (void) |
1696 | ead9360e | ths | { |
1697 | ead9360e | ths | env->CP0_TCSchedule[env->current_tc] = T0; |
1698 | ead9360e | ths | RETURN(); |
1699 | ead9360e | ths | } |
1700 | ead9360e | ths | |
1701 | ead9360e | ths | void op_mttc0_tcschedule (void) |
1702 | ead9360e | ths | { |
1703 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1704 | ead9360e | ths | |
1705 | ead9360e | ths | env->CP0_TCSchedule[other_tc] = T0; |
1706 | ead9360e | ths | RETURN(); |
1707 | ead9360e | ths | } |
1708 | ead9360e | ths | |
1709 | ead9360e | ths | void op_mtc0_tcschefback (void) |
1710 | ead9360e | ths | { |
1711 | ead9360e | ths | env->CP0_TCScheFBack[env->current_tc] = T0; |
1712 | ead9360e | ths | RETURN(); |
1713 | ead9360e | ths | } |
1714 | ead9360e | ths | |
1715 | ead9360e | ths | void op_mttc0_tcschefback (void) |
1716 | ead9360e | ths | { |
1717 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1718 | ead9360e | ths | |
1719 | ead9360e | ths | env->CP0_TCScheFBack[other_tc] = T0; |
1720 | ead9360e | ths | RETURN(); |
1721 | ead9360e | ths | } |
1722 | ead9360e | ths | |
1723 | 8c0fdd85 | ths | void op_mtc0_entrylo1 (void) |
1724 | 8c0fdd85 | ths | { |
1725 | 7a387fff | ths | /* Large physaddr not implemented */
|
1726 | 7a387fff | ths | /* 1k pages not implemented */
|
1727 | f1b0aa5d | ths | env->CP0_EntryLo1 = T0 & 0x3FFFFFFF;
|
1728 | 8c0fdd85 | ths | RETURN(); |
1729 | 8c0fdd85 | ths | } |
1730 | 8c0fdd85 | ths | |
1731 | 8c0fdd85 | ths | void op_mtc0_context (void) |
1732 | 8c0fdd85 | ths | { |
1733 | 534ce69f | ths | env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF); |
1734 | 8c0fdd85 | ths | RETURN(); |
1735 | 8c0fdd85 | ths | } |
1736 | 8c0fdd85 | ths | |
1737 | 8c0fdd85 | ths | void op_mtc0_pagemask (void) |
1738 | 8c0fdd85 | ths | { |
1739 | 7a387fff | ths | /* 1k pages not implemented */
|
1740 | f2e9ebef | ths | env->CP0_PageMask = T0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1)); |
1741 | 7a387fff | ths | RETURN(); |
1742 | 7a387fff | ths | } |
1743 | 7a387fff | ths | |
1744 | 7a387fff | ths | void op_mtc0_pagegrain (void) |
1745 | 7a387fff | ths | { |
1746 | 7a387fff | ths | /* SmartMIPS not implemented */
|
1747 | 7a387fff | ths | /* Large physaddr not implemented */
|
1748 | 7a387fff | ths | /* 1k pages not implemented */
|
1749 | 7a387fff | ths | env->CP0_PageGrain = 0;
|
1750 | 8c0fdd85 | ths | RETURN(); |
1751 | 8c0fdd85 | ths | } |
1752 | 8c0fdd85 | ths | |
1753 | 8c0fdd85 | ths | void op_mtc0_wired (void) |
1754 | 8c0fdd85 | ths | { |
1755 | ead9360e | ths | env->CP0_Wired = T0 % env->tlb->nb_tlb; |
1756 | ead9360e | ths | RETURN(); |
1757 | ead9360e | ths | } |
1758 | ead9360e | ths | |
1759 | ead9360e | ths | void op_mtc0_srsconf0 (void) |
1760 | ead9360e | ths | { |
1761 | ead9360e | ths | env->CP0_SRSConf0 |= T0 & env->CP0_SRSConf0_rw_bitmask; |
1762 | ead9360e | ths | RETURN(); |
1763 | ead9360e | ths | } |
1764 | ead9360e | ths | |
1765 | ead9360e | ths | void op_mtc0_srsconf1 (void) |
1766 | ead9360e | ths | { |
1767 | ead9360e | ths | env->CP0_SRSConf1 |= T0 & env->CP0_SRSConf1_rw_bitmask; |
1768 | ead9360e | ths | RETURN(); |
1769 | ead9360e | ths | } |
1770 | ead9360e | ths | |
1771 | ead9360e | ths | void op_mtc0_srsconf2 (void) |
1772 | ead9360e | ths | { |
1773 | ead9360e | ths | env->CP0_SRSConf2 |= T0 & env->CP0_SRSConf2_rw_bitmask; |
1774 | ead9360e | ths | RETURN(); |
1775 | ead9360e | ths | } |
1776 | ead9360e | ths | |
1777 | ead9360e | ths | void op_mtc0_srsconf3 (void) |
1778 | ead9360e | ths | { |
1779 | ead9360e | ths | env->CP0_SRSConf3 |= T0 & env->CP0_SRSConf3_rw_bitmask; |
1780 | ead9360e | ths | RETURN(); |
1781 | ead9360e | ths | } |
1782 | ead9360e | ths | |
1783 | ead9360e | ths | void op_mtc0_srsconf4 (void) |
1784 | ead9360e | ths | { |
1785 | ead9360e | ths | env->CP0_SRSConf4 |= T0 & env->CP0_SRSConf4_rw_bitmask; |
1786 | 7a387fff | ths | RETURN(); |
1787 | 7a387fff | ths | } |
1788 | 7a387fff | ths | |
1789 | 7a387fff | ths | void op_mtc0_hwrena (void) |
1790 | 7a387fff | ths | { |
1791 | 7a387fff | ths | env->CP0_HWREna = T0 & 0x0000000F;
|
1792 | 8c0fdd85 | ths | RETURN(); |
1793 | 8c0fdd85 | ths | } |
1794 | 8c0fdd85 | ths | |
1795 | 8c0fdd85 | ths | void op_mtc0_count (void) |
1796 | 8c0fdd85 | ths | { |
1797 | 8c0fdd85 | ths | CALL_FROM_TB2(cpu_mips_store_count, env, T0); |
1798 | 8c0fdd85 | ths | RETURN(); |
1799 | 8c0fdd85 | ths | } |
1800 | 8c0fdd85 | ths | |
1801 | 8c0fdd85 | ths | void op_mtc0_entryhi (void) |
1802 | 8c0fdd85 | ths | { |
1803 | 0feef828 | ths | target_ulong old, val; |
1804 | 8c0fdd85 | ths | |
1805 | 7a387fff | ths | /* 1k pages not implemented */
|
1806 | 100ce988 | ths | val = T0 & ((TARGET_PAGE_MASK << 1) | 0xFF); |
1807 | 100ce988 | ths | #ifdef TARGET_MIPS64
|
1808 | e034e2c3 | ths | val &= env->SEGMask; |
1809 | 100ce988 | ths | #endif
|
1810 | 8c0fdd85 | ths | old = env->CP0_EntryHi; |
1811 | 8c0fdd85 | ths | env->CP0_EntryHi = val; |
1812 | ead9360e | ths | if (env->CP0_Config3 & (1 << CP0C3_MT)) { |
1813 | ead9360e | ths | uint32_t tcst = env->CP0_TCStatus[env->current_tc] & ~0xff;
|
1814 | ead9360e | ths | env->CP0_TCStatus[env->current_tc] = tcst | (val & 0xff);
|
1815 | ead9360e | ths | } |
1816 | 8c0fdd85 | ths | /* If the ASID changes, flush qemu's TLB. */
|
1817 | 8c0fdd85 | ths | if ((old & 0xFF) != (val & 0xFF)) |
1818 | 8c0fdd85 | ths | CALL_FROM_TB2(cpu_mips_tlb_flush, env, 1);
|
1819 | 8c0fdd85 | ths | RETURN(); |
1820 | 8c0fdd85 | ths | } |
1821 | 8c0fdd85 | ths | |
1822 | ead9360e | ths | void op_mttc0_entryhi(void) |
1823 | ead9360e | ths | { |
1824 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1825 | ead9360e | ths | |
1826 | ead9360e | ths | env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (T0 & ~0xff); |
1827 | ead9360e | ths | env->CP0_TCStatus[other_tc] = (env->CP0_TCStatus[other_tc] & ~0xff) | (T0 & 0xff); |
1828 | ead9360e | ths | RETURN(); |
1829 | ead9360e | ths | } |
1830 | ead9360e | ths | |
1831 | 8c0fdd85 | ths | void op_mtc0_compare (void) |
1832 | 8c0fdd85 | ths | { |
1833 | 8c0fdd85 | ths | CALL_FROM_TB2(cpu_mips_store_compare, env, T0); |
1834 | 8c0fdd85 | ths | RETURN(); |
1835 | 8c0fdd85 | ths | } |
1836 | 8c0fdd85 | ths | |
1837 | 8c0fdd85 | ths | void op_mtc0_status (void) |
1838 | 8c0fdd85 | ths | { |
1839 | 4de9b249 | ths | uint32_t val, old; |
1840 | ead9360e | ths | uint32_t mask = env->CP0_Status_rw_bitmask; |
1841 | 8c0fdd85 | ths | |
1842 | f1b0aa5d | ths | val = T0 & mask; |
1843 | 8c0fdd85 | ths | old = env->CP0_Status; |
1844 | f41c52f1 | ths | if (!(val & (1 << CP0St_EXL)) && |
1845 | f41c52f1 | ths | !(val & (1 << CP0St_ERL)) &&
|
1846 | f41c52f1 | ths | !(env->hflags & MIPS_HFLAG_DM) && |
1847 | f41c52f1 | ths | (val & (1 << CP0St_UM)))
|
1848 | f41c52f1 | ths | env->hflags |= MIPS_HFLAG_UM; |
1849 | 6e473128 | ths | #ifdef TARGET_MIPS64
|
1850 | 3ddf0b5c | ths | if (!(env->CP0_Config0 & (0x3 << CP0C0_AT)) || |
1851 | 3ddf0b5c | ths | ((env->hflags & MIPS_HFLAG_UM) && |
1852 | 6e473128 | ths | !(val & (1 << CP0St_PX)) &&
|
1853 | 3ddf0b5c | ths | !(val & (1 << CP0St_UX))))
|
1854 | 6e473128 | ths | env->hflags &= ~MIPS_HFLAG_64; |
1855 | 6e473128 | ths | #endif
|
1856 | 5e755519 | ths | if (val & (1 << CP0St_CU1)) |
1857 | 5e755519 | ths | env->hflags |= MIPS_HFLAG_FPU; |
1858 | 5e755519 | ths | else
|
1859 | 5e755519 | ths | env->hflags &= ~MIPS_HFLAG_FPU; |
1860 | 5e755519 | ths | if (val & (1 << CP0St_FR)) |
1861 | 5e755519 | ths | env->hflags |= MIPS_HFLAG_F64; |
1862 | 5e755519 | ths | else
|
1863 | 5e755519 | ths | env->hflags &= ~MIPS_HFLAG_F64; |
1864 | 5a5012ec | ths | env->CP0_Status = (env->CP0_Status & ~mask) | val; |
1865 | f41c52f1 | ths | if (loglevel & CPU_LOG_EXEC)
|
1866 | f41c52f1 | ths | CALL_FROM_TB2(do_mtc0_status_debug, old, val); |
1867 | 4de9b249 | ths | CALL_FROM_TB1(cpu_mips_update_irq, env); |
1868 | 8c0fdd85 | ths | RETURN(); |
1869 | 8c0fdd85 | ths | } |
1870 | 8c0fdd85 | ths | |
1871 | ead9360e | ths | void op_mttc0_status(void) |
1872 | ead9360e | ths | { |
1873 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1874 | ead9360e | ths | uint32_t tcstatus = env->CP0_TCStatus[other_tc]; |
1875 | ead9360e | ths | |
1876 | ead9360e | ths | env->CP0_Status = T0 & ~0xf1000018;
|
1877 | ead9360e | ths | tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (T0 & (0xf << CP0St_CU0)); |
1878 | ead9360e | ths | tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((T0 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX)); |
1879 | ead9360e | ths | tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((T0 & (0x3 << CP0St_R0)) << (CP0TCSt_TKSU - CP0St_R0)); |
1880 | ead9360e | ths | env->CP0_TCStatus[other_tc] = tcstatus; |
1881 | ead9360e | ths | RETURN(); |
1882 | ead9360e | ths | } |
1883 | ead9360e | ths | |
1884 | 7a387fff | ths | void op_mtc0_intctl (void) |
1885 | 7a387fff | ths | { |
1886 | c090a8f4 | ths | /* vectored interrupts not implemented, timer on int 7,
|
1887 | c090a8f4 | ths | no performance counters. */
|
1888 | c090a8f4 | ths | env->CP0_IntCtl |= T0 & 0x000002e0;
|
1889 | 7a387fff | ths | RETURN(); |
1890 | 7a387fff | ths | } |
1891 | 7a387fff | ths | |
1892 | 7a387fff | ths | void op_mtc0_srsctl (void) |
1893 | 7a387fff | ths | { |
1894 | ead9360e | ths | uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS); |
1895 | ead9360e | ths | env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (T0 & mask); |
1896 | 7a387fff | ths | RETURN(); |
1897 | 7a387fff | ths | } |
1898 | 7a387fff | ths | |
1899 | 9c2149c8 | ths | void op_mtc0_srsmap (void) |
1900 | 9c2149c8 | ths | { |
1901 | ead9360e | ths | env->CP0_SRSMap = T0; |
1902 | 9c2149c8 | ths | RETURN(); |
1903 | 9c2149c8 | ths | } |
1904 | 9c2149c8 | ths | |
1905 | 8c0fdd85 | ths | void op_mtc0_cause (void) |
1906 | 8c0fdd85 | ths | { |
1907 | 39d51eb8 | ths | uint32_t mask = 0x00C00300;
|
1908 | 39d51eb8 | ths | |
1909 | 39d51eb8 | ths | if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR)) |
1910 | 39d51eb8 | ths | mask |= 1 << CP0Ca_DC;
|
1911 | 39d51eb8 | ths | |
1912 | e58c8ba5 | ths | env->CP0_Cause = (env->CP0_Cause & ~mask) | (T0 & mask); |
1913 | 8c0fdd85 | ths | |
1914 | 4de9b249 | ths | /* Handle the software interrupt as an hardware one, as they
|
1915 | 4de9b249 | ths | are very similar */
|
1916 | 4de9b249 | ths | if (T0 & CP0Ca_IP_mask) {
|
1917 | 4de9b249 | ths | CALL_FROM_TB1(cpu_mips_update_irq, env); |
1918 | 8c0fdd85 | ths | } |
1919 | 8c0fdd85 | ths | RETURN(); |
1920 | 8c0fdd85 | ths | } |
1921 | 8c0fdd85 | ths | |
1922 | 8c0fdd85 | ths | void op_mtc0_epc (void) |
1923 | 8c0fdd85 | ths | { |
1924 | f1b0aa5d | ths | env->CP0_EPC = T0; |
1925 | 8c0fdd85 | ths | RETURN(); |
1926 | 8c0fdd85 | ths | } |
1927 | 8c0fdd85 | ths | |
1928 | 7a387fff | ths | void op_mtc0_ebase (void) |
1929 | 7a387fff | ths | { |
1930 | 7a387fff | ths | /* vectored interrupts not implemented */
|
1931 | 7a387fff | ths | /* Multi-CPU not implemented */
|
1932 | b29a0341 | ths | env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000); |
1933 | 7a387fff | ths | RETURN(); |
1934 | 7a387fff | ths | } |
1935 | 7a387fff | ths | |
1936 | 8c0fdd85 | ths | void op_mtc0_config0 (void) |
1937 | 8c0fdd85 | ths | { |
1938 | 7bfd934a | ths | env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (T0 & 0x00000007); |
1939 | 8c0fdd85 | ths | RETURN(); |
1940 | 8c0fdd85 | ths | } |
1941 | 8c0fdd85 | ths | |
1942 | 7a387fff | ths | void op_mtc0_config2 (void) |
1943 | 7a387fff | ths | { |
1944 | 7a387fff | ths | /* tertiary/secondary caches not implemented */
|
1945 | 7a387fff | ths | env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
|
1946 | 7a387fff | ths | RETURN(); |
1947 | 7a387fff | ths | } |
1948 | 7a387fff | ths | |
1949 | fd88b6ab | ths | void op_mtc0_watchlo (void) |
1950 | 8c0fdd85 | ths | { |
1951 | 4e7a4a4e | ths | /* Watch exceptions for instructions, data loads, data stores
|
1952 | 4e7a4a4e | ths | not implemented. */
|
1953 | fd88b6ab | ths | env->CP0_WatchLo[PARAM1] = (T0 & ~0x7);
|
1954 | 8c0fdd85 | ths | RETURN(); |
1955 | 8c0fdd85 | ths | } |
1956 | 8c0fdd85 | ths | |
1957 | fd88b6ab | ths | void op_mtc0_watchhi (void) |
1958 | 8c0fdd85 | ths | { |
1959 | fd88b6ab | ths | env->CP0_WatchHi[PARAM1] = (T0 & 0x40FF0FF8);
|
1960 | fd88b6ab | ths | env->CP0_WatchHi[PARAM1] &= ~(env->CP0_WatchHi[PARAM1] & T0 & 0x7);
|
1961 | 8c0fdd85 | ths | RETURN(); |
1962 | 8c0fdd85 | ths | } |
1963 | 8c0fdd85 | ths | |
1964 | ead9360e | ths | void op_mtc0_xcontext (void) |
1965 | ead9360e | ths | { |
1966 | ead9360e | ths | target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1; |
1967 | ead9360e | ths | env->CP0_XContext = (env->CP0_XContext & mask) | (T0 & ~mask); |
1968 | ead9360e | ths | RETURN(); |
1969 | ead9360e | ths | } |
1970 | ead9360e | ths | |
1971 | 7a387fff | ths | void op_mtc0_framemask (void) |
1972 | 7a387fff | ths | { |
1973 | 7a387fff | ths | env->CP0_Framemask = T0; /* XXX */
|
1974 | 7a387fff | ths | RETURN(); |
1975 | 7a387fff | ths | } |
1976 | 7a387fff | ths | |
1977 | 8c0fdd85 | ths | void op_mtc0_debug (void) |
1978 | 8c0fdd85 | ths | { |
1979 | 8c0fdd85 | ths | env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120); |
1980 | 8c0fdd85 | ths | if (T0 & (1 << CP0DB_DM)) |
1981 | 8c0fdd85 | ths | env->hflags |= MIPS_HFLAG_DM; |
1982 | 8c0fdd85 | ths | else
|
1983 | 8c0fdd85 | ths | env->hflags &= ~MIPS_HFLAG_DM; |
1984 | 8c0fdd85 | ths | RETURN(); |
1985 | 8c0fdd85 | ths | } |
1986 | 8c0fdd85 | ths | |
1987 | ead9360e | ths | void op_mttc0_debug(void) |
1988 | ead9360e | ths | { |
1989 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1990 | ead9360e | ths | |
1991 | ead9360e | ths | /* XXX: Might be wrong, check with EJTAG spec. */
|
1992 | ead9360e | ths | env->CP0_Debug_tcstatus[other_tc] = T0 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)); |
1993 | ead9360e | ths | env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | |
1994 | ead9360e | ths | (T0 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); |
1995 | ead9360e | ths | RETURN(); |
1996 | ead9360e | ths | } |
1997 | ead9360e | ths | |
1998 | 8c0fdd85 | ths | void op_mtc0_depc (void) |
1999 | 8c0fdd85 | ths | { |
2000 | f1b0aa5d | ths | env->CP0_DEPC = T0; |
2001 | 8c0fdd85 | ths | RETURN(); |
2002 | 8c0fdd85 | ths | } |
2003 | 8c0fdd85 | ths | |
2004 | 7a387fff | ths | void op_mtc0_performance0 (void) |
2005 | 7a387fff | ths | { |
2006 | 7a387fff | ths | env->CP0_Performance0 = T0; /* XXX */
|
2007 | 7a387fff | ths | RETURN(); |
2008 | 7a387fff | ths | } |
2009 | 7a387fff | ths | |
2010 | 8c0fdd85 | ths | void op_mtc0_taglo (void) |
2011 | 8c0fdd85 | ths | { |
2012 | 9c2149c8 | ths | env->CP0_TagLo = T0 & 0xFFFFFCF6;
|
2013 | 8c0fdd85 | ths | RETURN(); |
2014 | 8c0fdd85 | ths | } |
2015 | 8c0fdd85 | ths | |
2016 | 7a387fff | ths | void op_mtc0_datalo (void) |
2017 | 7a387fff | ths | { |
2018 | 7a387fff | ths | env->CP0_DataLo = T0; /* XXX */
|
2019 | 7a387fff | ths | RETURN(); |
2020 | 7a387fff | ths | } |
2021 | 7a387fff | ths | |
2022 | 7a387fff | ths | void op_mtc0_taghi (void) |
2023 | 7a387fff | ths | { |
2024 | 7a387fff | ths | env->CP0_TagHi = T0; /* XXX */
|
2025 | 7a387fff | ths | RETURN(); |
2026 | 7a387fff | ths | } |
2027 | 7a387fff | ths | |
2028 | 7a387fff | ths | void op_mtc0_datahi (void) |
2029 | 7a387fff | ths | { |
2030 | 7a387fff | ths | env->CP0_DataHi = T0; /* XXX */
|
2031 | 7a387fff | ths | RETURN(); |
2032 | 7a387fff | ths | } |
2033 | 7a387fff | ths | |
2034 | 8c0fdd85 | ths | void op_mtc0_errorepc (void) |
2035 | 8c0fdd85 | ths | { |
2036 | f1b0aa5d | ths | env->CP0_ErrorEPC = T0; |
2037 | 8c0fdd85 | ths | RETURN(); |
2038 | 8c0fdd85 | ths | } |
2039 | 8c0fdd85 | ths | |
2040 | 8c0fdd85 | ths | void op_mtc0_desave (void) |
2041 | 8c0fdd85 | ths | { |
2042 | 8c0fdd85 | ths | env->CP0_DESAVE = T0; |
2043 | 6af0bf9c | bellard | RETURN(); |
2044 | 6af0bf9c | bellard | } |
2045 | 6af0bf9c | bellard | |
2046 | 534ce69f | ths | #ifdef TARGET_MIPS64
|
2047 | ead9360e | ths | void op_dmfc0_yqmask (void) |
2048 | f1b0aa5d | ths | { |
2049 | ead9360e | ths | T0 = env->CP0_YQMask; |
2050 | ead9360e | ths | RETURN(); |
2051 | ead9360e | ths | } |
2052 | ead9360e | ths | |
2053 | ead9360e | ths | void op_dmfc0_vpeschedule (void) |
2054 | ead9360e | ths | { |
2055 | ead9360e | ths | T0 = env->CP0_VPESchedule; |
2056 | ead9360e | ths | RETURN(); |
2057 | ead9360e | ths | } |
2058 | ead9360e | ths | |
2059 | ead9360e | ths | void op_dmfc0_vpeschefback (void) |
2060 | ead9360e | ths | { |
2061 | ead9360e | ths | T0 = env->CP0_VPEScheFBack; |
2062 | f1b0aa5d | ths | RETURN(); |
2063 | f1b0aa5d | ths | } |
2064 | f1b0aa5d | ths | |
2065 | 9c2149c8 | ths | void op_dmfc0_entrylo0 (void) |
2066 | 9c2149c8 | ths | { |
2067 | 9c2149c8 | ths | T0 = env->CP0_EntryLo0; |
2068 | 9c2149c8 | ths | RETURN(); |
2069 | 9c2149c8 | ths | } |
2070 | 9c2149c8 | ths | |
2071 | ead9360e | ths | void op_dmfc0_tcrestart (void) |
2072 | ead9360e | ths | { |
2073 | ead9360e | ths | T0 = env->PC[env->current_tc]; |
2074 | ead9360e | ths | RETURN(); |
2075 | ead9360e | ths | } |
2076 | ead9360e | ths | |
2077 | ead9360e | ths | void op_dmfc0_tchalt (void) |
2078 | ead9360e | ths | { |
2079 | ead9360e | ths | T0 = env->CP0_TCHalt[env->current_tc]; |
2080 | ead9360e | ths | RETURN(); |
2081 | ead9360e | ths | } |
2082 | ead9360e | ths | |
2083 | ead9360e | ths | void op_dmfc0_tccontext (void) |
2084 | ead9360e | ths | { |
2085 | ead9360e | ths | T0 = env->CP0_TCContext[env->current_tc]; |
2086 | ead9360e | ths | RETURN(); |
2087 | ead9360e | ths | } |
2088 | ead9360e | ths | |
2089 | ead9360e | ths | void op_dmfc0_tcschedule (void) |
2090 | ead9360e | ths | { |
2091 | ead9360e | ths | T0 = env->CP0_TCSchedule[env->current_tc]; |
2092 | ead9360e | ths | RETURN(); |
2093 | ead9360e | ths | } |
2094 | ead9360e | ths | |
2095 | ead9360e | ths | void op_dmfc0_tcschefback (void) |
2096 | ead9360e | ths | { |
2097 | ead9360e | ths | T0 = env->CP0_TCScheFBack[env->current_tc]; |
2098 | ead9360e | ths | RETURN(); |
2099 | ead9360e | ths | } |
2100 | ead9360e | ths | |
2101 | 9c2149c8 | ths | void op_dmfc0_entrylo1 (void) |
2102 | 9c2149c8 | ths | { |
2103 | 9c2149c8 | ths | T0 = env->CP0_EntryLo1; |
2104 | 9c2149c8 | ths | RETURN(); |
2105 | 9c2149c8 | ths | } |
2106 | 9c2149c8 | ths | |
2107 | 9c2149c8 | ths | void op_dmfc0_context (void) |
2108 | 9c2149c8 | ths | { |
2109 | 9c2149c8 | ths | T0 = env->CP0_Context; |
2110 | 9c2149c8 | ths | RETURN(); |
2111 | 9c2149c8 | ths | } |
2112 | 9c2149c8 | ths | |
2113 | 9c2149c8 | ths | void op_dmfc0_badvaddr (void) |
2114 | 9c2149c8 | ths | { |
2115 | 9c2149c8 | ths | T0 = env->CP0_BadVAddr; |
2116 | 9c2149c8 | ths | RETURN(); |
2117 | 9c2149c8 | ths | } |
2118 | 9c2149c8 | ths | |
2119 | 9c2149c8 | ths | void op_dmfc0_entryhi (void) |
2120 | 9c2149c8 | ths | { |
2121 | 9c2149c8 | ths | T0 = env->CP0_EntryHi; |
2122 | 9c2149c8 | ths | RETURN(); |
2123 | 9c2149c8 | ths | } |
2124 | 9c2149c8 | ths | |
2125 | 9c2149c8 | ths | void op_dmfc0_epc (void) |
2126 | 9c2149c8 | ths | { |
2127 | 9c2149c8 | ths | T0 = env->CP0_EPC; |
2128 | 9c2149c8 | ths | RETURN(); |
2129 | 9c2149c8 | ths | } |
2130 | 9c2149c8 | ths | |
2131 | 9c2149c8 | ths | void op_dmfc0_lladdr (void) |
2132 | 9c2149c8 | ths | { |
2133 | 9c2149c8 | ths | T0 = env->CP0_LLAddr >> 4;
|
2134 | 9c2149c8 | ths | RETURN(); |
2135 | 9c2149c8 | ths | } |
2136 | 9c2149c8 | ths | |
2137 | fd88b6ab | ths | void op_dmfc0_watchlo (void) |
2138 | 9c2149c8 | ths | { |
2139 | fd88b6ab | ths | T0 = env->CP0_WatchLo[PARAM1]; |
2140 | 9c2149c8 | ths | RETURN(); |
2141 | 9c2149c8 | ths | } |
2142 | 9c2149c8 | ths | |
2143 | 9c2149c8 | ths | void op_dmfc0_xcontext (void) |
2144 | 9c2149c8 | ths | { |
2145 | 9c2149c8 | ths | T0 = env->CP0_XContext; |
2146 | 9c2149c8 | ths | RETURN(); |
2147 | 9c2149c8 | ths | } |
2148 | 9c2149c8 | ths | |
2149 | 9c2149c8 | ths | void op_dmfc0_depc (void) |
2150 | 9c2149c8 | ths | { |
2151 | 9c2149c8 | ths | T0 = env->CP0_DEPC; |
2152 | 9c2149c8 | ths | RETURN(); |
2153 | 9c2149c8 | ths | } |
2154 | 9c2149c8 | ths | |
2155 | 9c2149c8 | ths | void op_dmfc0_errorepc (void) |
2156 | 9c2149c8 | ths | { |
2157 | 9c2149c8 | ths | T0 = env->CP0_ErrorEPC; |
2158 | 9c2149c8 | ths | RETURN(); |
2159 | 9c2149c8 | ths | } |
2160 | 534ce69f | ths | #endif /* TARGET_MIPS64 */ |
2161 | 9c2149c8 | ths | |
2162 | ead9360e | ths | /* MIPS MT functions */
|
2163 | ead9360e | ths | void op_mftgpr(void) |
2164 | ead9360e | ths | { |
2165 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
2166 | ead9360e | ths | |
2167 | ead9360e | ths | T0 = env->gpr[PARAM1][other_tc]; |
2168 | ead9360e | ths | RETURN(); |
2169 | ead9360e | ths | } |
2170 | ead9360e | ths | |
2171 | ead9360e | ths | void op_mftlo(void) |
2172 | ead9360e | ths | { |
2173 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
2174 | ead9360e | ths | |
2175 | ead9360e | ths | T0 = env->LO[PARAM1][other_tc]; |
2176 | ead9360e | ths | RETURN(); |
2177 | ead9360e | ths | } |
2178 | ead9360e | ths | |
2179 | ead9360e | ths | void op_mfthi(void) |
2180 | ead9360e | ths | { |
2181 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
2182 | ead9360e | ths | |
2183 | ead9360e | ths | T0 = env->HI[PARAM1][other_tc]; |
2184 | ead9360e | ths | RETURN(); |
2185 | ead9360e | ths | } |
2186 | ead9360e | ths | |
2187 | ead9360e | ths | void op_mftacx(void) |
2188 | ead9360e | ths | { |
2189 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
2190 | ead9360e | ths | |
2191 | ead9360e | ths | T0 = env->ACX[PARAM1][other_tc]; |
2192 | ead9360e | ths | RETURN(); |
2193 | ead9360e | ths | } |
2194 | ead9360e | ths | |
2195 | ead9360e | ths | void op_mftdsp(void) |
2196 | ead9360e | ths | { |
2197 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
2198 | ead9360e | ths | |
2199 | ead9360e | ths | T0 = env->DSPControl[other_tc]; |
2200 | ead9360e | ths | RETURN(); |
2201 | ead9360e | ths | } |
2202 | ead9360e | ths | |
2203 | ead9360e | ths | void op_mttgpr(void) |
2204 | ead9360e | ths | { |
2205 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
2206 | ead9360e | ths | |
2207 | ead9360e | ths | T0 = env->gpr[PARAM1][other_tc]; |
2208 | ead9360e | ths | RETURN(); |
2209 | ead9360e | ths | } |
2210 | ead9360e | ths | |
2211 | ead9360e | ths | void op_mttlo(void) |
2212 | ead9360e | ths | { |
2213 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
2214 | ead9360e | ths | |
2215 | ead9360e | ths | T0 = env->LO[PARAM1][other_tc]; |
2216 | ead9360e | ths | RETURN(); |
2217 | ead9360e | ths | } |
2218 | ead9360e | ths | |
2219 | ead9360e | ths | void op_mtthi(void) |
2220 | ead9360e | ths | { |
2221 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
2222 | ead9360e | ths | |
2223 | ead9360e | ths | T0 = env->HI[PARAM1][other_tc]; |
2224 | ead9360e | ths | RETURN(); |
2225 | ead9360e | ths | } |
2226 | ead9360e | ths | |
2227 | ead9360e | ths | void op_mttacx(void) |
2228 | ead9360e | ths | { |
2229 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
2230 | ead9360e | ths | |
2231 | ead9360e | ths | T0 = env->ACX[PARAM1][other_tc]; |
2232 | ead9360e | ths | RETURN(); |
2233 | ead9360e | ths | } |
2234 | ead9360e | ths | |
2235 | ead9360e | ths | void op_mttdsp(void) |
2236 | ead9360e | ths | { |
2237 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
2238 | ead9360e | ths | |
2239 | ead9360e | ths | T0 = env->DSPControl[other_tc]; |
2240 | ead9360e | ths | RETURN(); |
2241 | ead9360e | ths | } |
2242 | ead9360e | ths | |
2243 | ead9360e | ths | |
2244 | ead9360e | ths | void op_dmt(void) |
2245 | ead9360e | ths | { |
2246 | ead9360e | ths | // TODO
|
2247 | ead9360e | ths | T0 = 0;
|
2248 | ead9360e | ths | // rt = T0
|
2249 | ead9360e | ths | RETURN(); |
2250 | ead9360e | ths | } |
2251 | ead9360e | ths | |
2252 | ead9360e | ths | void op_emt(void) |
2253 | ead9360e | ths | { |
2254 | ead9360e | ths | // TODO
|
2255 | ead9360e | ths | T0 = 0;
|
2256 | ead9360e | ths | // rt = T0
|
2257 | ead9360e | ths | RETURN(); |
2258 | ead9360e | ths | } |
2259 | ead9360e | ths | |
2260 | ead9360e | ths | void op_dvpe(void) |
2261 | ead9360e | ths | { |
2262 | ead9360e | ths | // TODO
|
2263 | ead9360e | ths | T0 = 0;
|
2264 | ead9360e | ths | // rt = T0
|
2265 | ead9360e | ths | RETURN(); |
2266 | ead9360e | ths | } |
2267 | ead9360e | ths | |
2268 | ead9360e | ths | void op_evpe(void) |
2269 | ead9360e | ths | { |
2270 | ead9360e | ths | // TODO
|
2271 | ead9360e | ths | T0 = 0;
|
2272 | ead9360e | ths | // rt = T0
|
2273 | ead9360e | ths | RETURN(); |
2274 | ead9360e | ths | } |
2275 | ead9360e | ths | |
2276 | ead9360e | ths | void op_fork(void) |
2277 | ead9360e | ths | { |
2278 | ead9360e | ths | // T0 = rt, T1 = rs
|
2279 | ead9360e | ths | T0 = 0;
|
2280 | ead9360e | ths | // TODO: store to TC register
|
2281 | ead9360e | ths | RETURN(); |
2282 | ead9360e | ths | } |
2283 | ead9360e | ths | |
2284 | ead9360e | ths | void op_yield(void) |
2285 | ead9360e | ths | { |
2286 | ead9360e | ths | if (T0 < 0) { |
2287 | ead9360e | ths | /* No scheduling policy implemented. */
|
2288 | ead9360e | ths | if (T0 != -2) { |
2289 | ead9360e | ths | if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) && |
2290 | ead9360e | ths | env->CP0_TCStatus[env->current_tc] & (1 << CP0TCSt_DT)) {
|
2291 | ead9360e | ths | env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
|
2292 | ead9360e | ths | env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
|
2293 | ead9360e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_THREAD); |
2294 | ead9360e | ths | } |
2295 | ead9360e | ths | } |
2296 | ead9360e | ths | } else if (T0 == 0) { |
2297 | ead9360e | ths | if (0 /* TODO: TC underflow */) { |
2298 | ead9360e | ths | env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
|
2299 | ead9360e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_THREAD); |
2300 | ead9360e | ths | } else {
|
2301 | ead9360e | ths | // TODO: Deallocate TC
|
2302 | ead9360e | ths | } |
2303 | ead9360e | ths | } else if (T0 > 0) { |
2304 | ead9360e | ths | /* Yield qualifier inputs not implemented. */
|
2305 | ead9360e | ths | env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
|
2306 | ead9360e | ths | env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
|
2307 | ead9360e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_THREAD); |
2308 | ead9360e | ths | } |
2309 | ead9360e | ths | T0 = env->CP0_YQMask; |
2310 | ead9360e | ths | RETURN(); |
2311 | ead9360e | ths | } |
2312 | ead9360e | ths | |
2313 | 5a5012ec | ths | /* CP1 functions */
|
2314 | 6ea83fed | bellard | #if 0
|
2315 | 6ea83fed | bellard | # define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env)
|
2316 | 6ea83fed | bellard | #else
|
2317 | 6ea83fed | bellard | # define DEBUG_FPU_STATE() do { } while(0) |
2318 | 6ea83fed | bellard | #endif
|
2319 | 6ea83fed | bellard | |
2320 | 24c7b0e3 | ths | void op_cp0_enabled(void) |
2321 | 24c7b0e3 | ths | { |
2322 | 24c7b0e3 | ths | if (!(env->CP0_Status & (1 << CP0St_CU0)) && |
2323 | 996ba2cc | ths | (env->hflags & MIPS_HFLAG_UM)) { |
2324 | 1579a72e | ths | CALL_FROM_TB2(do_raise_exception_err, EXCP_CpU, 0);
|
2325 | 24c7b0e3 | ths | } |
2326 | 24c7b0e3 | ths | RETURN(); |
2327 | 24c7b0e3 | ths | } |
2328 | 24c7b0e3 | ths | |
2329 | 5a5012ec | ths | void op_cfc1 (void) |
2330 | 5a5012ec | ths | { |
2331 | ead9360e | ths | CALL_FROM_TB1(do_cfc1, PARAM1); |
2332 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2333 | 5a5012ec | ths | RETURN(); |
2334 | 5a5012ec | ths | } |
2335 | 5a5012ec | ths | |
2336 | 5a5012ec | ths | void op_ctc1 (void) |
2337 | 5a5012ec | ths | { |
2338 | ead9360e | ths | CALL_FROM_TB1(do_ctc1, PARAM1); |
2339 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
2340 | 6ea83fed | bellard | RETURN(); |
2341 | 6ea83fed | bellard | } |
2342 | 6ea83fed | bellard | |
2343 | 6ea83fed | bellard | void op_mfc1 (void) |
2344 | 6ea83fed | bellard | { |
2345 | 6ea83fed | bellard | T0 = WT0; |
2346 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
2347 | 6ea83fed | bellard | RETURN(); |
2348 | 6ea83fed | bellard | } |
2349 | 6ea83fed | bellard | |
2350 | 6ea83fed | bellard | void op_mtc1 (void) |
2351 | 6ea83fed | bellard | { |
2352 | 6ea83fed | bellard | WT0 = T0; |
2353 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
2354 | 6ea83fed | bellard | RETURN(); |
2355 | 6ea83fed | bellard | } |
2356 | 6ea83fed | bellard | |
2357 | 5a5012ec | ths | void op_dmfc1 (void) |
2358 | 5a5012ec | ths | { |
2359 | 5a5012ec | ths | T0 = DT0; |
2360 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2361 | 5a5012ec | ths | RETURN(); |
2362 | 5a5012ec | ths | } |
2363 | 5a5012ec | ths | |
2364 | 5a5012ec | ths | void op_dmtc1 (void) |
2365 | 5a5012ec | ths | { |
2366 | 5a5012ec | ths | DT0 = T0; |
2367 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2368 | 5a5012ec | ths | RETURN(); |
2369 | 5a5012ec | ths | } |
2370 | 5a5012ec | ths | |
2371 | 5a5012ec | ths | void op_mfhc1 (void) |
2372 | 5a5012ec | ths | { |
2373 | 5a5012ec | ths | T0 = WTH0; |
2374 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2375 | 5a5012ec | ths | RETURN(); |
2376 | 5a5012ec | ths | } |
2377 | 5a5012ec | ths | |
2378 | 5a5012ec | ths | void op_mthc1 (void) |
2379 | 5a5012ec | ths | { |
2380 | 5a5012ec | ths | WTH0 = T0; |
2381 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2382 | 5a5012ec | ths | RETURN(); |
2383 | 5a5012ec | ths | } |
2384 | 5a5012ec | ths | |
2385 | 6ea83fed | bellard | /* Float support.
|
2386 | 6ea83fed | bellard | Single precition routines have a "s" suffix, double precision a
|
2387 | 5a5012ec | ths | "d" suffix, 32bit integer "w", 64bit integer "l", paired singe "ps",
|
2388 | 5a5012ec | ths | paired single lowwer "pl", paired single upper "pu". */
|
2389 | 6ea83fed | bellard | |
2390 | 6ea83fed | bellard | #define FLOAT_OP(name, p) void OPPROTO op_float_##name##_##p(void) |
2391 | 6ea83fed | bellard | |
2392 | dd016883 | bellard | FLOAT_OP(cvtd, s) |
2393 | dd016883 | bellard | { |
2394 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvtd_s); |
2395 | dd016883 | bellard | DEBUG_FPU_STATE(); |
2396 | dd016883 | bellard | RETURN(); |
2397 | dd016883 | bellard | } |
2398 | 6ea83fed | bellard | FLOAT_OP(cvtd, w) |
2399 | 6ea83fed | bellard | { |
2400 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvtd_w); |
2401 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2402 | 5a5012ec | ths | RETURN(); |
2403 | 5a5012ec | ths | } |
2404 | 5a5012ec | ths | FLOAT_OP(cvtd, l) |
2405 | 5a5012ec | ths | { |
2406 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvtd_l); |
2407 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2408 | 5a5012ec | ths | RETURN(); |
2409 | 5a5012ec | ths | } |
2410 | 5a5012ec | ths | FLOAT_OP(cvtl, d) |
2411 | 5a5012ec | ths | { |
2412 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvtl_d); |
2413 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2414 | 5a5012ec | ths | RETURN(); |
2415 | 5a5012ec | ths | } |
2416 | 5a5012ec | ths | FLOAT_OP(cvtl, s) |
2417 | 5a5012ec | ths | { |
2418 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvtl_s); |
2419 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2420 | 5a5012ec | ths | RETURN(); |
2421 | 5a5012ec | ths | } |
2422 | 5a5012ec | ths | FLOAT_OP(cvtps, s) |
2423 | 5a5012ec | ths | { |
2424 | 5a5012ec | ths | WT2 = WT0; |
2425 | 5a5012ec | ths | WTH2 = WT1; |
2426 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2427 | 5a5012ec | ths | RETURN(); |
2428 | 5a5012ec | ths | } |
2429 | 5a5012ec | ths | FLOAT_OP(cvtps, pw) |
2430 | 5a5012ec | ths | { |
2431 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvtps_pw); |
2432 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2433 | 5a5012ec | ths | RETURN(); |
2434 | 5a5012ec | ths | } |
2435 | 5a5012ec | ths | FLOAT_OP(cvtpw, ps) |
2436 | 5a5012ec | ths | { |
2437 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvtpw_ps); |
2438 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
2439 | 6ea83fed | bellard | RETURN(); |
2440 | 6ea83fed | bellard | } |
2441 | dd016883 | bellard | FLOAT_OP(cvts, d) |
2442 | dd016883 | bellard | { |
2443 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvts_d); |
2444 | dd016883 | bellard | DEBUG_FPU_STATE(); |
2445 | dd016883 | bellard | RETURN(); |
2446 | dd016883 | bellard | } |
2447 | 6ea83fed | bellard | FLOAT_OP(cvts, w) |
2448 | 6ea83fed | bellard | { |
2449 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvts_w); |
2450 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2451 | 5a5012ec | ths | RETURN(); |
2452 | 5a5012ec | ths | } |
2453 | 5a5012ec | ths | FLOAT_OP(cvts, l) |
2454 | 5a5012ec | ths | { |
2455 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvts_l); |
2456 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2457 | 5a5012ec | ths | RETURN(); |
2458 | 5a5012ec | ths | } |
2459 | 5a5012ec | ths | FLOAT_OP(cvts, pl) |
2460 | 5a5012ec | ths | { |
2461 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvts_pl); |
2462 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2463 | 5a5012ec | ths | RETURN(); |
2464 | 5a5012ec | ths | } |
2465 | 5a5012ec | ths | FLOAT_OP(cvts, pu) |
2466 | 5a5012ec | ths | { |
2467 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvts_pu); |
2468 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
2469 | 6ea83fed | bellard | RETURN(); |
2470 | 6ea83fed | bellard | } |
2471 | 6ea83fed | bellard | FLOAT_OP(cvtw, s) |
2472 | 6ea83fed | bellard | { |
2473 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvtw_s); |
2474 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
2475 | 6ea83fed | bellard | RETURN(); |
2476 | 6ea83fed | bellard | } |
2477 | 6ea83fed | bellard | FLOAT_OP(cvtw, d) |
2478 | 6ea83fed | bellard | { |
2479 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvtw_d); |
2480 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2481 | 5a5012ec | ths | RETURN(); |
2482 | 5a5012ec | ths | } |
2483 | 5a5012ec | ths | |
2484 | 5a5012ec | ths | FLOAT_OP(pll, ps) |
2485 | 5a5012ec | ths | { |
2486 | 5a5012ec | ths | DT2 = ((uint64_t)WT0 << 32) | WT1;
|
2487 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2488 | 5a5012ec | ths | RETURN(); |
2489 | 5a5012ec | ths | } |
2490 | 5a5012ec | ths | FLOAT_OP(plu, ps) |
2491 | 5a5012ec | ths | { |
2492 | 5a5012ec | ths | DT2 = ((uint64_t)WT0 << 32) | WTH1;
|
2493 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2494 | 5a5012ec | ths | RETURN(); |
2495 | 5a5012ec | ths | } |
2496 | 5a5012ec | ths | FLOAT_OP(pul, ps) |
2497 | 5a5012ec | ths | { |
2498 | 5a5012ec | ths | DT2 = ((uint64_t)WTH0 << 32) | WT1;
|
2499 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2500 | 5a5012ec | ths | RETURN(); |
2501 | 5a5012ec | ths | } |
2502 | 5a5012ec | ths | FLOAT_OP(puu, ps) |
2503 | 5a5012ec | ths | { |
2504 | 5a5012ec | ths | DT2 = ((uint64_t)WTH0 << 32) | WTH1;
|
2505 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
2506 | 6ea83fed | bellard | RETURN(); |
2507 | 6ea83fed | bellard | } |
2508 | 6ea83fed | bellard | |
2509 | fd4a04eb | ths | #define FLOAT_ROUNDOP(op, ttype, stype) \
|
2510 | fd4a04eb | ths | FLOAT_OP(op ## ttype, stype) \ |
2511 | fd4a04eb | ths | { \ |
2512 | fd4a04eb | ths | CALL_FROM_TB0(do_float_ ## op ## ttype ## _ ## stype); \ |
2513 | fd4a04eb | ths | DEBUG_FPU_STATE(); \ |
2514 | fd4a04eb | ths | RETURN(); \ |
2515 | 6ea83fed | bellard | } |
2516 | 6ea83fed | bellard | |
2517 | fd4a04eb | ths | FLOAT_ROUNDOP(round, l, d) |
2518 | fd4a04eb | ths | FLOAT_ROUNDOP(round, l, s) |
2519 | fd4a04eb | ths | FLOAT_ROUNDOP(round, w, d) |
2520 | fd4a04eb | ths | FLOAT_ROUNDOP(round, w, s) |
2521 | 6ea83fed | bellard | |
2522 | fd4a04eb | ths | FLOAT_ROUNDOP(trunc, l, d) |
2523 | fd4a04eb | ths | FLOAT_ROUNDOP(trunc, l, s) |
2524 | fd4a04eb | ths | FLOAT_ROUNDOP(trunc, w, d) |
2525 | fd4a04eb | ths | FLOAT_ROUNDOP(trunc, w, s) |
2526 | 6ea83fed | bellard | |
2527 | fd4a04eb | ths | FLOAT_ROUNDOP(ceil, l, d) |
2528 | fd4a04eb | ths | FLOAT_ROUNDOP(ceil, l, s) |
2529 | fd4a04eb | ths | FLOAT_ROUNDOP(ceil, w, d) |
2530 | fd4a04eb | ths | FLOAT_ROUNDOP(ceil, w, s) |
2531 | fd4a04eb | ths | |
2532 | fd4a04eb | ths | FLOAT_ROUNDOP(floor, l, d) |
2533 | fd4a04eb | ths | FLOAT_ROUNDOP(floor, l, s) |
2534 | fd4a04eb | ths | FLOAT_ROUNDOP(floor, w, d) |
2535 | fd4a04eb | ths | FLOAT_ROUNDOP(floor, w, s) |
2536 | fd4a04eb | ths | #undef FLOAR_ROUNDOP
|
2537 | 6ea83fed | bellard | |
2538 | 5a5012ec | ths | FLOAT_OP(movf, d) |
2539 | 5a5012ec | ths | { |
2540 | ead9360e | ths | if (!(env->fpu->fcr31 & PARAM1))
|
2541 | 5a5012ec | ths | DT2 = DT0; |
2542 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2543 | 5a5012ec | ths | RETURN(); |
2544 | 5a5012ec | ths | } |
2545 | 5a5012ec | ths | FLOAT_OP(movf, s) |
2546 | 5a5012ec | ths | { |
2547 | ead9360e | ths | if (!(env->fpu->fcr31 & PARAM1))
|
2548 | 5a5012ec | ths | WT2 = WT0; |
2549 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2550 | 5a5012ec | ths | RETURN(); |
2551 | 5a5012ec | ths | } |
2552 | 5a5012ec | ths | FLOAT_OP(movf, ps) |
2553 | 5a5012ec | ths | { |
2554 | ead9360e | ths | if (!(env->fpu->fcr31 & PARAM1)) {
|
2555 | 5a5012ec | ths | WT2 = WT0; |
2556 | 5a5012ec | ths | WTH2 = WTH0; |
2557 | 5a5012ec | ths | } |
2558 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2559 | 5a5012ec | ths | RETURN(); |
2560 | 5a5012ec | ths | } |
2561 | 5a5012ec | ths | FLOAT_OP(movt, d) |
2562 | 5a5012ec | ths | { |
2563 | ead9360e | ths | if (env->fpu->fcr31 & PARAM1)
|
2564 | 5a5012ec | ths | DT2 = DT0; |
2565 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2566 | 5a5012ec | ths | RETURN(); |
2567 | 5a5012ec | ths | } |
2568 | 5a5012ec | ths | FLOAT_OP(movt, s) |
2569 | 5a5012ec | ths | { |
2570 | ead9360e | ths | if (env->fpu->fcr31 & PARAM1)
|
2571 | 5a5012ec | ths | WT2 = WT0; |
2572 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2573 | 5a5012ec | ths | RETURN(); |
2574 | 5a5012ec | ths | } |
2575 | 5a5012ec | ths | FLOAT_OP(movt, ps) |
2576 | 5a5012ec | ths | { |
2577 | ead9360e | ths | if (env->fpu->fcr31 & PARAM1) {
|
2578 | 5a5012ec | ths | WT2 = WT0; |
2579 | 5a5012ec | ths | WTH2 = WTH0; |
2580 | 5a5012ec | ths | } |
2581 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2582 | 5a5012ec | ths | RETURN(); |
2583 | 5a5012ec | ths | } |
2584 | 5a5012ec | ths | FLOAT_OP(movz, d) |
2585 | 5a5012ec | ths | { |
2586 | 5a5012ec | ths | if (!T0)
|
2587 | 5a5012ec | ths | DT2 = DT0; |
2588 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2589 | 5a5012ec | ths | RETURN(); |
2590 | 5a5012ec | ths | } |
2591 | 5a5012ec | ths | FLOAT_OP(movz, s) |
2592 | 5a5012ec | ths | { |
2593 | 5a5012ec | ths | if (!T0)
|
2594 | 5a5012ec | ths | WT2 = WT0; |
2595 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2596 | 5a5012ec | ths | RETURN(); |
2597 | 5a5012ec | ths | } |
2598 | 5a5012ec | ths | FLOAT_OP(movz, ps) |
2599 | 5a5012ec | ths | { |
2600 | 5a5012ec | ths | if (!T0) {
|
2601 | 5a5012ec | ths | WT2 = WT0; |
2602 | 5a5012ec | ths | WTH2 = WTH0; |
2603 | 5a5012ec | ths | } |
2604 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2605 | 5a5012ec | ths | RETURN(); |
2606 | 5a5012ec | ths | } |
2607 | 5a5012ec | ths | FLOAT_OP(movn, d) |
2608 | 5a5012ec | ths | { |
2609 | 5a5012ec | ths | if (T0)
|
2610 | 5a5012ec | ths | DT2 = DT0; |
2611 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2612 | 5a5012ec | ths | RETURN(); |
2613 | 5a5012ec | ths | } |
2614 | 5a5012ec | ths | FLOAT_OP(movn, s) |
2615 | 5a5012ec | ths | { |
2616 | 5a5012ec | ths | if (T0)
|
2617 | 5a5012ec | ths | WT2 = WT0; |
2618 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2619 | 5a5012ec | ths | RETURN(); |
2620 | 5a5012ec | ths | } |
2621 | 5a5012ec | ths | FLOAT_OP(movn, ps) |
2622 | 5a5012ec | ths | { |
2623 | 5a5012ec | ths | if (T0) {
|
2624 | 5a5012ec | ths | WT2 = WT0; |
2625 | 5a5012ec | ths | WTH2 = WTH0; |
2626 | 5a5012ec | ths | } |
2627 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2628 | 5a5012ec | ths | RETURN(); |
2629 | 5a5012ec | ths | } |
2630 | 5a5012ec | ths | |
2631 | 57fa1fb3 | ths | /* operations calling helpers, for s, d and ps */
|
2632 | 57fa1fb3 | ths | #define FLOAT_HOP(name) \
|
2633 | 6ea83fed | bellard | FLOAT_OP(name, d) \ |
2634 | 6ea83fed | bellard | { \ |
2635 | fd4a04eb | ths | CALL_FROM_TB0(do_float_ ## name ## _d); \ |
2636 | 6ea83fed | bellard | DEBUG_FPU_STATE(); \ |
2637 | fbcc6828 | ths | RETURN(); \ |
2638 | 6ea83fed | bellard | } \ |
2639 | 6ea83fed | bellard | FLOAT_OP(name, s) \ |
2640 | 6ea83fed | bellard | { \ |
2641 | fd4a04eb | ths | CALL_FROM_TB0(do_float_ ## name ## _s); \ |
2642 | 5a5012ec | ths | DEBUG_FPU_STATE(); \ |
2643 | fbcc6828 | ths | RETURN(); \ |
2644 | 5a5012ec | ths | } \ |
2645 | 5a5012ec | ths | FLOAT_OP(name, ps) \ |
2646 | 5a5012ec | ths | { \ |
2647 | fd4a04eb | ths | CALL_FROM_TB0(do_float_ ## name ## _ps); \ |
2648 | 6ea83fed | bellard | DEBUG_FPU_STATE(); \ |
2649 | fbcc6828 | ths | RETURN(); \ |
2650 | 6ea83fed | bellard | } |
2651 | 57fa1fb3 | ths | FLOAT_HOP(add) |
2652 | 57fa1fb3 | ths | FLOAT_HOP(sub) |
2653 | 57fa1fb3 | ths | FLOAT_HOP(mul) |
2654 | 57fa1fb3 | ths | FLOAT_HOP(div) |
2655 | 57fa1fb3 | ths | FLOAT_HOP(recip2) |
2656 | 57fa1fb3 | ths | FLOAT_HOP(rsqrt2) |
2657 | 57fa1fb3 | ths | FLOAT_HOP(rsqrt1) |
2658 | 57fa1fb3 | ths | FLOAT_HOP(recip1) |
2659 | 57fa1fb3 | ths | #undef FLOAT_HOP
|
2660 | 57fa1fb3 | ths | |
2661 | 57fa1fb3 | ths | /* operations calling helpers, for s and d */
|
2662 | 57fa1fb3 | ths | #define FLOAT_HOP(name) \
|
2663 | 57fa1fb3 | ths | FLOAT_OP(name, d) \ |
2664 | 57fa1fb3 | ths | { \ |
2665 | 57fa1fb3 | ths | CALL_FROM_TB0(do_float_ ## name ## _d); \ |
2666 | 57fa1fb3 | ths | DEBUG_FPU_STATE(); \ |
2667 | 57fa1fb3 | ths | RETURN(); \ |
2668 | 57fa1fb3 | ths | } \ |
2669 | 57fa1fb3 | ths | FLOAT_OP(name, s) \ |
2670 | 57fa1fb3 | ths | { \ |
2671 | 57fa1fb3 | ths | CALL_FROM_TB0(do_float_ ## name ## _s); \ |
2672 | 57fa1fb3 | ths | DEBUG_FPU_STATE(); \ |
2673 | 57fa1fb3 | ths | RETURN(); \ |
2674 | 57fa1fb3 | ths | } |
2675 | 57fa1fb3 | ths | FLOAT_HOP(rsqrt) |
2676 | 57fa1fb3 | ths | FLOAT_HOP(recip) |
2677 | 57fa1fb3 | ths | #undef FLOAT_HOP
|
2678 | 6ea83fed | bellard | |
2679 | 57fa1fb3 | ths | /* operations calling helpers, for ps */
|
2680 | 57fa1fb3 | ths | #define FLOAT_HOP(name) \
|
2681 | 57fa1fb3 | ths | FLOAT_OP(name, ps) \ |
2682 | 57fa1fb3 | ths | { \ |
2683 | 57fa1fb3 | ths | CALL_FROM_TB0(do_float_ ## name ## _ps); \ |
2684 | 57fa1fb3 | ths | DEBUG_FPU_STATE(); \ |
2685 | 57fa1fb3 | ths | RETURN(); \ |
2686 | fbcc6828 | ths | } |
2687 | 57fa1fb3 | ths | FLOAT_HOP(addr) |
2688 | 57fa1fb3 | ths | FLOAT_HOP(mulr) |
2689 | 57fa1fb3 | ths | #undef FLOAT_HOP
|
2690 | fbcc6828 | ths | |
2691 | 5a5012ec | ths | /* ternary operations */
|
2692 | 5a5012ec | ths | #define FLOAT_TERNOP(name1, name2) \
|
2693 | 5a5012ec | ths | FLOAT_OP(name1 ## name2, d) \ |
2694 | 5a5012ec | ths | { \ |
2695 | ead9360e | ths | FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fpu->fp_status); \ |
2696 | ead9360e | ths | FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fpu->fp_status); \ |
2697 | 5a5012ec | ths | DEBUG_FPU_STATE(); \ |
2698 | fbcc6828 | ths | RETURN(); \ |
2699 | 5a5012ec | ths | } \ |
2700 | 5a5012ec | ths | FLOAT_OP(name1 ## name2, s) \ |
2701 | 5a5012ec | ths | { \ |
2702 | ead9360e | ths | FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \ |
2703 | ead9360e | ths | FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \ |
2704 | 5a5012ec | ths | DEBUG_FPU_STATE(); \ |
2705 | fbcc6828 | ths | RETURN(); \ |
2706 | 5a5012ec | ths | } \ |
2707 | 5a5012ec | ths | FLOAT_OP(name1 ## name2, ps) \ |
2708 | 5a5012ec | ths | { \ |
2709 | ead9360e | ths | FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \ |
2710 | ead9360e | ths | FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fpu->fp_status); \ |
2711 | ead9360e | ths | FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \ |
2712 | ead9360e | ths | FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fpu->fp_status); \ |
2713 | 5a5012ec | ths | DEBUG_FPU_STATE(); \ |
2714 | fbcc6828 | ths | RETURN(); \ |
2715 | 5a5012ec | ths | } |
2716 | 5a5012ec | ths | FLOAT_TERNOP(mul, add) |
2717 | 5a5012ec | ths | FLOAT_TERNOP(mul, sub) |
2718 | 5a5012ec | ths | #undef FLOAT_TERNOP
|
2719 | 5a5012ec | ths | |
2720 | fbcc6828 | ths | /* negated ternary operations */
|
2721 | fbcc6828 | ths | #define FLOAT_NTERNOP(name1, name2) \
|
2722 | fbcc6828 | ths | FLOAT_OP(n ## name1 ## name2, d) \ |
2723 | fbcc6828 | ths | { \ |
2724 | ead9360e | ths | FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fpu->fp_status); \ |
2725 | ead9360e | ths | FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fpu->fp_status); \ |
2726 | fbcc6828 | ths | FDT2 ^= 1ULL << 63; \ |
2727 | fbcc6828 | ths | DEBUG_FPU_STATE(); \ |
2728 | fbcc6828 | ths | RETURN(); \ |
2729 | fbcc6828 | ths | } \ |
2730 | fbcc6828 | ths | FLOAT_OP(n ## name1 ## name2, s) \ |
2731 | fbcc6828 | ths | { \ |
2732 | ead9360e | ths | FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \ |
2733 | ead9360e | ths | FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \ |
2734 | fbcc6828 | ths | FST2 ^= 1 << 31; \ |
2735 | fbcc6828 | ths | DEBUG_FPU_STATE(); \ |
2736 | fbcc6828 | ths | RETURN(); \ |
2737 | fbcc6828 | ths | } \ |
2738 | fbcc6828 | ths | FLOAT_OP(n ## name1 ## name2, ps) \ |
2739 | fbcc6828 | ths | { \ |
2740 | ead9360e | ths | FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \ |
2741 | ead9360e | ths | FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fpu->fp_status); \ |
2742 | ead9360e | ths | FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \ |
2743 | ead9360e | ths | FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fpu->fp_status); \ |
2744 | fbcc6828 | ths | FST2 ^= 1 << 31; \ |
2745 | fbcc6828 | ths | FSTH2 ^= 1 << 31; \ |
2746 | fbcc6828 | ths | DEBUG_FPU_STATE(); \ |
2747 | fbcc6828 | ths | RETURN(); \ |
2748 | fbcc6828 | ths | } |
2749 | fbcc6828 | ths | FLOAT_NTERNOP(mul, add) |
2750 | fbcc6828 | ths | FLOAT_NTERNOP(mul, sub) |
2751 | fbcc6828 | ths | #undef FLOAT_NTERNOP
|
2752 | fbcc6828 | ths | |
2753 | 6ea83fed | bellard | /* unary operations, modifying fp status */
|
2754 | 6ea83fed | bellard | #define FLOAT_UNOP(name) \
|
2755 | 6ea83fed | bellard | FLOAT_OP(name, d) \ |
2756 | 6ea83fed | bellard | { \ |
2757 | ead9360e | ths | FDT2 = float64_ ## name(FDT0, &env->fpu->fp_status); \ |
2758 | 6ea83fed | bellard | DEBUG_FPU_STATE(); \ |
2759 | fbcc6828 | ths | RETURN(); \ |
2760 | 6ea83fed | bellard | } \ |
2761 | 6ea83fed | bellard | FLOAT_OP(name, s) \ |
2762 | 6ea83fed | bellard | { \ |
2763 | ead9360e | ths | FST2 = float32_ ## name(FST0, &env->fpu->fp_status); \ |
2764 | 6ea83fed | bellard | DEBUG_FPU_STATE(); \ |
2765 | 57fa1fb3 | ths | RETURN(); \ |
2766 | 6ea83fed | bellard | } |
2767 | 6ea83fed | bellard | FLOAT_UNOP(sqrt) |
2768 | 6ea83fed | bellard | #undef FLOAT_UNOP
|
2769 | 6ea83fed | bellard | |
2770 | 6ea83fed | bellard | /* unary operations, not modifying fp status */
|
2771 | 6ea83fed | bellard | #define FLOAT_UNOP(name) \
|
2772 | 6ea83fed | bellard | FLOAT_OP(name, d) \ |
2773 | 6ea83fed | bellard | { \ |
2774 | 6ea83fed | bellard | FDT2 = float64_ ## name(FDT0); \ |
2775 | 6ea83fed | bellard | DEBUG_FPU_STATE(); \ |
2776 | fbcc6828 | ths | RETURN(); \ |
2777 | 6ea83fed | bellard | } \ |
2778 | 6ea83fed | bellard | FLOAT_OP(name, s) \ |
2779 | 6ea83fed | bellard | { \ |
2780 | 6ea83fed | bellard | FST2 = float32_ ## name(FST0); \ |
2781 | 6ea83fed | bellard | DEBUG_FPU_STATE(); \ |
2782 | fbcc6828 | ths | RETURN(); \ |
2783 | 5a5012ec | ths | } \ |
2784 | 5a5012ec | ths | FLOAT_OP(name, ps) \ |
2785 | 5a5012ec | ths | { \ |
2786 | 5a5012ec | ths | FST2 = float32_ ## name(FST0); \ |
2787 | 5a5012ec | ths | FSTH2 = float32_ ## name(FSTH0); \ |
2788 | 5a5012ec | ths | DEBUG_FPU_STATE(); \ |
2789 | fbcc6828 | ths | RETURN(); \ |
2790 | 6ea83fed | bellard | } |
2791 | 6ea83fed | bellard | FLOAT_UNOP(abs) |
2792 | 6ea83fed | bellard | FLOAT_UNOP(chs) |
2793 | 6ea83fed | bellard | #undef FLOAT_UNOP
|
2794 | 6ea83fed | bellard | |
2795 | 6ea83fed | bellard | FLOAT_OP(mov, d) |
2796 | 6ea83fed | bellard | { |
2797 | 6ea83fed | bellard | FDT2 = FDT0; |
2798 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
2799 | 6ea83fed | bellard | RETURN(); |
2800 | 6ea83fed | bellard | } |
2801 | 6ea83fed | bellard | FLOAT_OP(mov, s) |
2802 | 6ea83fed | bellard | { |
2803 | 6ea83fed | bellard | FST2 = FST0; |
2804 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
2805 | 6ea83fed | bellard | RETURN(); |
2806 | 6ea83fed | bellard | } |
2807 | 5a5012ec | ths | FLOAT_OP(mov, ps) |
2808 | 5a5012ec | ths | { |
2809 | 5a5012ec | ths | FST2 = FST0; |
2810 | 5a5012ec | ths | FSTH2 = FSTH0; |
2811 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2812 | 5a5012ec | ths | RETURN(); |
2813 | 5a5012ec | ths | } |
2814 | 5a5012ec | ths | FLOAT_OP(alnv, ps) |
2815 | 5a5012ec | ths | { |
2816 | 5a5012ec | ths | switch (T0 & 0x7) { |
2817 | 5a5012ec | ths | case 0: |
2818 | 5a5012ec | ths | FST2 = FST0; |
2819 | 5a5012ec | ths | FSTH2 = FSTH0; |
2820 | 5a5012ec | ths | break;
|
2821 | 5a5012ec | ths | case 4: |
2822 | 5a5012ec | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
2823 | 5a5012ec | ths | FSTH2 = FST0; |
2824 | 5a5012ec | ths | FST2 = FSTH1; |
2825 | 5a5012ec | ths | #else
|
2826 | 5a5012ec | ths | FSTH2 = FST1; |
2827 | 5a5012ec | ths | FST2 = FSTH0; |
2828 | 5a5012ec | ths | #endif
|
2829 | 5a5012ec | ths | break;
|
2830 | 5a5012ec | ths | default: /* unpredictable */ |
2831 | 5a5012ec | ths | break;
|
2832 | 5a5012ec | ths | } |
2833 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2834 | 5a5012ec | ths | RETURN(); |
2835 | 5a5012ec | ths | } |
2836 | 6ea83fed | bellard | |
2837 | 6ea83fed | bellard | #ifdef CONFIG_SOFTFLOAT
|
2838 | 6ea83fed | bellard | #define clear_invalid() do { \ |
2839 | ead9360e | ths | int flags = get_float_exception_flags(&env->fpu->fp_status); \
|
2840 | 6ea83fed | bellard | flags &= ~float_flag_invalid; \ |
2841 | ead9360e | ths | set_float_exception_flags(flags, &env->fpu->fp_status); \ |
2842 | 6ea83fed | bellard | } while(0) |
2843 | 6ea83fed | bellard | #else
|
2844 | 6ea83fed | bellard | #define clear_invalid() do { } while(0) |
2845 | 6ea83fed | bellard | #endif
|
2846 | 6ea83fed | bellard | |
2847 | 6ea83fed | bellard | extern void dump_fpu_s(CPUState *env); |
2848 | 6ea83fed | bellard | |
2849 | fd4a04eb | ths | #define CMP_OP(fmt, op) \
|
2850 | fd4a04eb | ths | void OPPROTO op_cmp ## _ ## fmt ## _ ## op(void) \ |
2851 | fd4a04eb | ths | { \ |
2852 | fd4a04eb | ths | CALL_FROM_TB1(do_cmp ## _ ## fmt ## _ ## op, PARAM1); \ |
2853 | fd4a04eb | ths | DEBUG_FPU_STATE(); \ |
2854 | fd4a04eb | ths | RETURN(); \ |
2855 | fd4a04eb | ths | } \ |
2856 | fd4a04eb | ths | void OPPROTO op_cmpabs ## _ ## fmt ## _ ## op(void) \ |
2857 | fd4a04eb | ths | { \ |
2858 | fd4a04eb | ths | CALL_FROM_TB1(do_cmpabs ## _ ## fmt ## _ ## op, PARAM1); \ |
2859 | fd4a04eb | ths | DEBUG_FPU_STATE(); \ |
2860 | fd4a04eb | ths | RETURN(); \ |
2861 | fd4a04eb | ths | } |
2862 | fd4a04eb | ths | #define CMP_OPS(op) \
|
2863 | fd4a04eb | ths | CMP_OP(d, op) \ |
2864 | fd4a04eb | ths | CMP_OP(s, op) \ |
2865 | fd4a04eb | ths | CMP_OP(ps, op) |
2866 | fd4a04eb | ths | |
2867 | fd4a04eb | ths | CMP_OPS(f) |
2868 | fd4a04eb | ths | CMP_OPS(un) |
2869 | fd4a04eb | ths | CMP_OPS(eq) |
2870 | fd4a04eb | ths | CMP_OPS(ueq) |
2871 | fd4a04eb | ths | CMP_OPS(olt) |
2872 | fd4a04eb | ths | CMP_OPS(ult) |
2873 | fd4a04eb | ths | CMP_OPS(ole) |
2874 | fd4a04eb | ths | CMP_OPS(ule) |
2875 | fd4a04eb | ths | CMP_OPS(sf) |
2876 | fd4a04eb | ths | CMP_OPS(ngle) |
2877 | fd4a04eb | ths | CMP_OPS(seq) |
2878 | fd4a04eb | ths | CMP_OPS(ngl) |
2879 | fd4a04eb | ths | CMP_OPS(lt) |
2880 | fd4a04eb | ths | CMP_OPS(nge) |
2881 | fd4a04eb | ths | CMP_OPS(le) |
2882 | fd4a04eb | ths | CMP_OPS(ngt) |
2883 | fd4a04eb | ths | #undef CMP_OPS
|
2884 | fd4a04eb | ths | #undef CMP_OP
|
2885 | 6ea83fed | bellard | |
2886 | 6ea83fed | bellard | void op_bc1f (void) |
2887 | 6ea83fed | bellard | { |
2888 | ead9360e | ths | T0 = !!(~GET_FP_COND(env->fpu) & (0x1 << PARAM1));
|
2889 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2890 | 5a5012ec | ths | RETURN(); |
2891 | 5a5012ec | ths | } |
2892 | fd4a04eb | ths | void op_bc1any2f (void) |
2893 | 5a5012ec | ths | { |
2894 | ead9360e | ths | T0 = !!(~GET_FP_COND(env->fpu) & (0x3 << PARAM1));
|
2895 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2896 | 5a5012ec | ths | RETURN(); |
2897 | 5a5012ec | ths | } |
2898 | fd4a04eb | ths | void op_bc1any4f (void) |
2899 | 5a5012ec | ths | { |
2900 | ead9360e | ths | T0 = !!(~GET_FP_COND(env->fpu) & (0xf << PARAM1));
|
2901 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
2902 | 6ea83fed | bellard | RETURN(); |
2903 | 6ea83fed | bellard | } |
2904 | 6ea83fed | bellard | |
2905 | 6ea83fed | bellard | void op_bc1t (void) |
2906 | 6ea83fed | bellard | { |
2907 | ead9360e | ths | T0 = !!(GET_FP_COND(env->fpu) & (0x1 << PARAM1));
|
2908 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2909 | 5a5012ec | ths | RETURN(); |
2910 | 5a5012ec | ths | } |
2911 | fd4a04eb | ths | void op_bc1any2t (void) |
2912 | 5a5012ec | ths | { |
2913 | ead9360e | ths | T0 = !!(GET_FP_COND(env->fpu) & (0x3 << PARAM1));
|
2914 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
2915 | 5a5012ec | ths | RETURN(); |
2916 | 5a5012ec | ths | } |
2917 | fd4a04eb | ths | void op_bc1any4t (void) |
2918 | 5a5012ec | ths | { |
2919 | ead9360e | ths | T0 = !!(GET_FP_COND(env->fpu) & (0xf << PARAM1));
|
2920 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
2921 | 6ea83fed | bellard | RETURN(); |
2922 | 6ea83fed | bellard | } |
2923 | 6ea83fed | bellard | |
2924 | 6af0bf9c | bellard | void op_tlbwi (void) |
2925 | 6af0bf9c | bellard | { |
2926 | ead9360e | ths | CALL_FROM_TB0(env->tlb->do_tlbwi); |
2927 | 6af0bf9c | bellard | RETURN(); |
2928 | 6af0bf9c | bellard | } |
2929 | 6af0bf9c | bellard | |
2930 | 6af0bf9c | bellard | void op_tlbwr (void) |
2931 | 6af0bf9c | bellard | { |
2932 | ead9360e | ths | CALL_FROM_TB0(env->tlb->do_tlbwr); |
2933 | 6af0bf9c | bellard | RETURN(); |
2934 | 6af0bf9c | bellard | } |
2935 | 6af0bf9c | bellard | |
2936 | 6af0bf9c | bellard | void op_tlbp (void) |
2937 | 6af0bf9c | bellard | { |
2938 | ead9360e | ths | CALL_FROM_TB0(env->tlb->do_tlbp); |
2939 | 6af0bf9c | bellard | RETURN(); |
2940 | 6af0bf9c | bellard | } |
2941 | 6af0bf9c | bellard | |
2942 | 6af0bf9c | bellard | void op_tlbr (void) |
2943 | 6af0bf9c | bellard | { |
2944 | ead9360e | ths | CALL_FROM_TB0(env->tlb->do_tlbr); |
2945 | 6af0bf9c | bellard | RETURN(); |
2946 | 6af0bf9c | bellard | } |
2947 | 6af0bf9c | bellard | |
2948 | 6af0bf9c | bellard | /* Specials */
|
2949 | 6f5b89a0 | ths | #if defined (CONFIG_USER_ONLY)
|
2950 | 6f5b89a0 | ths | void op_tls_value (void) |
2951 | 6f5b89a0 | ths | { |
2952 | 5a5012ec | ths | T0 = env->tls_value; |
2953 | 6f5b89a0 | ths | } |
2954 | 6f5b89a0 | ths | #endif
|
2955 | 6f5b89a0 | ths | |
2956 | 6af0bf9c | bellard | void op_pmon (void) |
2957 | 6af0bf9c | bellard | { |
2958 | 6af0bf9c | bellard | CALL_FROM_TB1(do_pmon, PARAM1); |
2959 | 7a387fff | ths | RETURN(); |
2960 | 7a387fff | ths | } |
2961 | 7a387fff | ths | |
2962 | 7a387fff | ths | void op_di (void) |
2963 | 7a387fff | ths | { |
2964 | 7a387fff | ths | T0 = env->CP0_Status; |
2965 | 4de9b249 | ths | env->CP0_Status = T0 & ~(1 << CP0St_IE);
|
2966 | 4de9b249 | ths | CALL_FROM_TB1(cpu_mips_update_irq, env); |
2967 | 7a387fff | ths | RETURN(); |
2968 | 7a387fff | ths | } |
2969 | 7a387fff | ths | |
2970 | 7a387fff | ths | void op_ei (void) |
2971 | 7a387fff | ths | { |
2972 | 7a387fff | ths | T0 = env->CP0_Status; |
2973 | 4de9b249 | ths | env->CP0_Status = T0 | (1 << CP0St_IE);
|
2974 | 4de9b249 | ths | CALL_FROM_TB1(cpu_mips_update_irq, env); |
2975 | 7a387fff | ths | RETURN(); |
2976 | 6af0bf9c | bellard | } |
2977 | 6af0bf9c | bellard | |
2978 | 6af0bf9c | bellard | void op_trap (void) |
2979 | 6af0bf9c | bellard | { |
2980 | 6af0bf9c | bellard | if (T0) {
|
2981 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_TRAP); |
2982 | 6af0bf9c | bellard | } |
2983 | 6af0bf9c | bellard | RETURN(); |
2984 | 6af0bf9c | bellard | } |
2985 | 6af0bf9c | bellard | |
2986 | 4ad40f36 | bellard | void op_debug (void) |
2987 | 4ad40f36 | bellard | { |
2988 | 7a387fff | ths | CALL_FROM_TB1(do_raise_exception, EXCP_DEBUG); |
2989 | 7a387fff | ths | RETURN(); |
2990 | 4ad40f36 | bellard | } |
2991 | 4ad40f36 | bellard | |
2992 | 6af0bf9c | bellard | void op_set_lladdr (void) |
2993 | 6af0bf9c | bellard | { |
2994 | 6af0bf9c | bellard | env->CP0_LLAddr = T2; |
2995 | 7a387fff | ths | RETURN(); |
2996 | 6af0bf9c | bellard | } |
2997 | 6af0bf9c | bellard | |
2998 | f41c52f1 | ths | void debug_pre_eret (void); |
2999 | f41c52f1 | ths | void debug_post_eret (void); |
3000 | 6af0bf9c | bellard | void op_eret (void) |
3001 | 6af0bf9c | bellard | { |
3002 | f41c52f1 | ths | if (loglevel & CPU_LOG_EXEC)
|
3003 | f41c52f1 | ths | CALL_FROM_TB0(debug_pre_eret); |
3004 | 24c7b0e3 | ths | if (env->CP0_Status & (1 << CP0St_ERL)) { |
3005 | ead9360e | ths | env->PC[env->current_tc] = env->CP0_ErrorEPC; |
3006 | 24c7b0e3 | ths | env->CP0_Status &= ~(1 << CP0St_ERL);
|
3007 | 51e11d9e | bellard | } else {
|
3008 | ead9360e | ths | env->PC[env->current_tc] = env->CP0_EPC; |
3009 | 24c7b0e3 | ths | env->CP0_Status &= ~(1 << CP0St_EXL);
|
3010 | 51e11d9e | bellard | } |
3011 | 24c7b0e3 | ths | if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
3012 | 24c7b0e3 | ths | !(env->CP0_Status & (1 << CP0St_ERL)) &&
|
3013 | 24c7b0e3 | ths | !(env->hflags & MIPS_HFLAG_DM) && |
3014 | 24c7b0e3 | ths | (env->CP0_Status & (1 << CP0St_UM)))
|
3015 | 24c7b0e3 | ths | env->hflags |= MIPS_HFLAG_UM; |
3016 | 6e473128 | ths | #ifdef TARGET_MIPS64
|
3017 | 3ddf0b5c | ths | if (!(env->CP0_Config0 & (0x3 << CP0C0_AT)) || |
3018 | 3ddf0b5c | ths | ((env->hflags & MIPS_HFLAG_UM) && |
3019 | 6e473128 | ths | !(env->CP0_Status & (1 << CP0St_PX)) &&
|
3020 | 3ddf0b5c | ths | !(env->CP0_Status & (1 << CP0St_UX))))
|
3021 | 6e473128 | ths | env->hflags &= ~MIPS_HFLAG_64; |
3022 | 6e473128 | ths | #endif
|
3023 | f41c52f1 | ths | if (loglevel & CPU_LOG_EXEC)
|
3024 | f41c52f1 | ths | CALL_FROM_TB0(debug_post_eret); |
3025 | 6af0bf9c | bellard | env->CP0_LLAddr = 1;
|
3026 | 7a387fff | ths | RETURN(); |
3027 | 6af0bf9c | bellard | } |
3028 | 6af0bf9c | bellard | |
3029 | 6af0bf9c | bellard | void op_deret (void) |
3030 | 6af0bf9c | bellard | { |
3031 | f41c52f1 | ths | if (loglevel & CPU_LOG_EXEC)
|
3032 | f41c52f1 | ths | CALL_FROM_TB0(debug_pre_eret); |
3033 | ead9360e | ths | env->PC[env->current_tc] = env->CP0_DEPC; |
3034 | 24c7b0e3 | ths | env->hflags |= MIPS_HFLAG_DM; |
3035 | 24c7b0e3 | ths | if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
3036 | 24c7b0e3 | ths | !(env->CP0_Status & (1 << CP0St_ERL)) &&
|
3037 | 24c7b0e3 | ths | !(env->hflags & MIPS_HFLAG_DM) && |
3038 | 24c7b0e3 | ths | (env->CP0_Status & (1 << CP0St_UM)))
|
3039 | 24c7b0e3 | ths | env->hflags |= MIPS_HFLAG_UM; |
3040 | 6e473128 | ths | #ifdef TARGET_MIPS64
|
3041 | 3ddf0b5c | ths | if (!(env->CP0_Config0 & (0x3 << CP0C0_AT)) || |
3042 | 3ddf0b5c | ths | ((env->hflags & MIPS_HFLAG_UM) && |
3043 | 6e473128 | ths | !(env->CP0_Status & (1 << CP0St_PX)) &&
|
3044 | 3ddf0b5c | ths | !(env->CP0_Status & (1 << CP0St_UX))))
|
3045 | 6e473128 | ths | env->hflags &= ~MIPS_HFLAG_64; |
3046 | 6e473128 | ths | #endif
|
3047 | f41c52f1 | ths | if (loglevel & CPU_LOG_EXEC)
|
3048 | f41c52f1 | ths | CALL_FROM_TB0(debug_post_eret); |
3049 | 24c7b0e3 | ths | env->CP0_LLAddr = 1;
|
3050 | 7a387fff | ths | RETURN(); |
3051 | 7a387fff | ths | } |
3052 | 7a387fff | ths | |
3053 | 7a387fff | ths | void op_rdhwr_cpunum(void) |
3054 | 7a387fff | ths | { |
3055 | 1579a72e | ths | if (!(env->hflags & MIPS_HFLAG_UM) ||
|
3056 | 97428a4d | ths | (env->CP0_HWREna & (1 << 0)) || |
3057 | 1579a72e | ths | (env->CP0_Status & (1 << CP0St_CU0)))
|
3058 | 1579a72e | ths | T0 = env->CP0_EBase & 0x3ff;
|
3059 | 7a387fff | ths | else
|
3060 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_RI); |
3061 | 7a387fff | ths | RETURN(); |
3062 | 7a387fff | ths | } |
3063 | 7a387fff | ths | |
3064 | 7a387fff | ths | void op_rdhwr_synci_step(void) |
3065 | 7a387fff | ths | { |
3066 | 1579a72e | ths | if (!(env->hflags & MIPS_HFLAG_UM) ||
|
3067 | 97428a4d | ths | (env->CP0_HWREna & (1 << 1)) || |
3068 | 1579a72e | ths | (env->CP0_Status & (1 << CP0St_CU0)))
|
3069 | 1579a72e | ths | T0 = env->SYNCI_Step; |
3070 | 7a387fff | ths | else
|
3071 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_RI); |
3072 | 7a387fff | ths | RETURN(); |
3073 | 7a387fff | ths | } |
3074 | 7a387fff | ths | |
3075 | 7a387fff | ths | void op_rdhwr_cc(void) |
3076 | 7a387fff | ths | { |
3077 | 1579a72e | ths | if (!(env->hflags & MIPS_HFLAG_UM) ||
|
3078 | 97428a4d | ths | (env->CP0_HWREna & (1 << 2)) || |
3079 | 1579a72e | ths | (env->CP0_Status & (1 << CP0St_CU0)))
|
3080 | 1579a72e | ths | T0 = env->CP0_Count; |
3081 | 7a387fff | ths | else
|
3082 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_RI); |
3083 | 7a387fff | ths | RETURN(); |
3084 | 7a387fff | ths | } |
3085 | 7a387fff | ths | |
3086 | 7a387fff | ths | void op_rdhwr_ccres(void) |
3087 | 7a387fff | ths | { |
3088 | 1579a72e | ths | if (!(env->hflags & MIPS_HFLAG_UM) ||
|
3089 | 97428a4d | ths | (env->CP0_HWREna & (1 << 3)) || |
3090 | 1579a72e | ths | (env->CP0_Status & (1 << CP0St_CU0)))
|
3091 | 1579a72e | ths | T0 = env->CCRes; |
3092 | 7a387fff | ths | else
|
3093 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_RI); |
3094 | 1579a72e | ths | RETURN(); |
3095 | 1579a72e | ths | } |
3096 | 1579a72e | ths | |
3097 | 6af0bf9c | bellard | void op_save_state (void) |
3098 | 6af0bf9c | bellard | { |
3099 | 6af0bf9c | bellard | env->hflags = PARAM1; |
3100 | 6af0bf9c | bellard | RETURN(); |
3101 | 6af0bf9c | bellard | } |
3102 | 6af0bf9c | bellard | |
3103 | 6af0bf9c | bellard | void op_save_pc (void) |
3104 | 6af0bf9c | bellard | { |
3105 | ead9360e | ths | env->PC[env->current_tc] = PARAM1; |
3106 | 6af0bf9c | bellard | RETURN(); |
3107 | 6af0bf9c | bellard | } |
3108 | 6af0bf9c | bellard | |
3109 | 9b9e4393 | ths | #ifdef TARGET_MIPS64
|
3110 | 9b9e4393 | ths | void op_save_pc64 (void) |
3111 | 9b9e4393 | ths | { |
3112 | ead9360e | ths | env->PC[env->current_tc] = ((uint64_t)PARAM1 << 32) | (uint32_t)PARAM2;
|
3113 | 9b9e4393 | ths | RETURN(); |
3114 | 9b9e4393 | ths | } |
3115 | 9b9e4393 | ths | #endif
|
3116 | 9b9e4393 | ths | |
3117 | 16c00cb2 | ths | void op_interrupt_restart (void) |
3118 | 16c00cb2 | ths | { |
3119 | 16c00cb2 | ths | if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
3120 | 16c00cb2 | ths | !(env->CP0_Status & (1 << CP0St_ERL)) &&
|
3121 | 16c00cb2 | ths | !(env->hflags & MIPS_HFLAG_DM) && |
3122 | 16c00cb2 | ths | (env->CP0_Status & (1 << CP0St_IE)) &&
|
3123 | 16c00cb2 | ths | (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) { |
3124 | 16c00cb2 | ths | env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
|
3125 | 16c00cb2 | ths | CALL_FROM_TB1(do_raise_exception, EXCP_EXT_INTERRUPT); |
3126 | 16c00cb2 | ths | } |
3127 | 16c00cb2 | ths | RETURN(); |
3128 | 16c00cb2 | ths | } |
3129 | 16c00cb2 | ths | |
3130 | 6af0bf9c | bellard | void op_raise_exception (void) |
3131 | 6af0bf9c | bellard | { |
3132 | 6af0bf9c | bellard | CALL_FROM_TB1(do_raise_exception, PARAM1); |
3133 | 6af0bf9c | bellard | RETURN(); |
3134 | 6af0bf9c | bellard | } |
3135 | 6af0bf9c | bellard | |
3136 | 6af0bf9c | bellard | void op_raise_exception_err (void) |
3137 | 6af0bf9c | bellard | { |
3138 | 6af0bf9c | bellard | CALL_FROM_TB2(do_raise_exception_err, PARAM1, PARAM2); |
3139 | 6af0bf9c | bellard | RETURN(); |
3140 | 6af0bf9c | bellard | } |
3141 | 6af0bf9c | bellard | |
3142 | 6af0bf9c | bellard | void op_exit_tb (void) |
3143 | 6af0bf9c | bellard | { |
3144 | 6af0bf9c | bellard | EXIT_TB(); |
3145 | 7a387fff | ths | RETURN(); |
3146 | 6af0bf9c | bellard | } |
3147 | 6af0bf9c | bellard | |
3148 | 4ad40f36 | bellard | void op_wait (void) |
3149 | 4ad40f36 | bellard | { |
3150 | 4ad40f36 | bellard | env->halted = 1;
|
3151 | 4ad40f36 | bellard | CALL_FROM_TB1(do_raise_exception, EXCP_HLT); |
3152 | 7a387fff | ths | RETURN(); |
3153 | 7a387fff | ths | } |
3154 | 7a387fff | ths | |
3155 | 7a387fff | ths | /* Bitfield operations. */
|
3156 | 7a387fff | ths | void op_ext(void) |
3157 | 7a387fff | ths | { |
3158 | 7a387fff | ths | unsigned int pos = PARAM1; |
3159 | 7a387fff | ths | unsigned int size = PARAM2; |
3160 | 7a387fff | ths | |
3161 | f757d6ff | ths | T0 = ((uint32_t)T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0); |
3162 | 7a387fff | ths | RETURN(); |
3163 | 7a387fff | ths | } |
3164 | 7a387fff | ths | |
3165 | 7a387fff | ths | void op_ins(void) |
3166 | 7a387fff | ths | { |
3167 | 7a387fff | ths | unsigned int pos = PARAM1; |
3168 | 7a387fff | ths | unsigned int size = PARAM2; |
3169 | f757d6ff | ths | target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos; |
3170 | 7a387fff | ths | |
3171 | 171b31e7 | ths | T0 = (T0 & ~mask) | (((uint32_t)T1 << pos) & mask); |
3172 | 7a387fff | ths | RETURN(); |
3173 | 7a387fff | ths | } |
3174 | 7a387fff | ths | |
3175 | 7a387fff | ths | void op_wsbh(void) |
3176 | 7a387fff | ths | { |
3177 | 7a387fff | ths | T0 = ((T1 << 8) & ~0x00FF00FF) | ((T1 >> 8) & 0x00FF00FF); |
3178 | 7a387fff | ths | RETURN(); |
3179 | 7a387fff | ths | } |
3180 | 7a387fff | ths | |
3181 | 60aa19ab | ths | #ifdef TARGET_MIPS64
|
3182 | c570fd16 | ths | void op_dext(void) |
3183 | c570fd16 | ths | { |
3184 | c570fd16 | ths | unsigned int pos = PARAM1; |
3185 | c570fd16 | ths | unsigned int size = PARAM2; |
3186 | c570fd16 | ths | |
3187 | f757d6ff | ths | T0 = (T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0); |
3188 | c570fd16 | ths | RETURN(); |
3189 | c570fd16 | ths | } |
3190 | c570fd16 | ths | |
3191 | c570fd16 | ths | void op_dins(void) |
3192 | c570fd16 | ths | { |
3193 | c570fd16 | ths | unsigned int pos = PARAM1; |
3194 | c570fd16 | ths | unsigned int size = PARAM2; |
3195 | f757d6ff | ths | target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos; |
3196 | c570fd16 | ths | |
3197 | 171b31e7 | ths | T0 = (T0 & ~mask) | ((T1 << pos) & mask); |
3198 | c570fd16 | ths | RETURN(); |
3199 | c570fd16 | ths | } |
3200 | c570fd16 | ths | |
3201 | 7a387fff | ths | void op_dsbh(void) |
3202 | 7a387fff | ths | { |
3203 | 7a387fff | ths | T0 = ((T1 << 8) & ~0x00FF00FF00FF00FFULL) | ((T1 >> 8) & 0x00FF00FF00FF00FFULL); |
3204 | 7a387fff | ths | RETURN(); |
3205 | 7a387fff | ths | } |
3206 | 7a387fff | ths | |
3207 | 7a387fff | ths | void op_dshd(void) |
3208 | 7a387fff | ths | { |
3209 | 7a387fff | ths | T0 = ((T1 << 16) & ~0x0000FFFF0000FFFFULL) | ((T1 >> 16) & 0x0000FFFF0000FFFFULL); |
3210 | 7a387fff | ths | RETURN(); |
3211 | 7a387fff | ths | } |
3212 | c570fd16 | ths | #endif
|
3213 | 7a387fff | ths | |
3214 | 7a387fff | ths | void op_seb(void) |
3215 | 7a387fff | ths | { |
3216 | 7a387fff | ths | T0 = ((T1 & 0xFF) ^ 0x80) - 0x80; |
3217 | 7a387fff | ths | RETURN(); |
3218 | 7a387fff | ths | } |
3219 | 7a387fff | ths | |
3220 | 7a387fff | ths | void op_seh(void) |
3221 | 7a387fff | ths | { |
3222 | 7a387fff | ths | T0 = ((T1 & 0xFFFF) ^ 0x8000) - 0x8000; |
3223 | 7a387fff | ths | RETURN(); |
3224 | 4ad40f36 | bellard | } |