commit 5fafdf24ef2c090c164d4dc89684b3f379dbdd87
Author: ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>
Date:   Sun Sep 16 21:08:06 2007 +0000

    find -type f | xargs sed -i 's/[\t ]$//g' # on most files
    
    
    git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162

diff --git a/arm-dis.c b/arm-dis.c
index 1e027ef..7032f95 100644
--- a/arm-dis.c
+++ b/arm-dis.c
@@ -4,17 +4,17 @@
    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
    Modification by James G. Smith (jsmith@cygnus.co.uk)
 
-This file is part of libopcodes. 
+This file is part of libopcodes.
 
 This program is free software; you can redistribute it and/or modify it under
 the terms of the GNU General Public License as published by the Free
 Software Foundation; either version 2 of the License, or (at your option)
-any later version. 
+any later version.
 
 This program is distributed in the hope that it will be useful, but WITHOUT
 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-more details. 
+more details.
 
 You should have received a copy of the GNU General Public License
 along with this program; if not, write to the Free Software
@@ -34,7 +34,7 @@ struct thumb_opcode
 };
 
 /* format of the assembler string :
-   
+  
    %%			%
    %<bitfield>d		print the bitfield in decimal
    %<bitfield>x		print the bitfield in hex
@@ -104,7 +104,7 @@ static struct arm_opcode arm_opcodes[] =
     {0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
     {0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
     {0xf450f000, 0xfc70f000, "pld\t%a"},
-    
+   
     /* V5 Instructions.  */
     {0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
     {0xfa000000, 0xfe000000, "blx\t%B"},
@@ -116,7 +116,7 @@ static struct arm_opcode arm_opcodes[] =
     {0xfe000010, 0xff100010, "mcr2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
     {0xfe100010, 0xff100010, "mrc2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 
-    /* V5E "El Segundo" Instructions.  */    
+    /* V5E "El Segundo" Instructions.  */   
     {0x000000d0, 0x0e1000f0, "ldr%cd\t%12-15r, %s"},
     {0x000000f0, 0x0e1000f0, "str%cd\t%12-15r, %s"},
     {0x01000080, 0x0ff000f0, "smlabb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
@@ -303,7 +303,7 @@ static struct arm_opcode arm_opcodes[] =
     {0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
     {0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
     {0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
-    {0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, 
+    {0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
     {0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
     {0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
     {0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
@@ -571,7 +571,7 @@ static boolean force_thumb = false;
 static char * arm_fp_const[] =
 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
 
-static char * arm_shift[] = 
+static char * arm_shift[] =
 {"lsl", "lsr", "asr", "ror"};
 
 /* Forward declarations.  */
@@ -621,14 +621,14 @@ arm_decode_shift (given, func, stream)
      void * stream;
 {
   func (stream, "%s", arm_regnames[given & 0xf]);
-  
+ 
   if ((given & 0xff0) != 0)
     {
       if ((given & 0x10) == 0)
 	{
 	  int amount = (given & 0xf80) >> 7;
 	  int shift = (given & 0x60) >> 5;
-	  
+	 
 	  if (amount == 0)
 	    {
 	      if (shift == 3)
@@ -636,10 +636,10 @@ arm_decode_shift (given, func, stream)
 		  func (stream, ", rrx");
 		  return;
 		}
-	      
+	     
 	      amount = 32;
 	    }
-	  
+	 
 	  func (stream, ", %s #%d", arm_shift[shift], amount);
 	}
       else
@@ -666,7 +666,7 @@ print_insn_arm1 (pc, info, given)
       if ((given & insn->mask) == insn->value)
 	{
 	  char * c;
-	  
+	 
 	  for (c = insn->assembler; *c; c++)
 	    {
 	      if (*c == '%')
@@ -682,14 +682,14 @@ print_insn_arm1 (pc, info, given)
 			  && ((given & 0x02000000) == 0))
 			{
 			  int offset = given & 0xfff;
-			  
+			 
 			  func (stream, "[pc");
- 
+
 			  if (given & 0x01000000)
 			    {
 			      if ((given & 0x00800000) == 0)
 				offset = - offset;
-			  
+			 
 			      /* Pre-indexed.  */
 			      func (stream, ", #%d]", offset);
 
@@ -710,13 +710,13 @@ print_insn_arm1 (pc, info, given)
 			      /* ie ignore the offset.  */
 			      offset = pc + 8;
 			    }
-			  
+			 
 			  func (stream, "\t; ");
 			  info->print_address_func (offset, info);
 			}
 		      else
 			{
-			  func (stream, "[%s", 
+			  func (stream, "[%s",
 				arm_regnames[(given >> 16) & 0xf]);
 			  if ((given & 0x01000000) != 0)
 			    {
@@ -736,7 +736,7 @@ print_insn_arm1 (pc, info, given)
 				  arm_decode_shift (given, func, stream);
 				}
 
-			      func (stream, "]%s", 
+			      func (stream, "]%s",
 				    ((given & 0x00200000) != 0) ? "!" : "");
 			    }
 			  else
@@ -748,13 +748,13 @@ print_insn_arm1 (pc, info, given)
 				    func (stream, "], %s#%d",
 					  (((given & 0x00800000) == 0)
 					   ? "-" : ""), offset);
-				  else 
+				  else
 				    func (stream, "]");
 				}
 			      else
 				{
 				  func (stream, "], %s",
-					(((given & 0x00800000) == 0) 
+					(((given & 0x00800000) == 0)
 					 ? "-" : ""));
 				  arm_decode_shift (given, func, stream);
 				}
@@ -767,18 +767,18 @@ print_insn_arm1 (pc, info, given)
 			{
                           /* PC relative with immediate offset.  */
 			  int offset = ((given & 0xf00) >> 4) | (given & 0xf);
-			  
+			 
 			  if ((given & 0x00800000) == 0)
 			    offset = -offset;
-			  
+			 
 			  func (stream, "[pc, #%d]\t; ", offset);
-			  
+			 
 			  (*info->print_address_func)
 			    (offset + pc + 8, info);
 			}
 		      else
 			{
-			  func (stream, "[%s", 
+			  func (stream, "[%s",
 				arm_regnames[(given >> 16) & 0xf]);
 			  if ((given & 0x01000000) != 0)
 			    {
@@ -801,7 +801,7 @@ print_insn_arm1 (pc, info, given)
                                         arm_regnames[given & 0xf]);
 				}
 
-			      func (stream, "]%s", 
+			      func (stream, "]%s",
 				    ((given & 0x00200000) != 0) ? "!" : "");
 			    }
 			  else
@@ -815,7 +815,7 @@ print_insn_arm1 (pc, info, given)
 				    func (stream, "], %s#%d",
 					  (((given & 0x00800000) == 0)
 					   ? "-" : ""), offset);
-				  else 
+				  else
 				    func (stream, "]");
 				}
 			      else
@@ -829,7 +829,7 @@ print_insn_arm1 (pc, info, given)
 			    }
 			}
 		      break;
-			  
+			 
 		    case 'b':
 		      (*info->print_address_func)
 			(BDISP (given) * 4 + pc + 8, info);
@@ -911,7 +911,7 @@ print_insn_arm1 (pc, info, given)
 		      {
 			bfd_vma address;
 			bfd_vma offset = 0;
-			
+		
 			if (given & 0x00800000)
 			  /* Is signed, hi bits should be ones.  */
 			  offset = (-1) ^ 0x00ffffff;
@@ -920,7 +920,7 @@ print_insn_arm1 (pc, info, given)
 			offset += given & 0x00ffffff;
 			offset <<= 2;
 			address = offset + pc + 8;
-			
+		
 			if (given & 0x01000000)
 			  /* H bit allows addressing to 2-byte boundaries.  */
 			  address += 2;
@@ -976,7 +976,7 @@ print_insn_arm1 (pc, info, given)
 			  func (stream, "3");
 			}
 		      break;
-			
+		
 		    case 'P':
 		      switch (given & 0x00080080)
 			{
@@ -1028,7 +1028,7 @@ print_insn_arm1 (pc, info, given)
 			}
 		      break;
 
-		    case '0': case '1': case '2': case '3': case '4': 
+		    case '0': case '1': case '2': case '3': case '4':
 		    case '5': case '6': case '7': case '8': case '9':
 		      {
 			int bitstart = *c++ - '0';
@@ -1040,44 +1040,44 @@ print_insn_arm1 (pc, info, given)
 			  {
 			  case '-':
 			    c++;
-			    
+			   
 			    while (*c >= '0' && *c <= '9')
 			      bitend = (bitend * 10) + *c++ - '0';
-			    
+			   
 			    if (!bitend)
 			      abort ();
-			    
+			   
 			    switch (*c)
 			      {
 			      case 'r':
 				{
 				  long reg;
-				  
+				 
 				  reg = given >> bitstart;
 				  reg &= (2 << (bitend - bitstart)) - 1;
-				  
+				 
 				  func (stream, "%s", arm_regnames[reg]);
 				}
 				break;
 			      case 'd':
 				{
 				  long reg;
-				  
+				 
 				  reg = given >> bitstart;
 				  reg &= (2 << (bitend - bitstart)) - 1;
-				  
+				 
 				  func (stream, "%d", reg);
 				}
 				break;
 			      case 'x':
 				{
 				  long reg;
-				  
+				 
 				  reg = given >> bitstart;
 				  reg &= (2 << (bitend - bitstart)) - 1;
-				  
+				 
 				  func (stream, "0x%08x", reg);
-				  
+				 
 				  /* Some SWI instructions have special
 				     meanings.  */
 				  if ((given & 0x0fffffff) == 0x0FF00000)
@@ -1089,20 +1089,20 @@ print_insn_arm1 (pc, info, given)
 			      case 'X':
 				{
 				  long reg;
-				  
+				 
 				  reg = given >> bitstart;
 				  reg &= (2 << (bitend - bitstart)) - 1;
-				  
+				 
 				  func (stream, "%01x", reg & 0xf);
 				}
 				break;
 			      case 'f':
 				{
 				  long reg;
-				  
+				 
 				  reg = given >> bitstart;
 				  reg &= (2 << (bitend - bitstart)) - 1;
-				  
+				 
 				  if (reg > 7)
 				    func (stream, "#%s",
 					  arm_fp_const[reg & 7]);
@@ -1163,7 +1163,7 @@ print_insn_arm1 (pc, info, given)
 				    }
 				  break;
 
-				  
+				 
 				default:
 				  abort ();
 				}
@@ -1252,7 +1252,7 @@ print_insn_thumb (pc, info, given)
           if (!*c) /* Check for empty (not NULL) assembler string.  */
             {
 	      long offset;
-	      
+	     
 	      info->bytes_per_chunk = 4;
 	      info->bytes_per_line  = 4;
 
@@ -1274,16 +1274,16 @@ print_insn_thumb (pc, info, given)
             {
 	      info->bytes_per_chunk = 2;
 	      info->bytes_per_line  = 4;
-	  	      
+	  	     
               given &= 0xffff;
-	      
+	     
               for (; *c; c++)
                 {
                   if (*c == '%')
                     {
                       int domaskpc = 0;
                       int domasklr = 0;
-		      
+		     
                       switch (*++c)
                         {
                         case '%':
@@ -1293,11 +1293,11 @@ print_insn_thumb (pc, info, given)
                         case 'S':
                           {
                             long reg;
-			    
+			   
                             reg = (given >> 3) & 0x7;
                             if (given & (1 << 6))
                               reg += 8;
-			    
+			   
                             func (stream, "%s", arm_regnames[reg]);
                           }
                           break;
@@ -1305,11 +1305,11 @@ print_insn_thumb (pc, info, given)
                         case 'D':
                           {
                             long reg;
-			    
+			   
                             reg = given & 0x7;
                             if (given & (1 << 7))
                              reg += 8;
-			    
+			   
                             func (stream, "%s", arm_regnames[reg]);
                           }
                           break;
@@ -1331,9 +1331,9 @@ print_insn_thumb (pc, info, given)
                           {
                             int started = 0;
                             int reg;
-			    
+			   
                             func (stream, "{");
-			    
+			   
                             /* It would be nice if we could spot
                                ranges, and generate the rS-rE format: */
                             for (reg = 0; (reg < 8); reg++)
@@ -1365,12 +1365,12 @@ print_insn_thumb (pc, info, given)
                           break;
 
 
-                        case '0': case '1': case '2': case '3': case '4': 
+                        case '0': case '1': case '2': case '3': case '4':
                         case '5': case '6': case '7': case '8': case '9':
                           {
                             int bitstart = *c++ - '0';
                             int bitend = 0;
-			    
+			   
                             while (*c >= '0' && *c <= '9')
                               bitstart = (bitstart * 10) + *c++ - '0';
 
@@ -1379,7 +1379,7 @@ print_insn_thumb (pc, info, given)
                               case '-':
                                 {
                                   long reg;
-				  
+				 
                                   c++;
                                   while (*c >= '0' && *c <= '9')
                                     bitend = (bitend * 10) + *c++ - '0';
@@ -1478,11 +1478,11 @@ parse_arm_disassembler_option (option)
 {
   if (option == NULL)
     return;
-      
+     
   if (strneq (option, "reg-names-", 10))
     {
       int i;
-	
+
       option += 10;
 
       for (i = NUM_ARM_REGNAMES; i--;)
@@ -1491,7 +1491,7 @@ parse_arm_disassembler_option (option)
 	    regname_selected = i;
 	    break;
 	  }
-      
+     
       if (i < 0)
 	fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
     }
@@ -1501,7 +1501,7 @@ parse_arm_disassembler_option (option)
     force_thumb = 0;
   else
     fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
-  
+ 
   return;
 }
 
@@ -1512,7 +1512,7 @@ parse_disassembler_options (options)
      char * options;
 {
   char * space;
-  
+ 
   if (options == NULL)
     return;
 
@@ -1550,25 +1550,25 @@ print_insn_arm (pc, info)
   if (info->disassembler_options)
     {
       parse_disassembler_options (info->disassembler_options);
-      
+     
       /* To avoid repeated parsing of these options, we remove them here.  */
       info->disassembler_options = NULL;
     }
-  
+ 
   is_thumb = force_thumb;
   if (pc & 1)
     {
       is_thumb = 1;
       pc &= ~(bfd_vma) 1;
     }
-  
+ 
 #if 0
   if (!is_thumb && info->symbols != NULL)
     {
       if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
 	{
 	  coff_symbol_type * cs;
-	  
+	 
 	  cs = coffsymbol (*info->symbols);
 	  is_thumb = (   cs->native->u.syment.n_sclass == C_THUMBEXT
 		      || cs->native->u.syment.n_sclass == C_THUMBSTAT
@@ -1580,15 +1580,15 @@ print_insn_arm (pc, info)
 	{
 	  elf_symbol_type *  es;
 	  unsigned int       type;
-	  
+	 
 	  es = *(elf_symbol_type **)(info->symbols);
 	  type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
-	  
+	 
 	  is_thumb = (type == STT_ARM_TFUNC) || (type == STT_ARM_16BIT);
 	}
     }
 #endif
-  
+ 
   little = (info->endian == BFD_ENDIAN_LITTLE);
   info->bytes_per_chunk = 4;
   info->display_endian  = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
@@ -1599,17 +1599,17 @@ print_insn_arm (pc, info)
       if (status != 0 && is_thumb)
 	{
 	  info->bytes_per_chunk = 2;
-	  
+	 
 	  status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
 	  b[3] = b[2] = 0;
 	}
-      
+     
       if (status != 0)
 	{
 	  info->memory_error_func (status, pc, info);
 	  return -1;
 	}
-      
+     
       given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
     }
   else
@@ -1621,13 +1621,13 @@ print_insn_arm (pc, info)
 	  info->memory_error_func (status, pc, info);
 	  return -1;
 	}
-      
+     
       if (is_thumb)
 	{
 	  if (pc & 0x2)
 	    {
 	      given = (b[2] << 8) | b[3];
-	      
+	     
 	      status = info->read_memory_func
 		((pc + 4) & ~ 0x3, (bfd_byte *) b, 4, info);
 	      if (status != 0)
@@ -1635,7 +1635,7 @@ print_insn_arm (pc, info)
 		  info->memory_error_func (status, pc + 4, info);
 		  return -1;
 		}
-	      
+	     
 	      given |= (b[0] << 24) | (b[1] << 16);
 	    }
 	  else
@@ -1644,7 +1644,7 @@ print_insn_arm (pc, info)
       else
 	given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]);
     }
-  
+ 
   if (info->flags & INSN_HAS_RELOC)
     /* If the instruction has a reloc associated with it, then
        the offset field in the instruction will actually be the
@@ -1668,7 +1668,7 @@ print_arm_disassembler_options (FILE * stream)
   fprintf (stream, _("\n\
 The following ARM specific disassembler options are supported for use with\n\
 the -M switch:\n"));
-  
+ 
   for (i = NUM_ARM_REGNAMES; i--;)
     fprintf (stream, "  reg-names-%s %*c%s\n",
 	     regnames[i].name,
