Archipelago » qemu

/*

 *  APIC support

 *  Copyright (c) 2004-2005 Fabrice Bellard

 *

 * This library is free software; you can redistribute it and/or

    }\

}

                             uint8_t delivery_mode,

                             uint8_t vector_num, uint8_t polarity,

                             uint8_t trigger_mode)

        case APIC_DM_INIT:

            /* normal INIT IPI sent to processors */

                         apic_init_ipi(apic_iter) );

            return;

        case APIC_DM_EXTINT:

            /* handled in I/O APIC code */

            break;

            return;

    }

                 apic_set_irq(apic_iter, vector_num, trigger_mode) );

}

#ifdef DEBUG_APIC

    printf("cpu_set_apic_base: %016" PRIx64 "\n", val);

#endif

        (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));

    /* if disabled, cannot be enabled again */

    if (!(val & MSR_IA32_APICBASE_ENABLE)) {

    if (!(env->hflags & HF_HALTED_MASK))

        return;

    env->eip = 0;

                           0xffff, 0);

    env->hflags &= ~HF_HALTED_MASK;

}

                int trig_mode = (s->icr[0] >> 15) & 1;

                int level = (s->icr[0] >> 14) & 1;

                if (level == 0 && trig_mode == 1) {

                                 apic_iter->arb_id = apic_iter->id );

                    return;

                }

            break;

        case APIC_DM_SIPI:

                         apic_startup(apic_iter, vector_num) );

            return;

    }

        return -1;

    if (!(s->spurious_vec & APIC_SV_ENABLE))

        return -1;

    /* XXX: spurious IRQ handling */

    intno = get_highest_priority_int(s->irr);

    if (intno < 0)

{

    int64_t d;

    uint32_t val;

        s->count_shift;

    if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {

        /* periodic */

static void apic_timer_update(APICState *s, int64_t current_time)

{

    int64_t next_time, d;

    if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {

            s->count_shift;

        if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {

            d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);

    s->id = last_apic_id++;

    env->cpuid_apic_id = s->id;

    s->cpu_env = env;

        (s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE;

    /* XXX: mapping more APICs at the same memory location */

    if (apic_io_memory == 0) {

        /* NOTE: the APIC is directly connected to the CPU - it is not

           on the global memory bus. */

                                                apic_mem_write, NULL);

        cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,

                                     apic_io_memory);

    register_savevm("apic", s->id, 2, apic_save, apic_load, s);

    qemu_register_reset(apic_reset, s);

    local_apics[s->id] = s;

    return 0;

}

                    vector = pic_read_irq(isa_pic);

                else

                    vector = entry & 0xff;

                apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);

                                 vector, polarity, trig_mode);

            }

        }

    ioapic_reset(s);

    s->id = last_apic_id++;

                                       ioapic_mem_write, s);

    cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);

    register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);

    qemu_register_reset(ioapic_reset, s);

    return s;

}