Revision 5fafdf24 hw/apic.c

b/hw/apic.c
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/*
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 *  APIC support
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 * 
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 *
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 *  Copyright (c) 2004-2005 Fabrice Bellard
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 *
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 * This library is free software; you can redistribute it and/or
......
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    }\
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}
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static void apic_bus_deliver(const uint32_t *deliver_bitmask, 
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static void apic_bus_deliver(const uint32_t *deliver_bitmask,
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                             uint8_t delivery_mode,
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                             uint8_t vector_num, uint8_t polarity,
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                             uint8_t trigger_mode)
......
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        case APIC_DM_INIT:
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            /* normal INIT IPI sent to processors */
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            foreach_apic(apic_iter, deliver_bitmask, 
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            foreach_apic(apic_iter, deliver_bitmask,
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                         apic_init_ipi(apic_iter) );
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            return;
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        case APIC_DM_EXTINT:
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            /* handled in I/O APIC code */
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            break;
......
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            return;
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    }
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    foreach_apic(apic_iter, deliver_bitmask, 
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    foreach_apic(apic_iter, deliver_bitmask,
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                 apic_set_irq(apic_iter, vector_num, trigger_mode) );
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}
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......
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#ifdef DEBUG_APIC
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    printf("cpu_set_apic_base: %016" PRIx64 "\n", val);
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#endif
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    s->apicbase = (val & 0xfffff000) | 
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    s->apicbase = (val & 0xfffff000) |
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        (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
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    /* if disabled, cannot be enabled again */
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    if (!(val & MSR_IA32_APICBASE_ENABLE)) {
......
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    if (!(env->hflags & HF_HALTED_MASK))
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        return;
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    env->eip = 0;
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    cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12, 
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    cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
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                           0xffff, 0);
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    env->hflags &= ~HF_HALTED_MASK;
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}
......
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                int trig_mode = (s->icr[0] >> 15) & 1;
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                int level = (s->icr[0] >> 14) & 1;
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                if (level == 0 && trig_mode == 1) {
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                    foreach_apic(apic_iter, deliver_bitmask, 
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                    foreach_apic(apic_iter, deliver_bitmask,
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                                 apic_iter->arb_id = apic_iter->id );
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                    return;
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                }
......
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            break;
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        case APIC_DM_SIPI:
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            foreach_apic(apic_iter, deliver_bitmask, 
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            foreach_apic(apic_iter, deliver_bitmask,
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                         apic_startup(apic_iter, vector_num) );
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            return;
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    }
......
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        return -1;
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    if (!(s->spurious_vec & APIC_SV_ENABLE))
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        return -1;
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    /* XXX: spurious IRQ handling */
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    intno = get_highest_priority_int(s->irr);
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    if (intno < 0)
......
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{
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    int64_t d;
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    uint32_t val;
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    d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >> 
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    d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
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        s->count_shift;
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    if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
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        /* periodic */
......
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static void apic_timer_update(APICState *s, int64_t current_time)
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{
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    int64_t next_time, d;
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    if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
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        d = (current_time - s->initial_count_load_time) >> 
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        d = (current_time - s->initial_count_load_time) >>
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            s->count_shift;
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        if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
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            d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
......
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    s->id = last_apic_id++;
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    env->cpuid_apic_id = s->id;
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    s->cpu_env = env;
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    s->apicbase = 0xfee00000 | 
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    s->apicbase = 0xfee00000 |
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        (s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE;
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    /* XXX: mapping more APICs at the same memory location */
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    if (apic_io_memory == 0) {
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        /* NOTE: the APIC is directly connected to the CPU - it is not
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           on the global memory bus. */
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        apic_io_memory = cpu_register_io_memory(0, apic_mem_read, 
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        apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
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                                                apic_mem_write, NULL);
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        cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
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                                     apic_io_memory);
......
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    register_savevm("apic", s->id, 2, apic_save, apic_load, s);
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    qemu_register_reset(apic_reset, s);
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    local_apics[s->id] = s;
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    return 0;
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}
......
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                    vector = pic_read_irq(isa_pic);
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                else
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                    vector = entry & 0xff;
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                apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
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                apic_bus_deliver(deliver_bitmask, delivery_mode, 
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                apic_bus_deliver(deliver_bitmask, delivery_mode,
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                                 vector, polarity, trig_mode);
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            }
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        }
......
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    ioapic_reset(s);
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    s->id = last_apic_id++;
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    io_memory = cpu_register_io_memory(0, ioapic_mem_read, 
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    io_memory = cpu_register_io_memory(0, ioapic_mem_read,
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                                       ioapic_mem_write, s);
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    cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
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    register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);
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    qemu_register_reset(ioapic_reset, s);
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    return s;
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}

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