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/*

 * QEMU Cirrus CLGD 54xx VGA Emulator.

 * Copyright (c) 2004 Fabrice Bellard

 * Copyright (c) 2004 Makoto Suzuki (suzu)

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

} PCICirrusVGAState;

static uint8_t rop_to_index[256];

/***************************************

 *

 *  prototypes.

        s->cirrus_blt_fgcol = le16_to_cpu(color);

        break;

    case 3:

            (s->gr[0x11] << 8) | (s->gr[0x13] << 16);

        break;

    default:

        s->cirrus_blt_bgcol = le16_to_cpu(color);

        break;

    case 3:

            (s->gr[0x10] << 8) | (s->gr[0x12] << 16);

        break;

    default:

    dst = s->vram_ptr + s->cirrus_blt_dstaddr;

    (*s->cirrus_rop) (s, dst, src,

                      s->cirrus_blt_width, s->cirrus_blt_height);

    cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,

                             s->cirrus_blt_dstpitch, s->cirrus_blt_width,

    cirrus_fill_t rop_func;

    rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];

             s->cirrus_blt_dstpitch,

             s->cirrus_blt_width, s->cirrus_blt_height);

    cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,

static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)

{

    return cirrus_bitblt_common_patterncopy(s,

                                            (s->cirrus_blt_srcaddr & ~7));

}

{

    int copy_count;

    uint8_t *end_ptr;

    if (s->cirrus_srccounter > 0) {

        if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {

            cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);

    } else {

	if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {

            w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;

                s->cirrus_blt_srcpitch = ((w + 31) >> 5);

            else

                s->cirrus_blt_srcpitch = ((w + 7) >> 3);

#ifdef DEBUG_BITBLT

    printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",

           s->cirrus_blt_mode,

           s->cirrus_blt_modeext,

           s->cirrus_blt_width,

    }

    if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&

                               CIRRUS_BLTMODE_TRANSPARENTCOMP |

         (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {

        cirrus_bitblt_fgcol(s);

        cirrus_bitblt_solidfill(s, blt_rop);

    } else {

            CIRRUS_BLTMODE_COLOREXPAND) {

            if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {

 *

 ***************************************/

                               uint32_t *pline_offset,

                               uint32_t *pstart_addr,

                               uint32_t *pline_compare)

	| ((s->cr[0x1d] & 0x80) << 12);

    *pstart_addr = start_addr;

        ((s->cr[0x07] & 0x10) << 4) |

        ((s->cr[0x09] & 0x40) << 3);

    *pline_compare = line_compare;

static void cirrus_get_resolution(VGAState *s, int *pwidth, int *pheight)

{

    int width, height;

    width = (s->cr[0x01] + 1) * 8;

        ((s->cr[0x07] & 0x40) << 3);

    height = (height + 1);

    /* interlace support */

    return v;

}

                                  uint32_t mem_value)

{

    CirrusVGAState *s = opaque;

static inline void invalidate_cursor1(CirrusVGAState *s)

{

    if (s->last_hw_cursor_size) {

                                 s->last_hw_cursor_y + s->last_hw_cursor_y_start,

                                 s->last_hw_cursor_y + s->last_hw_cursor_y_end);

    }

        s->last_hw_cursor_y != s->hw_cursor_y) {

        invalidate_cursor1(s);

        s->last_hw_cursor_size = size;

        s->last_hw_cursor_x = s->hw_cursor_x;

        s->last_hw_cursor_y = s->hw_cursor_y;

    unsigned int color0, color1;

    const uint8_t *palette, *src;

    uint32_t content;

        return;

    /* fast test to see if the cursor intersects with the scan line */

    if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {

    if (scr_y < s->hw_cursor_y ||

        scr_y >= (s->hw_cursor_y + h))

        return;

    src = s->vram_ptr + s->real_vram_size - 16 * 1024;

    if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {

        src += (s->sr[0x13] & 0x3c) * 256;

        x2 = s->last_scr_width;

    w = x2 - x1;

    palette = s->cirrus_hidden_palette;

                             c6_to_8(palette[0x0 * 3 + 2]));

                             c6_to_8(palette[0xf * 3 + 2]));

    bpp = ((s->ds->depth + 7) >> 3);

    d1 += x1 * bpp;

    addr &= s->cirrus_addr_mask;

        ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {

	/* memory-mapped I/O */

	ret = cirrus_mmio_blt_read(s, addr & 0xff);

    unsigned mode;

    addr &= s->cirrus_addr_mask;

        ((addr & s->linear_mmio_mask) ==  s->linear_mmio_mask)) {

	/* memory-mapped I/O */

	cirrus_mmio_blt_write(s, addr & 0xff, val);

	} else if (s->gr[0x0B] & 0x02) {

            goto generic_io;

        }

	mode = s->gr[0x05] & 0x7;

	if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {

            s->cirrus_linear_write[0] = cirrus_linear_mem_writeb;

    register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);

    register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);

                                           cirrus_vga_mem_write, s);

                                 vga_io_memory);

    s->sr[0x06] = 0x0f;

    } else {

        s->sr[0x1F] = 0x22;		// MemClock

        s->sr[0x0F] = CIRRUS_MEMSIZE_2M;

            s->sr[0x17] = CIRRUS_BUSTYPE_PCI;

        else

            s->sr[0x17] = CIRRUS_BUSTYPE_ISA;

 *

 ***************************************/

                         unsigned long vga_ram_offset, int vga_ram_size)

{

    CirrusVGAState *s;

    s = qemu_mallocz(sizeof(CirrusVGAState));

                    ds, vga_ram_base, vga_ram_offset, vga_ram_size);

    cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);

    /* XXX ISA-LFB support */

				 s->cirrus_mmio_io_addr);

}

                         unsigned long vga_ram_offset, int vga_ram_size)

{

    PCICirrusVGAState *d;

    uint8_t *pci_conf;

    CirrusVGAState *s;

    int device_id;

    device_id = CIRRUS_ID_CLGD5446;

    /* setup PCI configuration registers */

                                                 -1, NULL, NULL);

    pci_conf = d->dev.config;

    pci_conf[0x00] = (uint8_t) (PCI_VENDOR_CIRRUS & 0xff);

    /* setup VGA */

    s = &d->cirrus_vga;

                    ds, vga_ram_base, vga_ram_offset, vga_ram_size);

    cirrus_init_common(s, device_id, 1);