Revision 5fafdf24 hw/gt64xxx.c

b/hw/gt64xxx.c
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 * QEMU GT64120 PCI host
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 *
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 * Copyright (c) 2006,2007 Aurelien Jarno
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 * 
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
......
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    /* Update IO mapping */
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    if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD])
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    {
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      /* Unmap old IO address */	    
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      /* Unmap old IO address */	   
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      if (s->PCI0IO_length)
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      {
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        cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED);	     
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        cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED);	    
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      }
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      /* Map new IO address */
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      s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
......
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    case GT_CPUERR_DATAHI:
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    case GT_CPUERR_PARITY:
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        /* Emulated memory has no error, always return the initial
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           values */ 
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           values */
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        val = s->regs[saddr];
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        break;
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......
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        /* Reading those register should empty all FIFO on the PCI
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           bus, which are not emulated. The return value should be
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           a random value that should be ignored. */
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        val = 0xc000ffee; 
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        val = 0xc000ffee;
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        break;
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    /* ECC */
......
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    case GT_ECC_CALC:
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    case GT_ECC_ERRADDR:
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        /* Emulated memory has no error, always return the initial
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           values */ 
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           values */
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        val = s->regs[saddr];
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        break;
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......
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        val = s->regs[saddr];
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        break;
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    case GT_PCI0_IACK:
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        /* Read the IRQ number */ 
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        /* Read the IRQ number */
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        val = pic_read_irq(isa_pic);
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        break;
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