Revision 5fafdf24 hw/ne2000.c
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/* |
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* QEMU NE2000 emulation |
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*
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* |
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* Copyright (c) 2003-2004 Fabrice Bellard |
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*
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* |
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* Permission is hereby granted, free of charge, to any person obtaining a copy |
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* of this software and associated documentation files (the "Software"), to deal |
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* in the Software without restriction, including without limitation the rights |
| ... | ... | |
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static int ne2000_can_receive(void *opaque) |
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{
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NE2000State *s = opaque; |
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if (s->cmd & E8390_STOP) |
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return 1; |
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return !ne2000_buffer_full(s); |
| ... | ... | |
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uint8_t *p; |
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unsigned int total_len, next, avail, len, index, mcast_idx; |
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uint8_t buf1[60]; |
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static const uint8_t broadcast_macaddr[6] =
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static const uint8_t broadcast_macaddr[6] = |
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{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
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#if defined(DEBUG_NE2000) |
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printf("NE2000: received len=%d\n", size);
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#endif |
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if (s->cmd & E8390_STOP || ne2000_buffer_full(s)) |
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return; |
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/* XXX: check this */ |
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if (s->rxcr & 0x10) {
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/* promiscuous: receive all */ |
| ... | ... | |
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if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) |
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return; |
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} else if (s->mem[0] == buf[0] && |
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s->mem[2] == buf[1] &&
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s->mem[4] == buf[2] &&
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s->mem[6] == buf[3] &&
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s->mem[8] == buf[4] &&
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s->mem[2] == buf[1] && |
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s->mem[4] == buf[2] && |
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s->mem[6] == buf[3] && |
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s->mem[8] == buf[4] && |
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s->mem[10] == buf[5]) {
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/* match */ |
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} else {
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| ... | ... | |
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} |
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if (val & E8390_TRANS) {
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index = (s->tpsr << 8); |
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/* XXX: next 2 lines are a hack to make netware 3.11 work */
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/* XXX: next 2 lines are a hack to make netware 3.11 work */ |
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if (index >= NE2000_PMEM_END) |
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index -= NE2000_PMEM_SIZE; |
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/* fail safe: check range on the transmitted length */ |
| ... | ... | |
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/* signal end of transfer */ |
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s->tsr = ENTSR_PTX; |
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s->isr |= ENISR_TX; |
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s->cmd &= ~E8390_TRANS;
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s->cmd &= ~E8390_TRANS; |
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ne2000_update_irq(s); |
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} |
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} |
| ... | ... | |
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return ret; |
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} |
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static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr,
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static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr, |
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uint32_t val) |
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{
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if (addr < 32 ||
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if (addr < 32 || |
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(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
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s->mem[addr] = val; |
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} |
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} |
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static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr,
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static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr, |
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uint32_t val) |
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{
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addr &= ~1; /* XXX: check exact behaviour if not even */ |
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if (addr < 32 ||
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if (addr < 32 || |
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(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
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*(uint16_t *)(s->mem + addr) = cpu_to_le16(val); |
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} |
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} |
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static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr,
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static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr, |
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uint32_t val) |
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{
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addr &= ~1; /* XXX: check exact behaviour if not even */ |
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if (addr < 32 ||
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if (addr < 32 || |
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(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
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cpu_to_le32wu((uint32_t *)(s->mem + addr), val); |
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} |
| ... | ... | |
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static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr) |
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{
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if (addr < 32 ||
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if (addr < 32 || |
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(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
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return s->mem[addr]; |
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} else {
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| ... | ... | |
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static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr) |
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{
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addr &= ~1; /* XXX: check exact behaviour if not even */ |
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if (addr < 32 ||
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if (addr < 32 || |
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(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
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return le16_to_cpu(*(uint16_t *)(s->mem + addr)); |
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} else {
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| ... | ... | |
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static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr) |
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{
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addr &= ~1; /* XXX: check exact behaviour if not even */ |
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if (addr < 32 ||
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if (addr < 32 || |
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(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
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return le32_to_cpupu((uint32_t *)(s->mem + addr)); |
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} else {
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| ... | ... | |
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void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd) |
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{
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NE2000State *s; |
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s = qemu_mallocz(sizeof(NE2000State)); |
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if (!s) |
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return; |
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register_ioport_write(base, 16, 1, ne2000_ioport_write, s); |
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register_ioport_read(base, 16, 1, ne2000_ioport_read, s); |
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|
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s->macaddr[3], |
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s->macaddr[4], |
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s->macaddr[5]); |
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register_savevm("ne2000", 0, 2, ne2000_save, ne2000_load, s);
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} |
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|
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NE2000State ne2000; |
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} PCINE2000State; |
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static void ne2000_map(PCIDevice *pci_dev, int region_num,
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static void ne2000_map(PCIDevice *pci_dev, int region_num, |
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uint32_t addr, uint32_t size, int type) |
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{
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PCINE2000State *d = (PCINE2000State *)pci_dev; |
| ... | ... | |
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PCINE2000State *d; |
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NE2000State *s; |
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uint8_t *pci_conf; |
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d = (PCINE2000State *)pci_register_device(bus, |
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"NE2000", sizeof(PCINE2000State), |
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devfn,
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devfn, |
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NULL, NULL); |
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pci_conf = d->dev.config; |
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pci_conf[0x00] = 0xec; // Realtek 8029 |
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pci_conf[0x01] = 0x10; |
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pci_conf[0x02] = 0x29; |
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pci_conf[0x03] = 0x80; |
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pci_conf[0x0a] = 0x00; // ethernet network controller
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pci_conf[0x0a] = 0x00; // ethernet network controller |
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pci_conf[0x0b] = 0x02; |
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pci_conf[0x0e] = 0x00; // header_type |
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pci_conf[0x3d] = 1; // interrupt pin 0 |
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pci_register_io_region(&d->dev, 0, 0x100,
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pci_register_io_region(&d->dev, 0, 0x100, |
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PCI_ADDRESS_SPACE_IO, ne2000_map); |
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s = &d->ne2000; |
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s->irq = d->dev.irq[0]; |
| ... | ... | |
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s->macaddr[3], |
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s->macaddr[4], |
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s->macaddr[5]); |
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/* XXX: instance number ? */ |
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register_savevm("ne2000", 0, 3, ne2000_save, ne2000_load, s);
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} |
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