Revision 5fafdf24 hw/openpic.c

b/hw/openpic.c
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/*
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 * OpenPIC emulation
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 * 
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 *
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 * Copyright (c) 2004 Jocelyn Mayer
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 * 
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
......
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 * - Motorola Harrier programmer manuel
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 *
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 * Serial interrupts, as implemented in Raven chipset are not supported yet.
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 * 
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 *
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 */
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#include "vl.h"
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......
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    priority = -1;
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    for (i = 0; i < MAX_IRQ; i++) {
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	if (IRQ_testbit(q, i)) {
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            DPRINTF("IRQ_check: irq %d set ipvp_pr=%d pr=%d\n", 
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            DPRINTF("IRQ_check: irq %d set ipvp_pr=%d pr=%d\n",
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                    i, IPVP_PRIORITY(opp->src[i].ipvp), priority);
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	    if (IPVP_PRIORITY(opp->src[i].ipvp) > priority) {
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		next = i;
......
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    IRQ_src_t *src;
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    src = &opp->src[n_IRQ];
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    DPRINTF("openpic: set irq %d = %d ipvp=%08x\n", 
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    DPRINTF("openpic: set irq %d = %d ipvp=%08x\n",
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            n_IRQ, level, src->ipvp);
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    if (test_bit(&src->ipvp, IPVP_SENSE)) {
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        /* level-sensitive irq */
......
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        /* NOTE: not fully accurate for special IRQs, but simple and
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           sufficient */
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        /* ACTIVITY bit is read-only */
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	opp->src[n_IRQ].ipvp = 
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	opp->src[n_IRQ].ipvp =
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            (opp->src[n_IRQ].ipvp & 0x40000000) |
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            (val & 0x800F00FF);
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        openpic_update_irq(opp, n_IRQ);
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        DPRINTF("Set IPVP %d to 0x%08x -> 0x%08x\n", 
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        DPRINTF("Set IPVP %d to 0x%08x -> 0x%08x\n",
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                n_IRQ, val, opp->src[n_IRQ].ipvp);
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	break;
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    case IRQ_IDE:
......
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    return retval;
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}
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static void write_doorbell_register (penpic_t *opp, int n_dbl,
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				     uint32_t offset, uint32_t value)
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{
......
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    IRQ_dst_t *dst;
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    uint32_t retval;
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    int idx, n_IRQ;
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    DPRINTF("%s: addr %08x\n", __func__, addr);
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    retval = 0xFFFFFFFF;
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    if (addr & 0xF)
......
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    &openpic_readl,
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};
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static void openpic_map(PCIDevice *pci_dev, int region_num, 
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static void openpic_map(PCIDevice *pci_dev, int region_num,
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                        uint32_t addr, uint32_t size, int type)
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{
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    openpic_t *opp;
......
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    openpic_t *opp;
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    uint8_t *pci_conf;
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    int i, m;
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    /* XXX: for now, only one CPU is supported */
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    if (nb_cpus != 1)
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        return NULL;
......
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        pci_conf[0x0b] = 0x08;
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        pci_conf[0x0e] = 0x00; // header_type
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        pci_conf[0x3d] = 0x00; // no interrupt pin
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        /* Register I/O spaces */
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        pci_register_io_region((PCIDevice *)opp, 0, 0x40000,
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                               PCI_ADDRESS_SPACE_MEM, &openpic_map);
......
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    }
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    opp->mem_index = cpu_register_io_memory(0, openpic_read,
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                                            openpic_write, opp);
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    //    isu_base &= 0xFFFC0000;
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    opp->nb_cpus = nb_cpus;
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    /* Set IRQ types */

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