Archipelago » qemu

 * QEMU PCI bus manager

 *

 * Copyright (c) 2004 Fabrice Bellard

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

}

/* -1 for devfn means auto assign */

                               int instance_size, int devfn,

                               PCIConfigWriteFunc *config_write)

{

    PCIDevice *pci_dev;

    if (pci_irq_index >= PCI_DEVICES_MAX)

        return NULL;

    if (devfn < 0) {

        for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {

            if (!bus->devices[devfn])

    return pci_dev;

}

                            PCIMapIORegionFunc *map_func)

{

    PCIIORegion *r;

    PCIIORegion *r;

    int cmd, i;

    uint32_t last_addr, new_addr, config_ofs;

    cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));

    for(i = 0; i < PCI_NUM_REGIONS; i++) {

        r = &d->io_regions[i];

        if (r->size != 0) {

            if (r->type & PCI_ADDRESS_SPACE_IO) {

                if (cmd & PCI_COMMAND_IO) {

                                                         config_ofs));

                    new_addr = new_addr & ~(r->size - 1);

                    last_addr = new_addr + r->size - 1;

                }

            } else {

                if (cmd & PCI_COMMAND_MEMORY) {

                                                         config_ofs));

                    /* the ROM slot has a specific enable bit */

                    if (i == PCI_ROM_SLOT && !(new_addr & 1))

                        }

                    } else {

                        cpu_register_physical_memory(pci_to_cpu_addr(r->addr),

                                                     IO_MEM_UNASSIGNED);

                    }

                }

    }

}

                                 uint32_t address, int len)

{

    uint32_t val;

    return val;

}

                              uint32_t address, uint32_t val, int len)

{

    int can_write, i;

    uint32_t end, addr;

                     (address >= 0x30 && address < 0x34))) {

        PCIIORegion *r;

        int reg;

    PCIBus *s = opaque;

    PCIDevice *pci_dev;

    int config_addr, bus_num;

#if defined(DEBUG_PCI) && 0

    printf("pci_data_write: addr=%08x val=%08x len=%d\n",

           addr, val, len);

    PCIDevice *pci_dev = (PCIDevice *)opaque;

    PCIBus *bus;

    int change;

    change = level - pci_dev->irq_state[irq_num];

    if (!change)

        return;

    const char *desc;

} pci_class_desc;

{

    { 0x0100, "SCSI controller"},

    { 0x0101, "IDE controller"},

        if (r->size != 0) {

            term_printf("      BAR%d: ", i);

            if (r->type & PCI_ADDRESS_SPACE_IO) {

                       r->addr, r->addr + r->size - 1);

            } else {

                       r->addr, r->addr + r->size - 1);

            }

        }

    PCIBus *bus = first_bus;

    PCIDevice *d;

    int devfn;

    while (bus && bus->bus_num != bus_num)

        bus = bus->next;

    if (bus) {

    PCIBus *bus;

} PCIBridge;

                             uint32_t address, uint32_t val, int len)

{

    PCIBridge *s = (PCIBridge *)d;

                        pci_map_irq_fn map_irq, const char *name)

{

    PCIBridge *s;

                                         devfn, NULL, pci_bridge_write_config);

    s->dev.config[0x00] = id >> 16;

    s->dev.config[0x01] = id >> 24;