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/*

 * QEMU AMD PC-Net II (Am79C970A) emulation

 * Copyright (c) 2004 Antony T Curtis

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */

/* This software was written to be compatible with the specification:

 * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet

 * AMD Publication# 19436  Rev:E  Amendment/0  Issue Date: June 2000

 */

/*

 * On Sparc32, this is the Lance (Am7990) part of chip STP2000 (Master I/O), also

 * produced as NCR89C100. See

static inline int padr_match(PCNetState *s, const uint8_t *buf, int size)

{

    struct qemu_ether_header *hdr = (void *)buf;

        s->csr[12] & 0xff, s->csr[12] >> 8,

        s->csr[13] & 0xff, s->csr[13] >> 8,

    };

    int result = (!CSR_DRCVPA(s)) && !memcmp(hdr->ether_dhost, padr, 6);

#ifdef PCNET_DEBUG_MATCH

static inline int ladr_match(PCNetState *s, const uint8_t *buf, int size)

{

    struct qemu_ether_header *hdr = (void *)buf;

        ((uint64_t *)&s->csr[8])[0] != 0LL) {

            s->csr[8] & 0xff, s->csr[8] >> 8,

            s->csr[9] & 0xff, s->csr[9] >> 8,

        };

        int index = lnc_mchash(hdr->ether_dhost) >> 26;

        return !!(ladr[index >> 3] & (1 << (index & 7)));

    return 0;

}

{

    while (idx < 1) idx += CSR_RCVRL(s);

    return s->rdra + ((CSR_RCVRL(s) - idx) * (BCR_SWSTYLE(s) ? 16 : 8));

static inline int64_t pcnet_get_next_poll_time(PCNetState *s, int64_t current_time)

{

                 ticks_per_sec, 33000000L);

    if (next_time <= current_time)

        next_time = current_time + 1;

    s->rdra = 0;

    s->tdra = 0;

    s->rap = 0;

    s->bcr[BCR_BSBC] &= ~0x0080;

    s->csr[0]   = 0x0004;

{

    int isr = 0;

    s->csr[0] &= ~0x0080;

#if 1

    if (((s->csr[0] & ~s->csr[3]) & 0x5f00) ||

        (((s->csr[4]>>1) & ~s->csr[4]) & 0x0115) ||

        (!!(s->csr[5] & 0x0008) && !!(s->csr[5] & 0x0010)) /* MPINT */)

#endif

    {

        isr = CSR_INEA(s);

        s->csr[0] |= 0x0080;

    }

    if (!!(s->csr[4] & 0x0080) && CSR_INEA(s)) { /* UINT */

        s->csr[4] &= ~0x0080;

        s->csr[4] |= 0x0040;

    }

#if 1

#else

    if ((!!(s->csr[5] & 0x0400) && !!(s->csr[5] & 0x0800)) /* SINT */ ||

        (!!(s->csr[5] & 0x0100) && !!(s->csr[5] & 0x0200)) /* SLPINT */ )

#ifdef PCNET_DEBUG

    printf("pcnet_init init_addr=0x%08x\n", PHYSADDR(s,CSR_IADR(s)));

#endif

    if (BCR_SSIZE32(s)) {

        struct pcnet_initblk32 initblk;

        s->phys_mem_read(s->dma_opaque, PHYSADDR(s,CSR_IADR(s)),

    CSR_XMTRC(s) = CSR_XMTRL(s);

#ifdef PCNET_DEBUG

        BCR_SSIZE32(s),

        s->rdra, CSR_RCVRL(s), s->tdra, CSR_XMTRL(s));

#endif

    s->csr[0] &= ~0x0004;       /* clear STOP bit */

}

    if (!CSR_DTX(s))

        s->csr[0] |= 0x0010;    /* set TXON */

    if (!CSR_DRX(s))

        s->csr[0] |= 0x0020;    /* set RXON */

        target_phys_addr_t nrda = pcnet_rdra_addr(s, -1 + CSR_RCVRC(s));

        target_phys_addr_t nnrd = pcnet_rdra_addr(s, -2 + CSR_RCVRC(s));

#else

            (CSR_RCVRL(s) - CSR_RCVRC(s)) *

            (BCR_SWSTYLE(s) ? 16 : 8 );

        int nrdc = CSR_RCVRC(s)<=1 ? CSR_RCVRL(s) : CSR_RCVRC(s)-1;

            (CSR_RCVRL(s) - nrdc) *

            (BCR_SWSTYLE(s) ? 16 : 8 );

        int nnrc = nrdc<=1 ? CSR_RCVRL(s) : nrdc-1;

            (CSR_RCVRL(s) - nnrc) *

            (BCR_SWSTYLE(s) ? 16 : 8 );

#endif

#endif

        }

    }

    if (CSR_CRDA(s)) {

        struct pcnet_RMD rmd;

        RMDLOAD(&rmd, PHYSADDR(s,CSR_CRDA(s)));

    } else {

        CSR_CRBC(s) = CSR_CRST(s) = 0;

    }

    if (CSR_NRDA(s)) {

        struct pcnet_RMD rmd;

        RMDLOAD(&rmd, PHYSADDR(s,CSR_NRDA(s)));

{

    s->csr[34] = s->csr[35] = 0;

    if (s->tdra) {

            (CSR_XMTRL(s) - CSR_XMTRC(s)) *

            (BCR_SWSTYLE(s) ? 16 : 8);

        int bad = 0;

    if (CSR_CXDA(s)) {

        struct pcnet_TMD tmd;

        CSR_CXBC(s) = GET_FIELD(tmd.length, TMDL, BCNT);

        CSR_CXST(s) = tmd.status;

    } else {

        CSR_CXBC(s) = CSR_CXST(s) = 0;

    }

    return !!(CSR_CXST(s) & 0x8000);

}

    PCNetState *s = opaque;

    if (CSR_STOP(s) || CSR_SPND(s))

        return 0;

    if (s->recv_pos > 0)

        return 0;

        size = MIN_BUF_SIZE;

    }

        || (is_bcast=padr_bcast(s, buf, size))

        || (is_ladr=ladr_match(s, buf, size))) {

                nrda = s->rdra +

                    (CSR_RCVRL(s) - rcvrc) *

                    (BCR_SWSTYLE(s) ? 16 : 8 );

                if (GET_FIELD(rmd.status, RMDS, OWN)) {

#ifdef PCNET_DEBUG_RMD

                                rcvrc, CSR_RCVRC(s));

#endif

                    CSR_RCVRC(s) = rcvrc;

            int pktcount = 0;

            memcpy(src, buf, size);

#if 1

            /* no need to compute the CRC */

            src[size] = 0;

                while (size < 46) {

                    src[size++] = 0;

                }

                while (p != &src[size]) {

                    CRC(fcs, *p++);

                }

                            PCNET_RECV_STORE();

                        }

                    }

            }

#undef PCNET_RECV_STORE

            s->csr[0] |= 0x0400;

#ifdef PCNET_DEBUG

                CSR_RCVRC(s), PHYSADDR(s,CSR_CRDA(s)), pktcount);

#endif

#ifdef PCNET_DEBUG_RMD

            PRINT_RMD(&rmd);

            while (pktcount--) {

                if (CSR_RCVRC(s) <= 1)

                    CSR_RCVRC(s) = CSR_RCVRL(s);

                else

            }

            pcnet_rdte_poll(s);

    }

    pcnet_poll(s);

}

static void pcnet_transmit(PCNetState *s)

    target_phys_addr_t xmit_cxda = 0;

    int count = CSR_XMTRL(s)-1;

    s->xmit_pos = -1;

    if (!CSR_TXON(s)) {

        s->csr[0] &= ~0x0008;

        return;

        if (count--)

            goto txagain;

    if (s->xmit_pos >= 0) {

        struct pcnet_TMD tmd;

        TMDLOAD(&tmd, PHYSADDR(s,xmit_cxda));

        pcnet_rdte_poll(s);

    }

        (CSR_TXON(s) && !CSR_DPOLL(s) && pcnet_tdte_poll(s)))

    {

        /* prevent recursion */

        pcnet_transmit(s);

    }

    if (!CSR_STOP(s) && !CSR_SPND(s) && !CSR_DPOLL(s)) {

        uint64_t now = qemu_get_clock(vm_clock) * 33;

            } else

                CSR_POLL(s) = t;

        }

            pcnet_get_next_poll_time(s,qemu_get_clock(vm_clock)));

    }

}

        if (!CSR_STRT(s) && (val & 2))

            pcnet_start(s);

            pcnet_transmit(s);

        return;

    case 3:

        break;

    case 4:

        val &= ~0x026a; val |= s->csr[4] & 0x026a;

        break;

    case 5:

        val &= ~0x0a90; val |= s->csr[5] & 0x0a90;

        break;

    case 16:

    PCNetState *s = opaque;

#ifdef PCNET_DEBUG

    printf("pcnet_aprom_writeb addr=0x%08x val=0x%02x\n", addr, val);

    /* Check APROMWE bit to enable write access */

    if (pcnet_bcr_readw(s,2) & 0x80)

        s->prom[addr & 15] = val;

static uint32_t pcnet_aprom_readb(void *opaque, uint32_t addr)

{

        pcnet_bcr_writew(s, BCR_BSBC, pcnet_bcr_readw(s, BCR_BSBC) | 0x0080);

#ifdef PCNET_DEBUG_IO

        printf("device switched into dword i/o mode\n");

    }

    pcnet_update_irq(s);

}

    PCNetState *s = opaque;

    uint32_t val = -1;

    pcnet_poll_timer(s);

        switch (addr & 0x0f) {

        case 0x00: /* RDP */

            val = pcnet_csr_readw(s, s->rap);

    return val;

}

                             uint32_t addr, uint32_t size, int type)

{

    PCNetState *d = (PCNetState *)pci_dev;

    register_ioport_write(addr, 16, 1, pcnet_aprom_writeb, d);

    register_ioport_read(addr, 16, 1, pcnet_aprom_readb, d);

    register_ioport_write(addr + 0x10, 0x10, 2, pcnet_ioport_writew, d);

    register_ioport_read(addr + 0x10, 0x10, 2, pcnet_ioport_readw, d);

    register_ioport_write(addr + 0x10, 0x10, 4, pcnet_ioport_writel, d);

        pcnet_aprom_writeb(d, addr & 0x0f, val);

}

{

    PCNetState *d = opaque;

    uint32_t val = -1;

    }

}

{

    PCNetState *d = opaque;

    uint32_t val = -1;

    }

}

{

    PCNetState *d = opaque;

    uint32_t val;

    (CPUReadMemoryFunc *)&pcnet_mmio_readl

};

                            uint32_t addr, uint32_t size, int type)

{

    PCNetState *d = (PCNetState *)pci_dev;

    uint8_t *pci_conf;

#if 0

        sizeof(struct pcnet_RMD), sizeof(struct pcnet_TMD));

#endif

    d = (PCNetState *)pci_register_device(bus, "PCNet", sizeof(PCNetState),

                                          devfn, NULL, NULL);

    pci_conf = d->dev.config;

    *(uint16_t *)&pci_conf[0x00] = cpu_to_le16(0x1022);

    *(uint16_t *)&pci_conf[0x06] = cpu_to_le16(0x0280);

    pci_conf[0x08] = 0x10;

    pci_conf[0x09] = 0x00;

    pci_conf[0x0b] = 0x02;

    pci_conf[0x0e] = 0x00; // header_type

    *(uint32_t *)&pci_conf[0x10] = cpu_to_le32(0x00000001);

    *(uint32_t *)&pci_conf[0x14] = cpu_to_le32(0x00000000);

    pci_conf[0x3d] = 1; // interrupt pin 0

    pci_conf[0x3e] = 0x06;

    pci_conf[0x3f] = 0xff;

    d->mmio_index =

      cpu_register_io_memory(0, pcnet_mmio_read, pcnet_mmio_write, d);

                           PCI_ADDRESS_SPACE_IO, pcnet_ioport_map);

                           PCI_ADDRESS_SPACE_MEM, pcnet_mmio_map);

    d->irq = d->dev.irq[0];

    d->phys_mem_read = pci_physical_memory_read;

    d->phys_mem_write = pci_physical_memory_write;