Revision 5fafdf24 hw/ppc_chrp.c

b/hw/ppc_chrp.c
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/*
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 * QEMU PPC CHRP/PMAC hardware System Emulator
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 * 
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 *
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 * Copyright (c) 2004-2007 Fabrice Bellard
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 * 
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
......
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    s = qemu_mallocz(sizeof(MacIONVRAMState));
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    if (!s)
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        return NULL;
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    macio_nvram_mem_index = cpu_register_io_memory(0, macio_nvram_read, 
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    macio_nvram_mem_index = cpu_register_io_memory(0, macio_nvram_read,
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                                                   macio_nvram_write, s);
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    return s;
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}
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static void macio_map(PCIDevice *pci_dev, int region_num, 
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static void macio_map(PCIDevice *pci_dev, int region_num,
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                      uint32_t addr, uint32_t size, int type)
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{
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    if (heathrow_pic_mem_index >= 0) {
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        cpu_register_physical_memory(addr + 0x00000, 0x1000, 
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        cpu_register_physical_memory(addr + 0x00000, 0x1000,
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                                     heathrow_pic_mem_index);
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    }
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    cpu_register_physical_memory(addr + 0x08000, 0x1000, dbdma_mem_index);
......
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    if (ide1_mem_index >= 0)
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        cpu_register_physical_memory(addr + 0x20000, 0x1000, ide1_mem_index);
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    if (openpic_mem_index >= 0) {
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        cpu_register_physical_memory(addr + 0x40000, 0x40000, 
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        cpu_register_physical_memory(addr + 0x40000, 0x40000,
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                                     openpic_mem_index);
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    }
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    if (macio_nvram_mem_index >= 0)
......
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    d->config[0x0e] = 0x00; // header_type
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    d->config[0x3d] = 0x01; // interrupt on pin 1
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    dbdma_mem_index = cpu_register_io_memory(0, dbdma_read, dbdma_write, NULL);
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    pci_register_io_region(d, 0, 0x80000, 
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    pci_register_io_region(d, 0, 0x80000,
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                           PCI_ADDRESS_SPACE_MEM, macio_map);
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}
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......
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{
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    static int vga_vbl_enabled;
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    int linesize;
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    //    printf("osi_call R5=%d\n", env->gpr[5]);
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    /* same handler as PearPC, coming from the original MOL video
......
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                break;
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            }
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        }
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        env->gpr[3] = 0; 
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        env->gpr[3] = 0;
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        env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
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        env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
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        env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */
......
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        break;
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    case 64: /* get color */
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        /* R6 = index */
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        env->gpr[3] = 0; 
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        env->gpr[3] = 0;
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        break;
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    case 116: /* set hwcursor */
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        /* R6 = x, R7 = y, R8 = visible, R9 = data */
......
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void pmac_format_nvram_partition(uint8_t *buf, int len)
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{
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    char partition_name[12] = "wwwwwwwwwwww";
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    buf[0] = 0x7f; /* free partition magic */
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    buf[1] = 0; /* checksum */
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    buf[2] = len >> 8;
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    buf[3] = len;
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    memcpy(buf + 4, partition_name, 12);
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    buf[1] = nvram_chksum(buf, 16);
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}    
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}   
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/* PowerPC CHRP hardware initialisation */
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static void ppc_chrp_init (int ram_size, int vga_ram_size, int boot_device,
......
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    bios_size = (bios_size + 0xfff) & ~0xfff;
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    cpu_register_physical_memory((uint32_t)(-bios_size),
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                                 bios_size, bios_offset | IO_MEM_ROM);
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    /* allocate and load VGA BIOS */
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    vga_bios_offset = bios_offset + bios_size;
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    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
......
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        phys_ram_base[vga_bios_offset + 1] = 'D';
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        phys_ram_base[vga_bios_offset + 2] = 'R';
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        phys_ram_base[vga_bios_offset + 3] = 'V';
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        cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4), 
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        cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4),
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                     vga_bios_size);
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        vga_bios_size += 8;
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    }
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    vga_bios_size = (vga_bios_size + 0xfff) & ~0xfff;
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    if (linux_boot) {
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        kernel_base = KERNEL_LOAD_ADDR;
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        /* now we can load the kernel */
......
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        /* XXX: suppress that */
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        dummy_irq = i8259_init(NULL);
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        /* XXX: use Mac Serial port */
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        serial_init(0x3f8, dummy_irq[4], serial_hds[0]);
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        for(i = 0; i < nb_nics; i++) {
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            if (!nd_table[i].model)
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                nd_table[i].model = "ne2k_pci";
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            pci_nic_init(pci_bus, &nd_table[i], -1);
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        }
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        pci_cmd646_ide_init(pci_bus, &bs_table[0], 0);
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        /* cuda also initialize ADB */
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        cuda_mem_index = cuda_init(pic[0x12]);
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        adb_kbd_init(&adb_bus);
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        adb_mouse_init(&adb_bus);
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        {
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            MacIONVRAMState *nvr;
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            nvr = macio_nvram_init();
......
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#endif
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        /* cuda also initialize ADB */
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        cuda_mem_index = cuda_init(pic[0x19]);
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        adb_kbd_init(&adb_bus);
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        adb_mouse_init(&adb_bus);
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        macio_init(pci_bus, 0x0022);
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        nvram = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
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        arch_name = "MAC99";
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    }
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......
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                  kernel_filename, kernel_cmdline,
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                  initrd_filename, cpu_model, 0);
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}
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static void ppc_heathrow_init (int ram_size, int vga_ram_size, int boot_device,
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                               DisplayState *ds, const char **fd_filename,
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                               int snapshot,

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