Revision 5fafdf24 hw/serial.c
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/* |
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* QEMU 16450 UART emulation |
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*
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* |
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* Copyright (c) 2003-2004 Fabrice Bellard |
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*
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* |
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* Permission is hereby granted, free of charge, to any person obtaining a copy |
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* of this software and associated documentation files (the "Software"), to deal |
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* in the Software without restriction, including without limitation the rights |
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} else { |
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parity = 'N'; |
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} |
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if (s->lcr & 0x04)
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if (s->lcr & 0x04) |
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stop_bits = 2; |
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else |
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stop_bits = 1; |
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ssp.stop_bits = stop_bits; |
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qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); |
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#if 0 |
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printf("speed=%d parity=%c data=%d stop=%d\n",
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printf("speed=%d parity=%c data=%d stop=%d\n", |
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speed, parity, data_bits, stop_bits); |
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#endif |
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} |
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{ |
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SerialState *s = opaque; |
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unsigned char ch; |
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addr &= 7; |
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#ifdef DEBUG_SERIAL |
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printf("serial: write addr=0x%02x val=0x%02x\n", addr, val); |
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break_enable = (val >> 6) & 1; |
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if (break_enable != s->last_break_enable) { |
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s->last_break_enable = break_enable; |
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qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
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qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK, |
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&break_enable); |
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} |
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} |
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default: |
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case 0: |
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if (s->lcr & UART_LCR_DLAB) { |
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ret = s->divider & 0xff;
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ret = s->divider & 0xff; |
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} else { |
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ret = s->rbr; |
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s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
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