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 * The license and distribution terms for this file may be

 * found in the file LICENSE in this distribution or at

 *  http://www.rtems.com/license/LICENSE.

 * @(#) sh7750_regs.h,v 1.2.4.1 2003/09/04 18:46:00 joel Exp

 */

#ifndef __SH7750_REGS_H__

#define __SH7750_REGS_H__

 * in 0x1f000000 - 0x1fffffff (area 7 address)

 */

					   priveleged mode */

#define SH7750_A7_BASE       0x1f000000	/* Accessable only using TLB */

#define SH7750_P4_REG32(ofs) (SH7750_P4_BASE + (ofs))

#define SH7750_A7_REG32(ofs) (SH7750_A7_BASE + (ofs))

 */

/* Page Table Entry High register - PTEH */

#define SH7750_PTEL_PR_RWPO   0x00000020	/*   read-write in priv mode */

#define SH7750_PTEL_PR_ROPU   0x00000040	/*   read-only in priv or user mode */

#define SH7750_PTEL_PR_RWPU   0x00000060	/*   read-write in priv or user mode */

						   (0 - page not cacheable) */

						   performed to a page) */

#define SH7750_PTEL_SH        0x00000002	/* Share Status bit (1 - page are

						   shared by processes) */

#define SH7750_CCR_A7         SH7750_A7_REG32(SH7750_CCR_REGOFS)

#define SH7750_CCR_IIX      0x00008000	/* IC index enable bit */

					   set it to clear IC */

#define SH7750_CCR_ICE      0x00000100	/* IC enable bit */

#define SH7750_CCR_OIX      0x00000080	/* OC index enable bit */

					   you should set ORA = 0 */

#define SH7750_CCR_OCI      0x00000008	/* OC invalidation bit */

#define SH7750_CCR_CB       0x00000004	/* Copy-back bit for P1 area */

/* Peripheral Module Interrupts - Memory Refresh Unit (REF) */

#define SH7750_EVT_REF_RCMI            0x580	/* Compare-match Interrupt */

						   interrupt */

/* Peripheral Module Interrupts - Hitachi User Debug Interface (H-UDI) */

#define SH7750_FRQCR          SH7750_P4_REG32(SH7750_FRQCR_REGOFS)

#define SH7750_FRQCR_A7       SH7750_A7_REG32(SH7750_FRQCR_REGOFS)

					   0 - CKIO pin goes to HiZ/pullup

					   1 - Clock is output from CKIO */

#define SH7750_FRQCR_PLL1EN   0x0400	/* PLL circuit 1 enable */

#define SH7750_BCR1_BREQEN    0x00080000	/* BREQ Enable:

						   0 - External requests are  not

						   accepted

						   accepted */

#define SH7750_BCR1_PSHR      0x00040000	/* Partial Sharing Bit:

						   0 - Master Mode

#define SH7750_MCR_TCAS_1     0x00000000	/*    1 */

#define SH7750_MCR_TCAS_2     0x00800000	/*    2 */

						   SDRAM: minimum number of cycles

						   until the next bank active cmd

						   is output after precharging */

#define SH7750_CHCR_DSA_AMEM16  0x0E000000	/* 16-bit attribute memory space */

#define SH7750_CHCR_DTC       0x01000000	/* Destination Address Wait Control

						   space wait control for PCMCIA

						   access */

						   Address Mode (External Addr

						   Space -> External Device) */

#define SH7750_CHCR_RS_ER_SA_ED_TO_EA   0x300	/* External Request, Single

						   Space) */

#define SH7750_CHCR_RS_AR_EA_TO_EA      0x400	/* Auto-Request (External Addr

						   Space -> External Addr Space) */

#define SH7750_CHCR_RS_AR_EA_TO_OCP     0x500	/* Auto-Request (External Addr

						   Space -> On-chip Peripheral

						   Module) */

						   Peripheral Module ->

						   External Addr Space */

#define SH7750_CHCR_RS_SCITX_EA_TO_SC   0x800	/* SCI Transmit-Data-Empty intr

#define SH7750_IPRC_HUDI_S    0

 * User Break Controller registers

 */

#define SH7750_BARA           0x200000	/* Break address regiser A */