Revision 5fafdf24 hw/sh7750_regs.h

b/hw/sh7750_regs.h
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 * The license and distribution terms for this file may be
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 * found in the file LICENSE in this distribution or at
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 *  http://www.rtems.com/license/LICENSE.
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 * 
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 *
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 * @(#) sh7750_regs.h,v 1.2.4.1 2003/09/04 18:46:00 joel Exp
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 */
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#ifndef __SH7750_REGS_H__
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#define __SH7750_REGS_H__
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/* 
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 * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address)  and 
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/*
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 * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address)  and
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 * in 0x1f000000 - 0x1fffffff (area 7 address)
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 */
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#define SH7750_P4_BASE       0xff000000	/* Accessable only in 
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#define SH7750_P4_BASE       0xff000000	/* Accessable only in
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					   priveleged mode */
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#define SH7750_A7_BASE       0x1f000000	/* Accessable only using TLB */
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#define SH7750_P4_REG32(ofs) (SH7750_P4_BASE + (ofs))
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#define SH7750_A7_REG32(ofs) (SH7750_A7_BASE + (ofs))
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/* 
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 * MMU Registers 
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/*
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 * MMU Registers
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 */
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/* Page Table Entry High register - PTEH */
......
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#define SH7750_PTEL_PR_RWPO   0x00000020	/*   read-write in priv mode */
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#define SH7750_PTEL_PR_ROPU   0x00000040	/*   read-only in priv or user mode */
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#define SH7750_PTEL_PR_RWPU   0x00000060	/*   read-write in priv or user mode */
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#define SH7750_PTEL_C         0x00000008	/* Cacheability 
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#define SH7750_PTEL_C         0x00000008	/* Cacheability
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						   (0 - page not cacheable) */
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#define SH7750_PTEL_D         0x00000004	/* Dirty bit (1 - write has been 
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#define SH7750_PTEL_D         0x00000004	/* Dirty bit (1 - write has been
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						   performed to a page) */
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#define SH7750_PTEL_SH        0x00000002	/* Share Status bit (1 - page are
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						   shared by processes) */
......
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#define SH7750_CCR_A7         SH7750_A7_REG32(SH7750_CCR_REGOFS)
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#define SH7750_CCR_IIX      0x00008000	/* IC index enable bit */
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#define SH7750_CCR_ICI      0x00000800	/* IC invalidation bit: 
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#define SH7750_CCR_ICI      0x00000800	/* IC invalidation bit:
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					   set it to clear IC */
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#define SH7750_CCR_ICE      0x00000100	/* IC enable bit */
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#define SH7750_CCR_OIX      0x00000080	/* OC index enable bit */
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#define SH7750_CCR_ORA      0x00000020	/* OC RAM enable bit 
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					   if you set OCE = 0, 
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#define SH7750_CCR_ORA      0x00000020	/* OC RAM enable bit
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					   if you set OCE = 0,
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					   you should set ORA = 0 */
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#define SH7750_CCR_OCI      0x00000008	/* OC invalidation bit */
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#define SH7750_CCR_CB       0x00000004	/* Copy-back bit for P1 area */
......
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/* Peripheral Module Interrupts - Memory Refresh Unit (REF) */
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#define SH7750_EVT_REF_RCMI            0x580	/* Compare-match Interrupt */
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#define SH7750_EVT_REF_ROVI            0x5A0	/* Refresh Counter Overflow 
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#define SH7750_EVT_REF_ROVI            0x5A0	/* Refresh Counter Overflow
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						   interrupt */
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/* Peripheral Module Interrupts - Hitachi User Debug Interface (H-UDI) */
......
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#define SH7750_FRQCR          SH7750_P4_REG32(SH7750_FRQCR_REGOFS)
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#define SH7750_FRQCR_A7       SH7750_A7_REG32(SH7750_FRQCR_REGOFS)
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#define SH7750_FRQCR_CKOEN    0x0800	/* Clock Output Enable 
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#define SH7750_FRQCR_CKOEN    0x0800	/* Clock Output Enable
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					   0 - CKIO pin goes to HiZ/pullup
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					   1 - Clock is output from CKIO */
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#define SH7750_FRQCR_PLL1EN   0x0400	/* PLL circuit 1 enable */
......
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#define SH7750_BCR1_BREQEN    0x00080000	/* BREQ Enable:
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						   0 - External requests are  not
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						   accepted
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						   1 - External requests are 
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						   1 - External requests are
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						   accepted */
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#define SH7750_BCR1_PSHR      0x00040000	/* Partial Sharing Bit:
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						   0 - Master Mode
......
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#define SH7750_MCR_TCAS_1     0x00000000	/*    1 */
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#define SH7750_MCR_TCAS_2     0x00800000	/*    2 */
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#define SH7750_MCR_TPC        0x00380000	/* DRAM: RAS Precharge Period 
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#define SH7750_MCR_TPC        0x00380000	/* DRAM: RAS Precharge Period
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						   SDRAM: minimum number of cycles
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						   until the next bank active cmd
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						   is output after precharging */
......
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#define SH7750_CHCR_DSA_AMEM16  0x0E000000	/* 16-bit attribute memory space */
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#define SH7750_CHCR_DTC       0x01000000	/* Destination Address Wait Control
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						   Select, specifies CS5 or CS6 
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						   Select, specifies CS5 or CS6
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						   space wait control for PCMCIA
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						   access */
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......
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						   Address Mode (External Addr
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						   Space -> External Device) */
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#define SH7750_CHCR_RS_ER_SA_ED_TO_EA   0x300	/* External Request, Single
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						   Address Mode, (External 
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						   Device -> External Addr 
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						   Address Mode, (External
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						   Device -> External Addr
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						   Space) */
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#define SH7750_CHCR_RS_AR_EA_TO_EA      0x400	/* Auto-Request (External Addr
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						   Space -> External Addr Space) */
......
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#define SH7750_CHCR_RS_AR_EA_TO_OCP     0x500	/* Auto-Request (External Addr
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						   Space -> On-chip Peripheral
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						   Module) */
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#define SH7750_CHCR_RS_AR_OCP_TO_EA     0x600	/* Auto-Request (On-chip 
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#define SH7750_CHCR_RS_AR_OCP_TO_EA     0x600	/* Auto-Request (On-chip
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						   Peripheral Module ->
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						   External Addr Space */
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#define SH7750_CHCR_RS_SCITX_EA_TO_SC   0x800	/* SCI Transmit-Data-Empty intr
......
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#define SH7750_IPRC_HUDI_S    0
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/* 
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/*
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 * User Break Controller registers
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 */
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#define SH7750_BARA           0x200000	/* Break address regiser A */

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