Archipelago » qemu

/*

 * USB UHCI controller emulation

 * Copyright (c) 2005 Fabrice Bellard

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

    /* For simplicity of implementation we only allow a single pending USB

       request.  This means all usb traffic on this controller is effectively

       suspended until that transfer completes.  When the transfer completes

       other queues will not be processed until the next frame.  The solution

       is to allow multiple pending requests.  */

    uint32_t async_qh;

static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)

{

    UHCIState *s = opaque;

    addr &= 0x1f;

    switch(addr) {

    case 0x0c:

static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val)

{

    UHCIState *s = opaque;

    addr &= 0x1f;

#ifdef DEBUG

    printf("uhci writew port=0x%04x val=0x%04x\n", addr, val);

            dev = port->port.dev;

            if (dev) {

                /* port reset */

                     !(port->ctrl & UHCI_PORT_RESET) ) {

                    usb_send_msg(dev, USB_MSG_RESET);

                }

            UHCIPort *port;

            int n;

            n = (addr >> 1) & 7;

                goto read_default;

            port = &s->ports[n];

            val = port->ctrl;

    if (td->ctrl & TD_CTRL_IOC) {

        *int_mask |= 0x01;

    }

    if (!(td->ctrl & TD_CTRL_ACTIVE))

        return 1;

           here.  The docs are somewhat unclear, but win2k relies on this

           behavior.  */

        td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK);

            (td->ctrl & TD_CTRL_SPD) &&

            len < max_len) {

            *int_mask |= 0x02;

                    uhci_update_irq(s);

                }

            }

                (err << TD_CTRL_ERROR_SHIFT);

            return 1;

        case USB_RET_NAK:

    le32_to_cpus(&qh.el_link);

    /* Re-process the queue containing the async packet.  */

    while (1) {

                                 (uint8_t *)&td, sizeof(td));

        le32_to_cpus(&td.link);

        le32_to_cpus(&td.ctrl);

        /* update the status bits of the TD */

        if (old_td_ctrl != td.ctrl) {

            val = cpu_to_le32(td.ctrl);

                                      sizeof(val));

        }

        if (ret < 0)

            /* update qh element link */

            qh.el_link = td.link;

            val = cpu_to_le32(qh.el_link);

                                      sizeof(val));

            if (!(qh.el_link & 4))

                break;

                /* TD */

                if (--cnt == 0)

                    break;

                                         (uint8_t *)&td, sizeof(td));

                le32_to_cpus(&td.link);

                le32_to_cpus(&td.ctrl);

                /* update the status bits of the TD */

                if (old_td_ctrl != td.ctrl) {

                    val = cpu_to_le32(td.ctrl);

                                              sizeof(val));

                }

                if (ret < 0)

                    /* update qh element link */

                    qh.el_link = td.link;

                    val = cpu_to_le32(qh.el_link);

                                              sizeof(val));

                    if (qh.el_link & 4) {

                        /* depth first */

                /* update the status bits of the TD */

                if (old_td_ctrl != td.ctrl) {

                    val = cpu_to_le32(td.ctrl);

                                              sizeof(val));

                }

                if (ret < 0)

        s->async_qh = 0;

    }

    /* prepare the timer for the next frame */

        (ticks_per_sec / FRAME_TIMER_FREQ);

    qemu_mod_timer(s->frame_timer, expire_time);

}

                    uint32_t addr, uint32_t size, int type)

{

    UHCIState *s = (UHCIState *)pci_dev;

    pci_conf[0x0e] = 0x00; // header_type

    pci_conf[0x3d] = 4; // interrupt pin 3

    pci_conf[0x60] = 0x10; // release number

    for(i = 0; i < NB_PORTS; i++) {

        qemu_register_usb_port(&s->ports[i].port, s, i, uhci_attach);

    }

    /* Use region 4 for consistency with real hardware.  BSD guests seem

       to rely on this.  */

                           PCI_ADDRESS_SPACE_IO, uhci_map);

}