Revision 5fafdf24 sparc-dis.c

b/sparc-dis.c
359 359
#define FBFCC(x)	(((x)&0x3)<<20)	/* v9 */
360 360

361 361
/* The order of the opcodes in the table is significant:
362
	
362

  
363 363
	* The assembler requires that all instances of the same mnemonic must
364 364
	be consecutive.	If they aren't, the assembler will bomb at runtime.
365 365

  
......
2341 2341
			 >> ((8 * sizeof (int)) - bits) )
2342 2342

  
2343 2343
static const char * const reg_names[] =
2344
{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",	
2345
  "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",	
2346
  "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",	
2347
  "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",	
2348
  "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",	
2349
  "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",	
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{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
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  "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
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  "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2347
  "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2348
  "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
2349
  "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
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  "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
2351 2351
  "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
2352
  "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",	
2353
  "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",	
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  "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
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  "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
2354 2354
  "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
2355 2355
  "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
2356 2356
/* psr, wim, tbr, fpsr, cpsr are v8 only.  */
......
2566 2566
	  /* Nonzero means that we have found a plus sign in the args
2567 2567
	     field of the opcode table.  */
2568 2568
	  int found_plus = 0;
2569
	  
2569
	 
2570 2570
	  /* Nonzero means we have an annulled branch.  */
2571 2571
	  int is_annulled = 0;
2572 2572

  
......
2621 2621
		  }		/* while there are comma started args */
2622 2622

  
2623 2623
		(*info->fprintf_func) (stream, " ");
2624
			
2624
		
2625 2625
		switch (*s)
2626 2626
		  {
2627 2627
		  case '+':
......
2722 2722
			 not before it.  */
2723 2723
		      if (found_plus)
2724 2724
			imm_added_to_rs1 = 1;
2725
		      
2725
		     
2726 2726
		      if (imm <= 9)
2727 2727
			(*info->fprintf_func) (stream, "%d", imm);
2728 2728
		      else
......
2806 2806
		  case 'o':
2807 2807
		    (*info->fprintf_func) (stream, "%%asi");
2808 2808
		    break;
2809
		    
2809
		   
2810 2810
		  case 'W':
2811 2811
		    (*info->fprintf_func) (stream, "%%tick");
2812 2812
		    break;
......
2859 2859
			(*info->fprintf_func) (stream, "%d", X_RD (insn));
2860 2860
		      break;
2861 2861
		    }
2862
		    
2862
		   
2863 2863
		  case 'M':
2864 2864
		    (*info->fprintf_func) (stream, "%%asr%d", X_RS1 (insn));
2865 2865
		    break;
2866
		    
2866
		   
2867 2867
		  case 'm':
2868 2868
		    (*info->fprintf_func) (stream, "%%asr%d", X_RD (insn));
2869 2869
		    break;
2870
		    
2870
		   
2871 2871
		  case 'L':
2872 2872
		    info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4;
2873 2873
		    (*info->print_address_func) (info->target, info);
......
2999 2999
		      && X_RD (prev_insn) == X_RS1 (insn))
3000 3000
		    {
3001 3001
		      (*info->fprintf_func) (stream, "\t! ");
3002
		      info->target = 
3002
		      info->target =
3003 3003
			((unsigned) 0xFFFFFFFF
3004 3004
			 & ((int) X_IMM22 (prev_insn) << 10));
3005 3005
		      if (imm_added_to_rs1)

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