Revision 5fafdf24 target-arm/cpu.h

b/target-arm/cpu.h
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/*
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 * ARM virtual CPU header
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 * 
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 *
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 *  Copyright (c) 2003 Fabrice Bellard
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 *
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 * This library is free software; you can redistribute it and/or
......
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    uint32_t banked_spsr[6];
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    uint32_t banked_r13[6];
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    uint32_t banked_r14[6];
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    /* These hold r8-r12.  */
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    uint32_t usr_regs[5];
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    uint32_t fiq_regs[5];
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    /* cpsr flag cache for faster execution */
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    uint32_t CF; /* 0 or 1 */
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    uint32_t VF; /* V is the bit 31. All other bits are undefined */
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        /* Temporary variables if we don't have spare fp regs.  */
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        float32 tmp0s, tmp1s;
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        float64 tmp0d, tmp1d;
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        float_status fp_status;
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    } vfp;
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/* you can call this signal handler from your SIGBUS and SIGSEGV
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   signal handlers to inform the virtual CPU of exceptions. non zero
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   is returned if the signal was handled by the virtual CPU.  */
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int cpu_arm_signal_handler(int host_signum, void *pinfo, 
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int cpu_arm_signal_handler(int host_signum, void *pinfo,
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                           void *puc);
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#define CPSR_M (0x1f)
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{
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    int ZF;
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    ZF = (env->NZF == 0);
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    return env->uncached_cpsr | (env->NZF & 0x80000000) | (ZF << 30) | 
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    return env->uncached_cpsr | (env->NZF & 0x80000000) | (ZF << 30) |
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        (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
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        | (env->thumb << 5);
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}

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