Revision 5fafdf24 target-arm/translate.c

b/target-arm/translate.c
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/*
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 *  ARM translation
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 * 
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 *
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 *  Copyright (c) 2003 Fabrice Bellard
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 *  Copyright (c) 2005 CodeSourcery, LLC
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 *  Copyright (c) 2007 OpenedHand, Ltd.
......
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    1, /* bic */
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    1, /* mvn */
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};
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static GenOpFunc1 *gen_shift_T1_im[4] = {
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    gen_op_shll_T1_im,
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    gen_op_shrl_T1_im,
......
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                                        int extra)
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{
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    int val, rm;
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    if (insn & (1 << 22)) {
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        /* immediate */
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        val = (insn & 0xf) | ((insn >> 4) & 0xf0);
......
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            delta_m = 0;
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            delta_d = 0;
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            bank_mask = 0;
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            if (veclen > 0) {
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                if (dp)
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                    bank_mask = 0xc;
......
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static void disas_arm_insn(CPUState * env, DisasContext *s)
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{
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    unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;
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    insn = ldl_code(s->pc);
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    s->pc += 4;
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    cond = insn >> 28;
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    if (cond == 0xf){
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        /* Unconditional instructions.  */
......
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                (insn & 0x00000090) != 0x90) ||
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               ((insn & 0x0e000000) == (1 << 25))) {
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        int set_cc, logic_cc, shiftop;
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        op1 = (insn >> 21) & 0xf;
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        set_cc = (insn >> 20) & 1;
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        logic_cc = table_logic_cc[op1] & set_cc;
......
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                            gen_movl_T1_reg(s, rn);
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                            gen_op_addl_T0_T1();
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                        }
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                        if (insn & (1 << 20)) 
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                        if (insn & (1 << 20))
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                            gen_op_logic_T0_cc();
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                        gen_movl_reg_T0(s, rd);
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                    } else {
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                        /* 64 bit mul */
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                        gen_movl_T0_reg(s, rs);
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                        gen_movl_T1_reg(s, rm);
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                        if (insn & (1 << 22)) 
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                        if (insn & (1 << 22))
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                            gen_op_imull_T0_T1();
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                        else
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                            gen_op_mull_T0_T1();
......
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                            gen_op_addq_lo_T0_T1(rn);
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                            gen_op_addq_lo_T0_T1(rd);
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                        }
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                        if (insn & (1 << 20)) 
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                        if (insn & (1 << 20))
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                            gen_op_logicq_cc();
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                        gen_movl_reg_T0(s, rn);
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                        gen_movl_reg_T1(s, rd);
......
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                    } else {
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                        /* SWP instruction */
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                        rm = (insn) & 0xf;
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                        gen_movl_T0_reg(s, rm);
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                        gen_movl_T1_reg(s, rn);
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                        if (insn & (1 << 22)) {
......
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                }
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                rn = (insn >> 16) & 0xf;
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                gen_movl_T1_reg(s, rn);
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                /* compute total size */
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                loaded_base = 0;
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                n = 0;
......
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        case 0xb:
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            {
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                int32_t offset;
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                /* branch (and link) */
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                val = (int32_t)s->pc;
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                if (insn & (1 << 24)) {
......
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        val = (uint32_t)s->pc + 2;
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        gen_op_movl_T1_im(val | 1);
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        gen_movl_reg_T1(s, 14);
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        val += offset << 1;
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        if (insn & (1 << 12)) {
3506 3506
            /* bl */
......
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/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
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   basic block 'tb'. If search_pc is TRUE, also generate PC
3525 3525
   information for each intermediate instruction. */
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static inline int gen_intermediate_code_internal(CPUState *env, 
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                                                 TranslationBlock *tb, 
3526
static inline int gen_intermediate_code_internal(CPUState *env,
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                                                 TranslationBlock *tb,
3528 3528
                                                 int search_pc)
3529 3529
{
3530 3530
    DisasContext dc1, *dc = &dc1;
......
3532 3532
    int j, lj;
3533 3533
    target_ulong pc_start;
3534 3534
    uint32_t next_page_start;
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3535
   
3536 3536
    /* generate intermediate code */
3537 3537
    pc_start = tb->pc;
3538
       
3538
      
3539 3539
    dc->tb = tb;
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3541 3541
    gen_opc_ptr = gen_opc_buf;
......
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  "usr", "fiq", "irq", "svc", "???", "???", "???", "abt",
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  "???", "???", "???", "und", "???", "???", "???", "sys"
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};
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void cpu_dump_state(CPUState *env, FILE *f, 
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void cpu_dump_state(CPUState *env, FILE *f,
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                    int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
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                    int flags)
3682 3682
{
......
3708 3708
                psr & (1 << 30) ? 'Z' : '-',
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                psr & (1 << 29) ? 'C' : '-',
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                psr & (1 << 28) ? 'V' : '-',
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                psr & CPSR_T ? 'T' : 'A', 
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                psr & CPSR_T ? 'T' : 'A',
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                cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26);
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3714 3714
    for (i = 0; i < 16; i++) {

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