Revision 5fafdf24 target-i386/helper2.c

b/target-i386/helper2.c
1 1
/*
2 2
 *  i386 helpers (without register variable usage)
3
 * 
3
 *
4 4
 *  Copyright (c) 2003 Fabrice Bellard
5 5
 *
6 6
 * This library is free software; you can redistribute it and/or
......
75 75
        ldt.seg_not_present = 0;
76 76
        ldt.useable = 1;
77 77
        modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */
78
        
78
       
79 79
        asm volatile ("movl %0, %%fs" : : "r" ((1 << 3) | 7));
80 80
    }
81 81
#endif
......
173 173
    env->ldt.flags = DESC_P_MASK;
174 174
    env->tr.limit = 0xffff;
175 175
    env->tr.flags = DESC_P_MASK;
176
    
177
    cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 0); 
176
   
177
    cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 0);
178 178
    cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 0);
179 179
    cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 0);
180 180
    cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 0);
181 181
    cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 0);
182 182
    cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 0);
183
    
183
   
184 184
    env->eip = 0xfff0;
185 185
    env->regs[R_EDX] = 0x600; /* indicate P6 processor */
186
    
186
   
187 187
    env->eflags = 0x2;
188
    
188
   
189 189
    /* FPU init */
190 190
    for(i = 0;i < 8; i++)
191 191
        env->fptags[i] = 1;
......
257 257
    "SARQ",
258 258
};
259 259

  
260
void cpu_dump_state(CPUState *env, FILE *f, 
260
void cpu_dump_state(CPUState *env, FILE *f,
261 261
                    int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
262 262
                    int flags)
263 263
{
......
268 268
    eflags = env->eflags;
269 269
#ifdef TARGET_X86_64
270 270
    if (env->hflags & HF_CS64_MASK) {
271
        cpu_fprintf(f, 
271
        cpu_fprintf(f,
272 272
                    "RAX=%016" PRIx64 " RBX=%016" PRIx64 " RCX=%016" PRIx64 " RDX=%016" PRIx64 "\n"
273 273
                    "RSI=%016" PRIx64 " RDI=%016" PRIx64 " RBP=%016" PRIx64 " RSP=%016" PRIx64 "\n"
274 274
                    "R8 =%016" PRIx64 " R9 =%016" PRIx64 " R10=%016" PRIx64 " R11=%016" PRIx64 "\n"
275 275
                    "R12=%016" PRIx64 " R13=%016" PRIx64 " R14=%016" PRIx64 " R15=%016" PRIx64 "\n"
276 276
                    "RIP=%016" PRIx64 " RFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
277
                    env->regs[R_EAX], 
278
                    env->regs[R_EBX], 
279
                    env->regs[R_ECX], 
280
                    env->regs[R_EDX], 
281
                    env->regs[R_ESI], 
282
                    env->regs[R_EDI], 
283
                    env->regs[R_EBP], 
284
                    env->regs[R_ESP], 
285
                    env->regs[8], 
286
                    env->regs[9], 
287
                    env->regs[10], 
288
                    env->regs[11], 
289
                    env->regs[12], 
290
                    env->regs[13], 
291
                    env->regs[14], 
292
                    env->regs[15], 
277
                    env->regs[R_EAX],
278
                    env->regs[R_EBX],
279
                    env->regs[R_ECX],
280
                    env->regs[R_EDX],
281
                    env->regs[R_ESI],
282
                    env->regs[R_EDI],
283
                    env->regs[R_EBP],
284
                    env->regs[R_ESP],
285
                    env->regs[8],
286
                    env->regs[9],
287
                    env->regs[10],
288
                    env->regs[11],
289
                    env->regs[12],
290
                    env->regs[13],
291
                    env->regs[14],
292
                    env->regs[15],
293 293
                    env->eip, eflags,
294 294
                    eflags & DF_MASK ? 'D' : '-',
295 295
                    eflags & CC_O ? 'O' : '-',
......
298 298
                    eflags & CC_A ? 'A' : '-',
299 299
                    eflags & CC_P ? 'P' : '-',
300 300
                    eflags & CC_C ? 'C' : '-',
301
                    env->hflags & HF_CPL_MASK, 
301
                    env->hflags & HF_CPL_MASK,
302 302
                    (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
303 303
                    (env->a20_mask >> 20) & 1,
304 304
                    (env->hflags >> HF_SMM_SHIFT) & 1,
305 305
                    (env->hflags >> HF_HALTED_SHIFT) & 1);
306
    } else 
306
    } else
307 307
#endif
308 308
    {
309 309
        cpu_fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
310 310
                    "ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
311 311
                    "EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
312
                    (uint32_t)env->regs[R_EAX], 
313
                    (uint32_t)env->regs[R_EBX], 
314
                    (uint32_t)env->regs[R_ECX], 
315
                    (uint32_t)env->regs[R_EDX], 
316
                    (uint32_t)env->regs[R_ESI], 
317
                    (uint32_t)env->regs[R_EDI], 
318
                    (uint32_t)env->regs[R_EBP], 
319
                    (uint32_t)env->regs[R_ESP], 
312
                    (uint32_t)env->regs[R_EAX],
313
                    (uint32_t)env->regs[R_EBX],
314
                    (uint32_t)env->regs[R_ECX],
315
                    (uint32_t)env->regs[R_EDX],
316
                    (uint32_t)env->regs[R_ESI],
317
                    (uint32_t)env->regs[R_EDI],
318
                    (uint32_t)env->regs[R_EBP],
319
                    (uint32_t)env->regs[R_ESP],
320 320
                    (uint32_t)env->eip, eflags,
321 321
                    eflags & DF_MASK ? 'D' : '-',
322 322
                    eflags & CC_O ? 'O' : '-',
......
325 325
                    eflags & CC_A ? 'A' : '-',
326 326
                    eflags & CC_P ? 'P' : '-',
327 327
                    eflags & CC_C ? 'C' : '-',
328
                    env->hflags & HF_CPL_MASK, 
328
                    env->hflags & HF_CPL_MASK,
329 329
                    (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
330 330
                    (env->a20_mask >> 20) & 1,
331 331
                    (env->hflags >> HF_SMM_SHIFT) & 1,
......
358 358
        cpu_fprintf(f, "IDT=     %016" PRIx64 " %08x\n",
359 359
                    env->idt.base, env->idt.limit);
360 360
        cpu_fprintf(f, "CR0=%08x CR2=%016" PRIx64 " CR3=%016" PRIx64 " CR4=%08x\n",
361
                    (uint32_t)env->cr[0], 
362
                    env->cr[2], 
363
                    env->cr[3], 
361
                    (uint32_t)env->cr[0],
362
                    env->cr[2],
363
                    env->cr[3],
364 364
                    (uint32_t)env->cr[4]);
365 365
    } else
366 366
#endif
......
389 389
        cpu_fprintf(f, "IDT=     %08x %08x\n",
390 390
                    (uint32_t)env->idt.base, env->idt.limit);
391 391
        cpu_fprintf(f, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",
392
                    (uint32_t)env->cr[0], 
393
                    (uint32_t)env->cr[2], 
394
                    (uint32_t)env->cr[3], 
392
                    (uint32_t)env->cr[0],
393
                    (uint32_t)env->cr[2],
394
                    (uint32_t)env->cr[3],
395 395
                    (uint32_t)env->cr[4]);
396 396
    }
397 397
    if (flags & X86_DUMP_CCOP) {
......
402 402
#ifdef TARGET_X86_64
403 403
        if (env->hflags & HF_CS64_MASK) {
404 404
            cpu_fprintf(f, "CCS=%016" PRIx64 " CCD=%016" PRIx64 " CCO=%-8s\n",
405
                        env->cc_src, env->cc_dst, 
405
                        env->cc_src, env->cc_dst,
406 406
                        cc_op_name);
407
        } else 
407
        } else
408 408
#endif
409 409
        {
410 410
            cpu_fprintf(f, "CCS=%08x CCD=%08x CCO=%-8s\n",
411
                        (uint32_t)env->cc_src, (uint32_t)env->cc_dst, 
411
                        (uint32_t)env->cc_src, (uint32_t)env->cc_dst,
412 412
                        cc_op_name);
413 413
        }
414 414
    }
......
445 445
            else
446 446
                cpu_fprintf(f, " ");
447 447
        }
448
        if (env->hflags & HF_CS64_MASK) 
448
        if (env->hflags & HF_CS64_MASK)
449 449
            nb = 16;
450 450
        else
451 451
            nb = 8;
452 452
        for(i=0;i<nb;i++) {
453 453
            cpu_fprintf(f, "XMM%02d=%08x%08x%08x%08x",
454
                        i, 
454
                        i,
455 455
                        env->xmm_regs[i].XMM_L(3),
456 456
                        env->xmm_regs[i].XMM_L(2),
457 457
                        env->xmm_regs[i].XMM_L(1),
......
516 516
    }
517 517
#endif
518 518
    env->cr[0] = new_cr0 | CR0_ET_MASK;
519
    
519
   
520 520
    /* update PE flag in hidden flags */
521 521
    pe_state = (env->cr[0] & CR0_PE_MASK);
522 522
    env->hflags = (env->hflags & ~HF_PE_MASK) | (pe_state << HF_PE_SHIFT);
......
566 566
    tlb_flush_page(env, addr);
567 567
}
568 568

  
569
#if defined(CONFIG_USER_ONLY) 
569
#if defined(CONFIG_USER_ONLY)
570 570

  
571
int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, 
571
int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
572 572
                             int is_write, int is_user, int is_softmmu)
573 573
{
574 574
    /* user mode only emulation */
......
590 590
#define PHYS_ADDR_MASK 0xfffff000
591 591

  
592 592
/* return value:
593
   -1 = cannot handle fault 
594
   0  = nothing more to do 
593
   -1 = cannot handle fault
594
   0  = nothing more to do
595 595
   1  = generate PF fault
596 596
   2  = soft MMU activation required for this block
597 597
*/
598
int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, 
598
int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
599 599
                             int is_write1, int is_user, int is_softmmu)
600 600
{
601 601
    uint64_t ptep, pte;
......
603 603
    int error_code, is_dirty, prot, page_size, ret, is_write;
604 604
    unsigned long paddr, page_offset;
605 605
    target_ulong vaddr, virt_addr;
606
    
606
   
607 607
#if defined(DEBUG_MMU)
608
    printf("MMU fault: addr=" TARGET_FMT_lx " w=%d u=%d eip=" TARGET_FMT_lx "\n", 
608
    printf("MMU fault: addr=" TARGET_FMT_lx " w=%d u=%d eip=" TARGET_FMT_lx "\n",
609 609
           addr, is_write1, is_user, env->eip);
610 610
#endif
611 611
    is_write = is_write1 & 1;
612
    
612
   
613 613
    if (!(env->cr[0] & CR0_PG_MASK)) {
614 614
        pte = addr;
615 615
        virt_addr = addr & TARGET_PAGE_MASK;
......
635 635
                env->exception_index = EXCP0D_GPF;
636 636
                return 1;
637 637
            }
638
            
639
            pml4e_addr = ((env->cr[3] & ~0xfff) + (((addr >> 39) & 0x1ff) << 3)) & 
638
           
639
            pml4e_addr = ((env->cr[3] & ~0xfff) + (((addr >> 39) & 0x1ff) << 3)) &
640 640
                env->a20_mask;
641 641
            pml4e = ldq_phys(pml4e_addr);
642 642
            if (!(pml4e & PG_PRESENT_MASK)) {
......
652 652
                stl_phys_notdirty(pml4e_addr, pml4e);
653 653
            }
654 654
            ptep = pml4e ^ PG_NX_MASK;
655
            pdpe_addr = ((pml4e & PHYS_ADDR_MASK) + (((addr >> 30) & 0x1ff) << 3)) & 
655
            pdpe_addr = ((pml4e & PHYS_ADDR_MASK) + (((addr >> 30) & 0x1ff) << 3)) &
656 656
                env->a20_mask;
657 657
            pdpe = ldq_phys(pdpe_addr);
658 658
            if (!(pdpe & PG_PRESENT_MASK)) {
......
672 672
#endif
673 673
        {
674 674
            /* XXX: load them when cr3 is loaded ? */
675
            pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) & 
675
            pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) &
676 676
                env->a20_mask;
677 677
            pdpe = ldq_phys(pdpe_addr);
678 678
            if (!(pdpe & PG_PRESENT_MASK)) {
......
706 706
                if (is_write && !(ptep & PG_RW_MASK))
707 707
                    goto do_fault_protect;
708 708
            } else {
709
                if ((env->cr[0] & CR0_WP_MASK) && 
710
                    is_write && !(ptep & PG_RW_MASK)) 
709
                if ((env->cr[0] & CR0_WP_MASK) &&
710
                    is_write && !(ptep & PG_RW_MASK))
711 711
                    goto do_fault_protect;
712 712
            }
713 713
            is_dirty = is_write && !(pde & PG_DIRTY_MASK);
......
718 718
                stl_phys_notdirty(pde_addr, pde);
719 719
            }
720 720
            /* align to page_size */
721
            pte = pde & ((PHYS_ADDR_MASK & ~(page_size - 1)) | 0xfff); 
721
            pte = pde & ((PHYS_ADDR_MASK & ~(page_size - 1)) | 0xfff);
722 722
            virt_addr = addr & ~(page_size - 1);
723 723
        } else {
724 724
            /* 4 KB page */
......
741 741
            ptep &= pte ^ PG_NX_MASK;
742 742
            ptep ^= PG_NX_MASK;
743 743
            if ((ptep & PG_NX_MASK) && is_write1 == 2)
744
                goto do_fault_protect; 
744
                goto do_fault_protect;
745 745
            if (is_user) {
746 746
                if (!(ptep & PG_USER_MASK))
747 747
                    goto do_fault_protect;
......
749 749
                    goto do_fault_protect;
750 750
            } else {
751 751
                if ((env->cr[0] & CR0_WP_MASK) &&
752
                    is_write && !(ptep & PG_RW_MASK)) 
752
                    is_write && !(ptep & PG_RW_MASK))
753 753
                    goto do_fault_protect;
754 754
            }
755 755
            is_dirty = is_write && !(pte & PG_DIRTY_MASK);
......
767 767
        uint32_t pde;
768 768

  
769 769
        /* page directory entry */
770
        pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) & 
770
        pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) &
771 771
            env->a20_mask;
772 772
        pde = ldl_phys(pde_addr);
773 773
        if (!(pde & PG_PRESENT_MASK)) {
......
783 783
                if (is_write && !(pde & PG_RW_MASK))
784 784
                    goto do_fault_protect;
785 785
            } else {
786
                if ((env->cr[0] & CR0_WP_MASK) && 
787
                    is_write && !(pde & PG_RW_MASK)) 
786
                if ((env->cr[0] & CR0_WP_MASK) &&
787
                    is_write && !(pde & PG_RW_MASK))
788 788
                    goto do_fault_protect;
789 789
            }
790 790
            is_dirty = is_write && !(pde & PG_DIRTY_MASK);
......
794 794
                    pde |= PG_DIRTY_MASK;
795 795
                stl_phys_notdirty(pde_addr, pde);
796 796
            }
797
        
797
       
798 798
            pte = pde & ~( (page_size - 1) & ~0xfff); /* align to page_size */
799 799
            ptep = pte;
800 800
            virt_addr = addr & ~(page_size - 1);
......
805 805
            }
806 806

  
807 807
            /* page directory entry */
808
            pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & 
808
            pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) &
809 809
                env->a20_mask;
810 810
            pte = ldl_phys(pte_addr);
811 811
            if (!(pte & PG_PRESENT_MASK)) {
......
821 821
                    goto do_fault_protect;
822 822
            } else {
823 823
                if ((env->cr[0] & CR0_WP_MASK) &&
824
                    is_write && !(ptep & PG_RW_MASK)) 
824
                    is_write && !(ptep & PG_RW_MASK))
825 825
                    goto do_fault_protect;
826 826
            }
827 827
            is_dirty = is_write && !(pte & PG_DIRTY_MASK);
......
859 859
    page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
860 860
    paddr = (pte & TARGET_PAGE_MASK) + page_offset;
861 861
    vaddr = virt_addr + page_offset;
862
    
862
   
863 863
    ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
864 864
    return ret;
865 865
 do_fault_protect:
......
869 869
    error_code |= (is_write << PG_ERROR_W_BIT);
870 870
    if (is_user)
871 871
        error_code |= PG_ERROR_U_MASK;
872
    if (is_write1 == 2 && 
873
        (env->efer & MSR_EFER_NXE) && 
872
    if (is_write1 == 2 &&
873
        (env->efer & MSR_EFER_NXE) &&
874 874
        (env->cr[4] & CR4_PAE_MASK))
875 875
        error_code |= PG_ERROR_I_D_MASK;
876 876
    env->error_code = error_code;
......
897 897
            sext = (int64_t)addr >> 47;
898 898
            if (sext != 0 && sext != -1)
899 899
                return -1;
900
            
901
            pml4e_addr = ((env->cr[3] & ~0xfff) + (((addr >> 39) & 0x1ff) << 3)) & 
900
           
901
            pml4e_addr = ((env->cr[3] & ~0xfff) + (((addr >> 39) & 0x1ff) << 3)) &
902 902
                env->a20_mask;
903 903
            pml4e = ldl_phys(pml4e_addr);
904 904
            if (!(pml4e & PG_PRESENT_MASK))
905 905
                return -1;
906
            
907
            pdpe_addr = ((pml4e & ~0xfff) + (((addr >> 30) & 0x1ff) << 3)) & 
906
           
907
            pdpe_addr = ((pml4e & ~0xfff) + (((addr >> 30) & 0x1ff) << 3)) &
908 908
                env->a20_mask;
909 909
            pdpe = ldl_phys(pdpe_addr);
910 910
            if (!(pdpe & PG_PRESENT_MASK))
911 911
                return -1;
912
        } else 
912
        } else
913 913
#endif
914 914
        {
915
            pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) & 
915
            pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) &
916 916
                env->a20_mask;
917 917
            pdpe = ldl_phys(pdpe_addr);
918 918
            if (!(pdpe & PG_PRESENT_MASK))
......
944 944
            /* page directory entry */
945 945
            pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) & env->a20_mask;
946 946
            pde = ldl_phys(pde_addr);
947
            if (!(pde & PG_PRESENT_MASK)) 
947
            if (!(pde & PG_PRESENT_MASK))
948 948
                return -1;
949 949
            if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
950 950
                pte = pde & ~0x003ff000; /* align to 4MB */
......
987 987
{
988 988
    int fptag, i, j;
989 989
    struct fpstate fp1, *fp = &fp1;
990
    
990
   
991 991
    fp->fpuc = env->fpuc;
992 992
    fp->fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
993 993
    fptag = 0;
......
1008 1008
    asm volatile ("frstor %0" : "=m" (*fp));
1009 1009
    env->native_fp_regs = 1;
1010 1010
}
1011
 
1011

  
1012 1012
void save_native_fp_state(CPUState *env)
1013 1013
{
1014 1014
    int fptag, i, j;

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