commit 5fafdf24ef2c090c164d4dc89684b3f379dbdd87
Author: ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>
Date:   Sun Sep 16 21:08:06 2007 +0000

    find -type f | xargs sed -i 's/[\t ]$//g' # on most files
    
    
    git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162

diff --git a/target-i386/helper2.c b/target-i386/helper2.c
index 327d54b..8b61cf8 100644
--- a/target-i386/helper2.c
+++ b/target-i386/helper2.c
@@ -1,6 +1,6 @@
 /*
  *  i386 helpers (without register variable usage)
- * 
+ *
  *  Copyright (c) 2003 Fabrice Bellard
  *
  * This library is free software; you can redistribute it and/or
@@ -75,7 +75,7 @@ CPUX86State *cpu_x86_init(void)
         ldt.seg_not_present = 0;
         ldt.useable = 1;
         modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */
-        
+       
         asm volatile ("movl %0, %%fs" : : "r" ((1 << 3) | 7));
     }
 #endif
@@ -173,19 +173,19 @@ void cpu_reset(CPUX86State *env)
     env->ldt.flags = DESC_P_MASK;
     env->tr.limit = 0xffff;
     env->tr.flags = DESC_P_MASK;
-    
-    cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 0); 
+   
+    cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 0);
     cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 0);
     cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 0);
     cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 0);
     cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 0);
     cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 0);
-    
+   
     env->eip = 0xfff0;
     env->regs[R_EDX] = 0x600; /* indicate P6 processor */
-    
+   
     env->eflags = 0x2;
-    
+   
     /* FPU init */
     for(i = 0;i < 8; i++)
         env->fptags[i] = 1;
@@ -257,7 +257,7 @@ static const char *cc_op_str[] = {
     "SARQ",
 };
 
-void cpu_dump_state(CPUState *env, FILE *f, 
+void cpu_dump_state(CPUState *env, FILE *f,
                     int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
                     int flags)
 {
@@ -268,28 +268,28 @@ void cpu_dump_state(CPUState *env, FILE *f,
     eflags = env->eflags;
 #ifdef TARGET_X86_64
     if (env->hflags & HF_CS64_MASK) {
-        cpu_fprintf(f, 
+        cpu_fprintf(f,
                     "RAX=%016" PRIx64 " RBX=%016" PRIx64 " RCX=%016" PRIx64 " RDX=%016" PRIx64 "\n"
                     "RSI=%016" PRIx64 " RDI=%016" PRIx64 " RBP=%016" PRIx64 " RSP=%016" PRIx64 "\n"
                     "R8 =%016" PRIx64 " R9 =%016" PRIx64 " R10=%016" PRIx64 " R11=%016" PRIx64 "\n"
                     "R12=%016" PRIx64 " R13=%016" PRIx64 " R14=%016" PRIx64 " R15=%016" PRIx64 "\n"
                     "RIP=%016" PRIx64 " RFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
-                    env->regs[R_EAX], 
-                    env->regs[R_EBX], 
-                    env->regs[R_ECX], 
-                    env->regs[R_EDX], 
-                    env->regs[R_ESI], 
-                    env->regs[R_EDI], 
-                    env->regs[R_EBP], 
-                    env->regs[R_ESP], 
-                    env->regs[8], 
-                    env->regs[9], 
-                    env->regs[10], 
-                    env->regs[11], 
-                    env->regs[12], 
-                    env->regs[13], 
-                    env->regs[14], 
-                    env->regs[15], 
+                    env->regs[R_EAX],
+                    env->regs[R_EBX],
+                    env->regs[R_ECX],
+                    env->regs[R_EDX],
+                    env->regs[R_ESI],
+                    env->regs[R_EDI],
+                    env->regs[R_EBP],
+                    env->regs[R_ESP],
+                    env->regs[8],
+                    env->regs[9],
+                    env->regs[10],
+                    env->regs[11],
+                    env->regs[12],
+                    env->regs[13],
+                    env->regs[14],
+                    env->regs[15],
                     env->eip, eflags,
                     eflags & DF_MASK ? 'D' : '-',
                     eflags & CC_O ? 'O' : '-',
@@ -298,25 +298,25 @@ void cpu_dump_state(CPUState *env, FILE *f,
                     eflags & CC_A ? 'A' : '-',
                     eflags & CC_P ? 'P' : '-',
                     eflags & CC_C ? 'C' : '-',
-                    env->hflags & HF_CPL_MASK, 
+                    env->hflags & HF_CPL_MASK,
                     (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
                     (env->a20_mask >> 20) & 1,
                     (env->hflags >> HF_SMM_SHIFT) & 1,
                     (env->hflags >> HF_HALTED_SHIFT) & 1);
-    } else 
+    } else
 #endif
     {
         cpu_fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
                     "ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
                     "EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
-                    (uint32_t)env->regs[R_EAX], 
-                    (uint32_t)env->regs[R_EBX], 
-                    (uint32_t)env->regs[R_ECX], 
-                    (uint32_t)env->regs[R_EDX], 
-                    (uint32_t)env->regs[R_ESI], 
-                    (uint32_t)env->regs[R_EDI], 
-                    (uint32_t)env->regs[R_EBP], 
-                    (uint32_t)env->regs[R_ESP], 
+                    (uint32_t)env->regs[R_EAX],
+                    (uint32_t)env->regs[R_EBX],
+                    (uint32_t)env->regs[R_ECX],
+                    (uint32_t)env->regs[R_EDX],
+                    (uint32_t)env->regs[R_ESI],
+                    (uint32_t)env->regs[R_EDI],
+                    (uint32_t)env->regs[R_EBP],
+                    (uint32_t)env->regs[R_ESP],
                     (uint32_t)env->eip, eflags,
                     eflags & DF_MASK ? 'D' : '-',
                     eflags & CC_O ? 'O' : '-',
@@ -325,7 +325,7 @@ void cpu_dump_state(CPUState *env, FILE *f,
                     eflags & CC_A ? 'A' : '-',
                     eflags & CC_P ? 'P' : '-',
                     eflags & CC_C ? 'C' : '-',
-                    env->hflags & HF_CPL_MASK, 
+                    env->hflags & HF_CPL_MASK,
                     (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
                     (env->a20_mask >> 20) & 1,
                     (env->hflags >> HF_SMM_SHIFT) & 1,
@@ -358,9 +358,9 @@ void cpu_dump_state(CPUState *env, FILE *f,
         cpu_fprintf(f, "IDT=     %016" PRIx64 " %08x\n",
                     env->idt.base, env->idt.limit);
         cpu_fprintf(f, "CR0=%08x CR2=%016" PRIx64 " CR3=%016" PRIx64 " CR4=%08x\n",
-                    (uint32_t)env->cr[0], 
-                    env->cr[2], 
-                    env->cr[3], 
+                    (uint32_t)env->cr[0],
+                    env->cr[2],
+                    env->cr[3],
                     (uint32_t)env->cr[4]);
     } else
 #endif
@@ -389,9 +389,9 @@ void cpu_dump_state(CPUState *env, FILE *f,
         cpu_fprintf(f, "IDT=     %08x %08x\n",
                     (uint32_t)env->idt.base, env->idt.limit);
         cpu_fprintf(f, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",
-                    (uint32_t)env->cr[0], 
-                    (uint32_t)env->cr[2], 
-                    (uint32_t)env->cr[3], 
+                    (uint32_t)env->cr[0],
+                    (uint32_t)env->cr[2],
+                    (uint32_t)env->cr[3],
                     (uint32_t)env->cr[4]);
     }
     if (flags & X86_DUMP_CCOP) {
@@ -402,13 +402,13 @@ void cpu_dump_state(CPUState *env, FILE *f,
 #ifdef TARGET_X86_64
         if (env->hflags & HF_CS64_MASK) {
             cpu_fprintf(f, "CCS=%016" PRIx64 " CCD=%016" PRIx64 " CCO=%-8s\n",
-                        env->cc_src, env->cc_dst, 
+                        env->cc_src, env->cc_dst,
                         cc_op_name);
-        } else 
+        } else
 #endif
         {
             cpu_fprintf(f, "CCS=%08x CCD=%08x CCO=%-8s\n",
-                        (uint32_t)env->cc_src, (uint32_t)env->cc_dst, 
+                        (uint32_t)env->cc_src, (uint32_t)env->cc_dst,
                         cc_op_name);
         }
     }
@@ -445,13 +445,13 @@ void cpu_dump_state(CPUState *env, FILE *f,
             else
                 cpu_fprintf(f, " ");
         }
-        if (env->hflags & HF_CS64_MASK) 
+        if (env->hflags & HF_CS64_MASK)
             nb = 16;
         else
             nb = 8;
         for(i=0;i<nb;i++) {
             cpu_fprintf(f, "XMM%02d=%08x%08x%08x%08x",
-                        i, 
+                        i,
                         env->xmm_regs[i].XMM_L(3),
                         env->xmm_regs[i].XMM_L(2),
                         env->xmm_regs[i].XMM_L(1),
@@ -516,7 +516,7 @@ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
     }
 #endif
     env->cr[0] = new_cr0 | CR0_ET_MASK;
-    
+   
     /* update PE flag in hidden flags */
     pe_state = (env->cr[0] & CR0_PE_MASK);
     env->hflags = (env->hflags & ~HF_PE_MASK) | (pe_state << HF_PE_SHIFT);
@@ -566,9 +566,9 @@ void cpu_x86_flush_tlb(CPUX86State *env, target_ulong addr)
     tlb_flush_page(env, addr);
 }
 
-#if defined(CONFIG_USER_ONLY) 
+#if defined(CONFIG_USER_ONLY)
 
-int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, 
+int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
                              int is_write, int is_user, int is_softmmu)
 {
     /* user mode only emulation */
@@ -590,12 +590,12 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
 #define PHYS_ADDR_MASK 0xfffff000
 
 /* return value:
-   -1 = cannot handle fault 
-   0  = nothing more to do 
+   -1 = cannot handle fault
+   0  = nothing more to do
    1  = generate PF fault
    2  = soft MMU activation required for this block
 */
-int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, 
+int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
                              int is_write1, int is_user, int is_softmmu)
 {
     uint64_t ptep, pte;
@@ -603,13 +603,13 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
     int error_code, is_dirty, prot, page_size, ret, is_write;
     unsigned long paddr, page_offset;
     target_ulong vaddr, virt_addr;
-    
+   
 #if defined(DEBUG_MMU)
-    printf("MMU fault: addr=" TARGET_FMT_lx " w=%d u=%d eip=" TARGET_FMT_lx "\n", 
+    printf("MMU fault: addr=" TARGET_FMT_lx " w=%d u=%d eip=" TARGET_FMT_lx "\n",
            addr, is_write1, is_user, env->eip);
 #endif
     is_write = is_write1 & 1;
-    
+   
     if (!(env->cr[0] & CR0_PG_MASK)) {
         pte = addr;
         virt_addr = addr & TARGET_PAGE_MASK;
@@ -635,8 +635,8 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
                 env->exception_index = EXCP0D_GPF;
                 return 1;
             }
-            
-            pml4e_addr = ((env->cr[3] & ~0xfff) + (((addr >> 39) & 0x1ff) << 3)) & 
+           
+            pml4e_addr = ((env->cr[3] & ~0xfff) + (((addr >> 39) & 0x1ff) << 3)) &
                 env->a20_mask;
             pml4e = ldq_phys(pml4e_addr);
             if (!(pml4e & PG_PRESENT_MASK)) {
@@ -652,7 +652,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
                 stl_phys_notdirty(pml4e_addr, pml4e);
             }
             ptep = pml4e ^ PG_NX_MASK;
-            pdpe_addr = ((pml4e & PHYS_ADDR_MASK) + (((addr >> 30) & 0x1ff) << 3)) & 
+            pdpe_addr = ((pml4e & PHYS_ADDR_MASK) + (((addr >> 30) & 0x1ff) << 3)) &
                 env->a20_mask;
             pdpe = ldq_phys(pdpe_addr);
             if (!(pdpe & PG_PRESENT_MASK)) {
@@ -672,7 +672,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
 #endif
         {
             /* XXX: load them when cr3 is loaded ? */
-            pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) & 
+            pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) &
                 env->a20_mask;
             pdpe = ldq_phys(pdpe_addr);
             if (!(pdpe & PG_PRESENT_MASK)) {
@@ -706,8 +706,8 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
                 if (is_write && !(ptep & PG_RW_MASK))
                     goto do_fault_protect;
             } else {
-                if ((env->cr[0] & CR0_WP_MASK) && 
-                    is_write && !(ptep & PG_RW_MASK)) 
+                if ((env->cr[0] & CR0_WP_MASK) &&
+                    is_write && !(ptep & PG_RW_MASK))
                     goto do_fault_protect;
             }
             is_dirty = is_write && !(pde & PG_DIRTY_MASK);
@@ -718,7 +718,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
                 stl_phys_notdirty(pde_addr, pde);
             }
             /* align to page_size */
-            pte = pde & ((PHYS_ADDR_MASK & ~(page_size - 1)) | 0xfff); 
+            pte = pde & ((PHYS_ADDR_MASK & ~(page_size - 1)) | 0xfff);
             virt_addr = addr & ~(page_size - 1);
         } else {
             /* 4 KB page */
@@ -741,7 +741,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
             ptep &= pte ^ PG_NX_MASK;
             ptep ^= PG_NX_MASK;
             if ((ptep & PG_NX_MASK) && is_write1 == 2)
-                goto do_fault_protect; 
+                goto do_fault_protect;
             if (is_user) {
                 if (!(ptep & PG_USER_MASK))
                     goto do_fault_protect;
@@ -749,7 +749,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
                     goto do_fault_protect;
             } else {
                 if ((env->cr[0] & CR0_WP_MASK) &&
-                    is_write && !(ptep & PG_RW_MASK)) 
+                    is_write && !(ptep & PG_RW_MASK))
                     goto do_fault_protect;
             }
             is_dirty = is_write && !(pte & PG_DIRTY_MASK);
@@ -767,7 +767,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
         uint32_t pde;
 
         /* page directory entry */
-        pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) & 
+        pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) &
             env->a20_mask;
         pde = ldl_phys(pde_addr);
         if (!(pde & PG_PRESENT_MASK)) {
@@ -783,8 +783,8 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
                 if (is_write && !(pde & PG_RW_MASK))
                     goto do_fault_protect;
             } else {
-                if ((env->cr[0] & CR0_WP_MASK) && 
-                    is_write && !(pde & PG_RW_MASK)) 
+                if ((env->cr[0] & CR0_WP_MASK) &&
+                    is_write && !(pde & PG_RW_MASK))
                     goto do_fault_protect;
             }
             is_dirty = is_write && !(pde & PG_DIRTY_MASK);
@@ -794,7 +794,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
                     pde |= PG_DIRTY_MASK;
                 stl_phys_notdirty(pde_addr, pde);
             }
-        
+       
             pte = pde & ~( (page_size - 1) & ~0xfff); /* align to page_size */
             ptep = pte;
             virt_addr = addr & ~(page_size - 1);
@@ -805,7 +805,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
             }
 
             /* page directory entry */
-            pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & 
+            pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) &
                 env->a20_mask;
             pte = ldl_phys(pte_addr);
             if (!(pte & PG_PRESENT_MASK)) {
@@ -821,7 +821,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
                     goto do_fault_protect;
             } else {
                 if ((env->cr[0] & CR0_WP_MASK) &&
-                    is_write && !(ptep & PG_RW_MASK)) 
+                    is_write && !(ptep & PG_RW_MASK))
                     goto do_fault_protect;
             }
             is_dirty = is_write && !(pte & PG_DIRTY_MASK);
@@ -859,7 +859,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
     page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
     paddr = (pte & TARGET_PAGE_MASK) + page_offset;
     vaddr = virt_addr + page_offset;
-    
+   
     ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
     return ret;
  do_fault_protect:
@@ -869,8 +869,8 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
     error_code |= (is_write << PG_ERROR_W_BIT);
     if (is_user)
         error_code |= PG_ERROR_U_MASK;
-    if (is_write1 == 2 && 
-        (env->efer & MSR_EFER_NXE) && 
+    if (is_write1 == 2 &&
+        (env->efer & MSR_EFER_NXE) &&
         (env->cr[4] & CR4_PAE_MASK))
         error_code |= PG_ERROR_I_D_MASK;
     env->error_code = error_code;
@@ -897,22 +897,22 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
             sext = (int64_t)addr >> 47;
             if (sext != 0 && sext != -1)
                 return -1;
-            
-            pml4e_addr = ((env->cr[3] & ~0xfff) + (((addr >> 39) & 0x1ff) << 3)) & 
+           
+            pml4e_addr = ((env->cr[3] & ~0xfff) + (((addr >> 39) & 0x1ff) << 3)) &
                 env->a20_mask;
             pml4e = ldl_phys(pml4e_addr);
             if (!(pml4e & PG_PRESENT_MASK))
                 return -1;
-            
-            pdpe_addr = ((pml4e & ~0xfff) + (((addr >> 30) & 0x1ff) << 3)) & 
+           
+            pdpe_addr = ((pml4e & ~0xfff) + (((addr >> 30) & 0x1ff) << 3)) &
                 env->a20_mask;
             pdpe = ldl_phys(pdpe_addr);
             if (!(pdpe & PG_PRESENT_MASK))
                 return -1;
-        } else 
+        } else
 #endif
         {
-            pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) & 
+            pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) &
                 env->a20_mask;
             pdpe = ldl_phys(pdpe_addr);
             if (!(pdpe & PG_PRESENT_MASK))
@@ -944,7 +944,7 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
             /* page directory entry */
             pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) & env->a20_mask;
             pde = ldl_phys(pde_addr);
-            if (!(pde & PG_PRESENT_MASK)) 
+            if (!(pde & PG_PRESENT_MASK))
                 return -1;
             if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
                 pte = pde & ~0x003ff000; /* align to 4MB */
@@ -987,7 +987,7 @@ void restore_native_fp_state(CPUState *env)
 {
     int fptag, i, j;
     struct fpstate fp1, *fp = &fp1;
-    
+   
     fp->fpuc = env->fpuc;
     fp->fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
     fptag = 0;
@@ -1008,7 +1008,7 @@ void restore_native_fp_state(CPUState *env)
     asm volatile ("frstor %0" : "=m" (*fp));
     env->native_fp_regs = 1;
 }
- 
+
 void save_native_fp_state(CPUState *env)
 {
     int fptag, i, j;
