Archipelago » qemu

/*

 *  i386 on i386 translation

 *  Copyright (c) 2003 Fabrice Bellard

 *

 * This library is free software; you can redistribute it and/or

enum {

    OT_BYTE = 0,

    OT_WORD,

    OT_QUAD,

};

    /* code output */

    uint8_t *gen_code_ptr;

    uint8_t *gen_code_start;

    /* current block context */

    target_ulong cs_base; /* base of CS segment */

    int pe;     /* protected mode */

    gl(s, val - (long)(s->gen_code_ptr + 4));

}

                                    uint32_t addr, uint32_t val)

{

    gb(s, CPU_SEG); /* seg movl im, addr */

    gb(s, 0x05);

    gl(s, addr);

    gl(s, val);

}

                                    uint32_t addr, uint32_t val)

{

    gb(s, CPU_SEG); /* seg movl im, addr */

    gb(s, 0x05);

    gl(s, addr);

    gw(s, val);

    gb(s, 0xe9); /* jmp */

    tb->tb_jmp_offset[1] = s->gen_code_ptr - s->gen_code_start;

    gl(s, 0);

    tb->tb_next_offset[0] = s->gen_code_ptr - s->gen_code_start;

    gen_movl_addr_im(s, CPU_FIELD_OFFSET(eip), target_eip);

    gen_movl_addr_im(s, CPU_FIELD_OFFSET(tmp0), (uint32_t)tb);

        base = rm;

        index = 0;

        scale = 0;

        if (base == 4) {

            havesib = 1;

            code = ldub_code(s->pc++);

            s->pc += 4;

            break;

        }

    } else {

        switch (mod) {

        case 0:

static inline void parse_modrm(DisasContext *s, int modrm)

{

    if ((modrm & 0xc0) != 0xc0)

}

static inline uint32_t insn_get(DisasContext *s, int ot)

        /* extended op code */

        b = ldub_code(s->pc++) | 0x100;

        goto reswitch;

        /**************************/

        /* arith & logic */

    case 0x00 ... 0x05:

                ot = OT_BYTE;

            else

                ot = dflag ? OT_LONG : OT_WORD;

            switch(f) {

            case 0: /* OP Ev, Gv */

                modrm = ldub_code(s->pc++);

                ot = OT_BYTE;

            else

                ot = dflag ? OT_LONG : OT_WORD;

            modrm = ldub_code(s->pc++);

            parse_modrm(s, modrm);

            break;

        case 2: /* call Ev */

            /* XXX: optimize and handle MEM exceptions specifically

               pushl next_eip

               fs movl %eax, eip

            */

            goto unsupported_op;

        case 4: /* jmp Ev */

            /* XXX: optimize and handle MEM exceptions specifically

               fs movl %eax, eip

            */

            goto unsupported_op;

            ot = dflag ? OT_LONG : OT_WORD;

        insn_get(s, ot);

        break;

    case 0x98: /* CWDE/CBW */

        break;

    case 0x99: /* CDQ/CWD */

        break;

    case 0x84: /* test Ev, Gv */

    case 0x1c0:

    case 0x1c1: /* xadd Ev, Gv */

            goto illegal_op;

        parse_modrm(s, modrm);

        break;

        /**************************/

        /* push/pop */

    case 0x50 ... 0x57: /* push */

        goto unsupported_op;

        /************************/

        /* floats */

#if 1

        /* currently not stable enough */

        goto unsupported_op;

            goto illegal_op;

        parse_modrm(s, modrm);

        break;

    case 0xa0: /* mov EAX, Ov */

    case 0xa1:

    case 0xa2: /* mov Ov, EAX */

        parse_modrm(s, modrm);

        ldub_code(s->pc++);

        break;

        /************************/

        /* string ops */

    case 0xa4: /* movsS */

    case 0xa5:

        break;

    case 0xaa: /* stosS */

    case 0xab:

        break;

    case 0xc3: /* ret */

        gb(s, CPU_SEG);

            gb(s, 0x66); /* d16 */

        gb(s, 0x8f); /* pop addr */

        gb(s, 0x05);

        if (dflag) {

            val = insn_get(s, OT_LONG);

        } else {

        }

    do_jcc:

        next_eip = s->pc - s->cs_base;

    case 0x90: /* nop */

        break;

    case 0x9b: /* fwait */

            (HF_MP_MASK | HF_TS_MASK)) {

            goto unsupported_op;

        }

#define GEN_CODE_MAX_INSN_SIZE 512

static inline int gen_intermediate_code_internal(CPUState *env,

                                                 uint8_t *gen_code_ptr,

                                                 int *gen_code_size_ptr,

                                                 int search_pc,

        env->singlestep_enabled)

        return -1;

    flags = tb->flags;

                 HF_SOFTMMU_MASK | HF_INHIBIT_IRQ_MASK))

        return -1;

    if (!(flags & HF_SS32_MASK))

        return -1;

    if (tb->cflags & CF_SINGLE_INSN)

        return -1;

        GEN_CODE_MAX_SIZE - GEN_CODE_MAX_INSN_SIZE;

    dc->gen_code_ptr = gen_code_ptr;

    dc->gen_code_start = gen_code_ptr;

            break;

        }

    }

#ifdef DEBUG_DISAS

    if (loglevel & CPU_LOG_TB_IN_ASM) {

        fprintf(logfile, "----------------\n");

                lookup_symbol(pc_start),

                tb->cflags & CF_TB_FP_USED ? 1 : 0);

	target_disas(logfile, pc_start, dc->pc - pc_start, !dc->code32);

    tb->tb_jmp_offset[2] = 0xffff;

    tb->tb_jmp_offset[3] = 0xffff;

#endif

                                          tb->tc_ptr, gen_code_size_ptr,

                                          0, NULL);

}

static uint8_t dummy_gen_code_buf[GEN_CODE_MAX_SIZE];

                           CPUState *env, unsigned long searched_pc,

                           void *puc)

{

    if (searched_pc < (unsigned long)tb->tc_ptr)

        return -1;

    searched_pc = searched_pc - (long)tb->tc_ptr + (long)dummy_gen_code_buf;

                                         dummy_gen_code_buf, NULL,

                                         1, (uint8_t *)searched_pc);

    if (ret < 0)

        return ret;

    /* restore all the CPU state from the CPU context from the

       signal. The FPU context stays in the host CPU. */

    env->regs[R_EAX] = uc->uc_mcontext.gregs[REG_EAX];

    env->regs[R_ECX] = uc->uc_mcontext.gregs[REG_ECX];

    env->regs[R_EDX] = uc->uc_mcontext.gregs[REG_EDX];