Revision 5fafdf24 target-i386/translate.c

b/target-i386/translate.c
1 1
/*
2 2
 *  i386 translation
3
 * 
3
 *
4 4
 *  Copyright (c) 2003 Fabrice Bellard
5 5
 *
6 6
 * This library is free software; you can redistribute it and/or
......
109 109

  
110 110
/* i386 arith/logic operations */
111 111
enum {
112
    OP_ADDL, 
113
    OP_ORL, 
114
    OP_ADCL, 
112
    OP_ADDL,
113
    OP_ORL,
114
    OP_ADCL,
115 115
    OP_SBBL,
116
    OP_ANDL, 
117
    OP_SUBL, 
118
    OP_XORL, 
116
    OP_ANDL,
117
    OP_SUBL,
118
    OP_XORL,
119 119
    OP_CMPL,
120 120
};
121 121

  
122 122
/* i386 shift ops */
123 123
enum {
124
    OP_ROL, 
125
    OP_ROR, 
126
    OP_RCL, 
127
    OP_RCR, 
128
    OP_SHL, 
129
    OP_SHR, 
124
    OP_ROL,
125
    OP_ROR,
126
    OP_RCL,
127
    OP_RCR,
128
    OP_SHL,
129
    OP_SHR,
130 130
    OP_SHL1, /* undocumented */
131 131
    OP_SAR = 7,
132 132
};
......
144 144
enum {
145 145
    OT_BYTE = 0,
146 146
    OT_WORD,
147
    OT_LONG, 
147
    OT_LONG,
148 148
    OT_QUAD,
149 149
};
150 150

  
......
333 333
#endif
334 334
};
335 335

  
336
static GenOpFunc *gen_op_mov_TN_reg[NB_OP_SIZES][2][CPU_NB_REGS] = 
336
static GenOpFunc *gen_op_mov_TN_reg[NB_OP_SIZES][2][CPU_NB_REGS] =
337 337
{
338 338
    [OT_BYTE] = {
339 339
        {
......
878 878
    gen_op_jnz_ecxl,
879 879
    X86_64_ONLY(gen_op_jnz_ecxq),
880 880
};
881
    
881
   
882 882
static GenOpFunc1 *gen_op_jz_ecx[3] = {
883 883
    gen_op_jz_ecxw,
884 884
    gen_op_jz_ecxl,
......
966 966
    if (s->aflag == 2) {
967 967
        gen_op_addq_ESI_T0();
968 968
        gen_op_addq_EDI_T0();
969
    } else 
969
    } else
970 970
#endif
971 971
    if (s->aflag) {
972 972
        gen_op_addl_ESI_T0();
......
1009 1009
#ifdef TARGET_X86_64
1010 1010
    if (s->aflag == 2) {
1011 1011
        gen_op_addq_EDI_T0();
1012
    } else 
1012
    } else
1013 1013
#endif
1014 1014
    if (s->aflag) {
1015 1015
        gen_op_addl_EDI_T0();
......
1027 1027
#ifdef TARGET_X86_64
1028 1028
    if (s->aflag == 2) {
1029 1029
        gen_op_addq_ESI_T0();
1030
    } else 
1030
    } else
1031 1031
#endif
1032 1032
    if (s->aflag) {
1033 1033
        gen_op_addl_ESI_T0();
......
1046 1046
#ifdef TARGET_X86_64
1047 1047
    if (s->aflag == 2) {
1048 1048
        gen_op_addq_EDI_T0();
1049
    } else 
1049
    } else
1050 1050
#endif
1051 1051
    if (s->aflag) {
1052 1052
        gen_op_addl_EDI_T0();
......
1067 1067
    if (s->aflag == 2) {
1068 1068
        gen_op_addq_ESI_T0();
1069 1069
        gen_op_addq_EDI_T0();
1070
    } else 
1070
    } else
1071 1071
#endif
1072 1072
    if (s->aflag) {
1073 1073
        gen_op_addl_ESI_T0();
......
1089 1089
#ifdef TARGET_X86_64
1090 1090
    if (s->aflag == 2) {
1091 1091
        gen_op_addq_EDI_T0();
1092
    } else 
1092
    } else
1093 1093
#endif
1094 1094
    if (s->aflag) {
1095 1095
        gen_op_addl_EDI_T0();
......
1107 1107
#ifdef TARGET_X86_64
1108 1108
    if (s->aflag == 2) {
1109 1109
        gen_op_addq_ESI_T0();
1110
    } else 
1110
    } else
1111 1111
#endif
1112 1112
    if (s->aflag) {
1113 1113
        gen_op_addl_ESI_T0();
......
1318 1318
static void gen_op(DisasContext *s1, int op, int ot, int d)
1319 1319
{
1320 1320
    GenOpFunc *gen_update_cc;
1321
    
1321
   
1322 1322
    if (d != OR_TMP0) {
1323 1323
        gen_op_mov_TN_reg[ot][0][d]();
1324 1324
    } else {
......
1408 1408
    /* for zero counts, flags are not updated, so must do it dynamically */
1409 1409
    if (s1->cc_op != CC_OP_DYNAMIC)
1410 1410
        gen_op_set_cc_op(s1->cc_op);
1411
    
1411
   
1412 1412
    if (d != OR_TMP0)
1413 1413
        gen_op_shift_T0_T1_cc[ot][op]();
1414 1414
    else
......
1448 1448
        base = rm;
1449 1449
        index = 0;
1450 1450
        scale = 0;
1451
        
1451
       
1452 1452
        if (base == 4) {
1453 1453
            havesib = 1;
1454 1454
            code = ldub_code(s->pc++);
......
1480 1480
            s->pc += 4;
1481 1481
            break;
1482 1482
        }
1483
        
1483
       
1484 1484
        if (base >= 0) {
1485 1485
            /* for correct popl handling with esp */
1486 1486
            if (base == 4 && s->popl_esp_hack)
......
1494 1494
                    else
1495 1495
                        gen_op_addq_A0_im64(disp >> 32, disp);
1496 1496
                }
1497
            } else 
1497
            } else
1498 1498
#endif
1499 1499
            {
1500 1500
                gen_op_movl_A0_reg[base]();
......
1508 1508
                    gen_op_movq_A0_im(disp);
1509 1509
                else
1510 1510
                    gen_op_movq_A0_im64(disp >> 32, disp);
1511
            } else 
1511
            } else
1512 1512
#endif
1513 1513
            {
1514 1514
                gen_op_movl_A0_im(disp);
......
1519 1519
#ifdef TARGET_X86_64
1520 1520
            if (s->aflag == 2) {
1521 1521
                gen_op_addq_A0_reg_sN[scale][index]();
1522
            } else 
1522
            } else
1523 1523
#endif
1524 1524
            {
1525 1525
                gen_op_addl_A0_reg_sN[scale][index]();
......
1535 1535
#ifdef TARGET_X86_64
1536 1536
            if (s->aflag == 2) {
1537 1537
                gen_op_addq_A0_seg(offsetof(CPUX86State,segs[override].base));
1538
            } else 
1538
            } else
1539 1539
#endif
1540 1540
            {
1541 1541
                gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
......
1627 1627
    if (s->aflag) {
1628 1628

  
1629 1629
        base = rm;
1630
        
1630
       
1631 1631
        if (base == 4) {
1632 1632
            code = ldub_code(s->pc++);
1633 1633
            base = (code & 7);
1634 1634
        }
1635
        
1635
       
1636 1636
        switch (mod) {
1637 1637
        case 0:
1638 1638
            if (base == 5) {
......
1681 1681
#ifdef TARGET_X86_64
1682 1682
        if (CODE64(s)) {
1683 1683
            gen_op_addq_A0_seg(offsetof(CPUX86State,segs[override].base));
1684
        } else 
1684
        } else
1685 1685
#endif
1686 1686
        {
1687 1687
            gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
......
1776 1776
    }
1777 1777
}
1778 1778

  
1779
static inline void gen_jcc(DisasContext *s, int b, 
1779
static inline void gen_jcc(DisasContext *s, int b,
1780 1780
                           target_ulong val, target_ulong next_eip)
1781 1781
{
1782 1782
    TranslationBlock *tb;
......
1787 1787

  
1788 1788
    inv = b & 1;
1789 1789
    jcc_op = (b >> 1) & 7;
1790
    
1790
   
1791 1791
    if (s->jmp_opt) {
1792 1792
        switch(s->cc_op) {
1793 1793
            /* we optimize the cmp/jcc case */
......
1797 1797
        case CC_OP_SUBQ:
1798 1798
            func = gen_jcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
1799 1799
            break;
1800
            
1800
           
1801 1801
            /* some jumps are easy to compute */
1802 1802
        case CC_OP_ADDB:
1803 1803
        case CC_OP_ADDW:
......
1864 1864
            gen_setcc_slow[jcc_op]();
1865 1865
            func = gen_op_jnz_T0_label;
1866 1866
        }
1867
    
1867
   
1868 1868
        if (inv) {
1869 1869
            tmp = val;
1870 1870
            val = next_eip;
......
1922 1922
        if (!func)
1923 1923
            goto slow_jcc;
1924 1924
        break;
1925
        
1925
       
1926 1926
        /* some jumps are easy to compute */
1927 1927
    case CC_OP_ADDB:
1928 1928
    case CC_OP_ADDW:
......
2001 2001
    if (CODE64(s)) {
2002 2002
        if (addend == 8)
2003 2003
            gen_op_addq_ESP_8();
2004
        else 
2004
        else
2005 2005
            gen_op_addq_ESP_im(addend);
2006 2006
    } else
2007 2007
#endif
......
2010 2010
            gen_op_addl_ESP_2();
2011 2011
        else if (addend == 4)
2012 2012
            gen_op_addl_ESP_4();
2013
        else 
2013
        else
2014 2014
            gen_op_addl_ESP_im(addend);
2015 2015
    } else {
2016 2016
        if (addend == 2)
......
2036 2036
            gen_op_st_T0_A0[OT_WORD + s->mem_index]();
2037 2037
        }
2038 2038
        gen_op_movq_ESP_A0();
2039
    } else 
2039
    } else
2040 2040
#endif
2041 2041
    {
2042 2042
        gen_op_movl_A0_reg[R_ESP]();
......
2077 2077
            gen_op_st_T0_A0[OT_WORD + s->mem_index]();
2078 2078
        }
2079 2079
        gen_op_movq_ESP_A0();
2080
    } else 
2080
    } else
2081 2081
#endif
2082 2082
    {
2083 2083
        gen_op_movl_A0_reg[R_ESP]();
......
2094 2094
            gen_op_addl_A0_SS();
2095 2095
        }
2096 2096
        gen_op_st_T1_A0[s->dflag + 1 + s->mem_index]();
2097
        
2097
       
2098 2098
        if (s->ss32 && !s->addseg)
2099 2099
            gen_op_movl_ESP_A0();
2100 2100
        else
......
2109 2109
    if (CODE64(s)) {
2110 2110
        gen_op_movq_A0_reg[R_ESP]();
2111 2111
        gen_op_ld_T0_A0[(s->dflag ? OT_QUAD : OT_WORD) + s->mem_index]();
2112
    } else 
2112
    } else
2113 2113
#endif
2114 2114
    {
2115 2115
        gen_op_movl_A0_reg[R_ESP]();
......
2196 2196
    if (CODE64(s)) {
2197 2197
        ot = s->dflag ? OT_QUAD : OT_WORD;
2198 2198
        opsize = 1 << ot;
2199
        
2199
       
2200 2200
        gen_op_movl_A0_ESP();
2201 2201
        gen_op_addq_A0_im(-opsize);
2202 2202
        gen_op_movl_T1_A0();
......
2210 2210
        gen_op_mov_reg_T1[ot][R_EBP]();
2211 2211
        gen_op_addl_T1_im( -esp_addend + (-opsize * level) );
2212 2212
        gen_op_mov_reg_T1[OT_QUAD][R_ESP]();
2213
    } else 
2213
    } else
2214 2214
#endif
2215 2215
    {
2216 2216
        ot = s->dflag + OT_WORD;
2217 2217
        opsize = 2 << s->dflag;
2218
        
2218
       
2219 2219
        gen_op_movl_A0_ESP();
2220 2220
        gen_op_addl_A0_im(-opsize);
2221 2221
        if (!s->ss32)
......
2246 2246

  
2247 2247
/* an interrupt is different from an exception because of the
2248 2248
   privilege checks */
2249
static void gen_interrupt(DisasContext *s, int intno, 
2249
static void gen_interrupt(DisasContext *s, int intno,
2250 2250
                          target_ulong cur_eip, target_ulong next_eip)
2251 2251
{
2252 2252
    if (s->cc_op != CC_OP_DYNAMIC)
......
2309 2309

  
2310 2310
static void gen_movtl_T0_im(target_ulong val)
2311 2311
{
2312
#ifdef TARGET_X86_64    
2312
#ifdef TARGET_X86_64   
2313 2313
    if ((int32_t)val == val) {
2314 2314
        gen_op_movl_T0_im(val);
2315 2315
    } else {
......
2322 2322

  
2323 2323
static void gen_movtl_T1_im(target_ulong val)
2324 2324
{
2325
#ifdef TARGET_X86_64    
2325
#ifdef TARGET_X86_64   
2326 2326
    if ((int32_t)val == val) {
2327 2327
        gen_op_movl_T1_im(val);
2328 2328
    } else {
......
2410 2410
    [0x57] = { gen_op_pxor_xmm, gen_op_pxor_xmm }, /* xorps, xorpd */
2411 2411
    [0x58] = SSE_FOP(add),
2412 2412
    [0x59] = SSE_FOP(mul),
2413
    [0x5a] = { gen_op_cvtps2pd, gen_op_cvtpd2ps, 
2413
    [0x5a] = { gen_op_cvtps2pd, gen_op_cvtpd2ps,
2414 2414
               gen_op_cvtss2sd, gen_op_cvtsd2ss },
2415 2415
    [0x5b] = { gen_op_cvtdq2ps, gen_op_cvtps2dq, gen_op_cvttps2dq },
2416 2416
    [0x5c] = SSE_FOP(sub),
......
2438 2438
    [0x6d] = { NULL, gen_op_punpckhqdq_xmm },
2439 2439
    [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */
2440 2440
    [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */
2441
    [0x70] = { (GenOpFunc2 *)gen_op_pshufw_mmx, 
2442
               (GenOpFunc2 *)gen_op_pshufd_xmm, 
2443
               (GenOpFunc2 *)gen_op_pshufhw_xmm, 
2441
    [0x70] = { (GenOpFunc2 *)gen_op_pshufw_mmx,
2442
               (GenOpFunc2 *)gen_op_pshufd_xmm,
2443
               (GenOpFunc2 *)gen_op_pshufhw_xmm,
2444 2444
               (GenOpFunc2 *)gen_op_pshuflw_xmm },
2445 2445
    [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */
2446 2446
    [0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */
......
2522 2522
    gen_op_cvtsi2sd,
2523 2523
    X86_64_ONLY(gen_op_cvtsq2ss),
2524 2524
    X86_64_ONLY(gen_op_cvtsq2sd),
2525
    
2525
   
2526 2526
    gen_op_cvttss2si,
2527 2527
    gen_op_cvttsd2si,
2528 2528
    X86_64_ONLY(gen_op_cvttss2sq),
......
2533 2533
    X86_64_ONLY(gen_op_cvtss2sq),
2534 2534
    X86_64_ONLY(gen_op_cvtsd2sq),
2535 2535
};
2536
    
2536
   
2537 2537
static GenOpFunc2 *sse_op_table4[8][4] = {
2538 2538
    SSE_FOP(cmpeq),
2539 2539
    SSE_FOP(cmplt),
......
2544 2544
    SSE_FOP(cmpnle),
2545 2545
    SSE_FOP(cmpord),
2546 2546
};
2547
    
2547
   
2548 2548
static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
2549 2549
{
2550 2550
    int b1, op1_offset, op2_offset, is_xmm, val, ot;
......
2553 2553
    GenOpFunc3 *sse_op3;
2554 2554

  
2555 2555
    b &= 0xff;
2556
    if (s->prefix & PREFIX_DATA) 
2556
    if (s->prefix & PREFIX_DATA)
2557 2557
        b1 = 1;
2558
    else if (s->prefix & PREFIX_REPZ) 
2558
    else if (s->prefix & PREFIX_REPZ)
2559 2559
        b1 = 2;
2560
    else if (s->prefix & PREFIX_REPNZ) 
2560
    else if (s->prefix & PREFIX_REPNZ)
2561 2561
        b1 = 3;
2562 2562
    else
2563 2563
        b1 = 0;
2564 2564
    sse_op2 = sse_op_table1[b][b1];
2565
    if (!sse_op2) 
2565
    if (!sse_op2)
2566 2566
        goto illegal_op;
2567 2567
    if (b <= 0x5f || b == 0xc6 || b == 0xc2) {
2568 2568
        is_xmm = 1;
......
2606 2606
        b |= (b1 << 8);
2607 2607
        switch(b) {
2608 2608
        case 0x0e7: /* movntq */
2609
            if (mod == 3) 
2609
            if (mod == 3)
2610 2610
                goto illegal_op;
2611 2611
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2612 2612
            gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,fpregs[reg].mmx));
......
2625 2625
            if (s->dflag == 2) {
2626 2626
                gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
2627 2627
                gen_op_movq_mm_T0_mmx(offsetof(CPUX86State,fpregs[reg].mmx));
2628
            } else 
2628
            } else
2629 2629
#endif
2630 2630
            {
2631 2631
                gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
......
2637 2637
            if (s->dflag == 2) {
2638 2638
                gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
2639 2639
                gen_op_movq_mm_T0_xmm(offsetof(CPUX86State,xmm_regs[reg]));
2640
            } else 
2640
            } else
2641 2641
#endif
2642 2642
            {
2643 2643
                gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
......
2770 2770
            if (s->dflag == 2) {
2771 2771
                gen_op_movq_T0_mm_mmx(offsetof(CPUX86State,fpregs[reg].mmx));
2772 2772
                gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
2773
            } else 
2773
            } else
2774 2774
#endif
2775 2775
            {
2776 2776
                gen_op_movl_T0_mm_mmx(offsetof(CPUX86State,fpregs[reg].mmx));
......
2782 2782
            if (s->dflag == 2) {
2783 2783
                gen_op_movq_T0_mm_xmm(offsetof(CPUX86State,xmm_regs[reg]));
2784 2784
                gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
2785
            } else 
2785
            } else
2786 2786
#endif
2787 2787
            {
2788 2788
                gen_op_movl_T0_mm_xmm(offsetof(CPUX86State,xmm_regs[reg]));
......
2982 2982
                rm = (modrm & 7) | REX_B(s);
2983 2983
                op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
2984 2984
            }
2985
            sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2) + 4 + 
2985
            sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2) + 4 +
2986 2986
                          (b & 1) * 4](op2_offset);
2987 2987
            gen_op_mov_reg_T0[ot][reg]();
2988 2988
            break;
2989 2989
        case 0xc4: /* pinsrw */
2990
        case 0x1c4: 
2990
        case 0x1c4:
2991 2991
            s->rip_offset = 1;
2992 2992
            gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
2993 2993
            val = ldub_code(s->pc++);
......
3000 3000
            }
3001 3001
            break;
3002 3002
        case 0xc5: /* pextrw */
3003
        case 0x1c5: 
3003
        case 0x1c5:
3004 3004
            if (mod != 3)
3005 3005
                goto illegal_op;
3006 3006
            val = ldub_code(s->pc++);
......
3062 3062
        switch(b) {
3063 3063
        case 0xf7:
3064 3064
            /* maskmov : we must prepare A0 */
3065
            if (mod != 3) 
3065
            if (mod != 3)
3066 3066
                goto illegal_op;
3067 3067
#ifdef TARGET_X86_64
3068 3068
            if (s->aflag == 2) {
3069 3069
                gen_op_movq_A0_reg[R_EDI]();
3070
            } else 
3070
            } else
3071 3071
#endif
3072 3072
            {
3073 3073
                gen_op_movl_A0_reg[R_EDI]();
......
3164 3164
#ifdef TARGET_X86_64
3165 3165
    s->rex_x = 0;
3166 3166
    s->rex_b = 0;
3167
    x86_64_hregs = 0; 
3167
    x86_64_hregs = 0;
3168 3168
#endif
3169 3169
    s->rip_offset = 0; /* for relative ip address */
3170 3170
 next_byte:
......
3225 3225
        }
3226 3226
        if (!(prefixes & PREFIX_ADR))
3227 3227
            aflag = 2;
3228
    } else 
3228
    } else
3229 3229
#endif
3230 3230
    {
3231 3231
        switch (b) {
......
3285 3285
        /* extended op code */
3286 3286
        b = ldub_code(s->pc++) | 0x100;
3287 3287
        goto reswitch;
3288
        
3288
       
3289 3289
        /**************************/
3290 3290
        /* arith & logic */
3291 3291
    case 0x00 ... 0x05:
......
3305 3305
                ot = OT_BYTE;
3306 3306
            else
3307 3307
                ot = dflag + OT_WORD;
3308
            
3308
           
3309 3309
            switch(f) {
3310 3310
            case 0: /* OP Ev, Gv */
3311 3311
                modrm = ldub_code(s->pc++);
......
3364 3364
                ot = OT_BYTE;
3365 3365
            else
3366 3366
                ot = dflag + OT_WORD;
3367
            
3367
           
3368 3368
            modrm = ldub_code(s->pc++);
3369 3369
            mod = (modrm >> 6) & 3;
3370 3370
            rm = (modrm & 7) | REX_B(s);
3371 3371
            op = (modrm >> 3) & 7;
3372
            
3372
           
3373 3373
            if (mod != 3) {
3374 3374
                if (b == 0x83)
3375 3375
                    s->rip_offset = 1;
......
3656 3656
        break;
3657 3657

  
3658 3658
    case 0x84: /* test Ev, Gv */
3659
    case 0x85: 
3659
    case 0x85:
3660 3660
        if ((b & 1) == 0)
3661 3661
            ot = OT_BYTE;
3662 3662
        else
......
3666 3666
        mod = (modrm >> 6) & 3;
3667 3667
        rm = (modrm & 7) | REX_B(s);
3668 3668
        reg = ((modrm >> 3) & 7) | rex_r;
3669
        
3669
       
3670 3670
        gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3671 3671
        gen_op_mov_TN_reg[ot][1][reg]();
3672 3672
        gen_op_testl_T0_T1_cc();
3673 3673
        s->cc_op = CC_OP_LOGICB + ot;
3674 3674
        break;
3675
        
3675
       
3676 3676
    case 0xa8: /* test eAX, Iv */
3677 3677
    case 0xa9:
3678 3678
        if ((b & 1) == 0)
......
3686 3686
        gen_op_testl_T0_T1_cc();
3687 3687
        s->cc_op = CC_OP_LOGICB + ot;
3688 3688
        break;
3689
        
3689
       
3690 3690
    case 0x98: /* CWDE/CBW */
3691 3691
#ifdef TARGET_X86_64
3692 3692
        if (dflag == 2) {
......
3804 3804
        gen_op_cmpxchg8b();
3805 3805
        s->cc_op = CC_OP_EFLAGS;
3806 3806
        break;
3807
        
3807
       
3808 3808
        /**************************/
3809 3809
        /* push/pop */
3810 3810
    case 0x50 ... 0x57: /* push */
......
3955 3955
            ot = dflag + OT_WORD;
3956 3956
        modrm = ldub_code(s->pc++);
3957 3957
        reg = ((modrm >> 3) & 7) | rex_r;
3958
        
3958
       
3959 3959
        /* generate a generic store */
3960 3960
        gen_ldst_modrm(s, modrm, ot, reg, 1);
3961 3961
        break;
......
3986 3986
            ot = OT_WORD + dflag;
3987 3987
        modrm = ldub_code(s->pc++);
3988 3988
        reg = ((modrm >> 3) & 7) | rex_r;
3989
        
3989
       
3990 3990
        gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3991 3991
        gen_op_mov_reg_T0[ot][reg]();
3992 3992
        break;
......
4038 4038
            reg = ((modrm >> 3) & 7) | rex_r;
4039 4039
            mod = (modrm >> 6) & 3;
4040 4040
            rm = (modrm & 7) | REX_B(s);
4041
            
4041
           
4042 4042
            if (mod == 3) {
4043 4043
                gen_op_mov_TN_reg[ot][0][rm]();
4044 4044
                switch(ot | (b & 8)) {
......
4084 4084
        s->addseg = val;
4085 4085
        gen_op_mov_reg_A0[ot - OT_WORD][reg]();
4086 4086
        break;
4087
        
4087
       
4088 4088
    case 0xa0: /* mov EAX, Ov */
4089 4089
    case 0xa1:
4090 4090
    case 0xa2: /* mov Ov, EAX */
......
4104 4104
                    gen_op_movq_A0_im(offset_addr);
4105 4105
                else
4106 4106
                    gen_op_movq_A0_im64(offset_addr >> 32, offset_addr);
4107
            } else 
4107
            } else
4108 4108
#endif
4109 4109
            {
4110 4110
                if (s->aflag) {
......
4129 4129
        if (s->aflag == 2) {
4130 4130
            gen_op_movq_A0_reg[R_EBX]();
4131 4131
            gen_op_addq_A0_AL();
4132
        } else 
4132
        } else
4133 4133
#endif
4134 4134
        {
4135 4135
            gen_op_movl_A0_reg[R_EBX]();
......
4156 4156
            reg = (b & 7) | REX_B(s);
4157 4157
            gen_movtl_T0_im(tmp);
4158 4158
            gen_op_mov_reg_T0[OT_QUAD][reg]();
4159
        } else 
4159
        } else
4160 4160
#endif
4161 4161
        {
4162 4162
            ot = dflag ? OT_LONG : OT_WORD;
......
4239 4239
            gen_eob(s);
4240 4240
        }
4241 4241
        break;
4242
        
4242
       
4243 4243
        /************************/
4244 4244
        /* shifts */
4245 4245
    case 0xc0:
......
4252 4252
                ot = OT_BYTE;
4253 4253
            else
4254 4254
                ot = dflag + OT_WORD;
4255
            
4255
           
4256 4256
            modrm = ldub_code(s->pc++);
4257 4257
            mod = (modrm >> 6) & 3;
4258 4258
            op = (modrm >> 3) & 7;
4259
            
4259
           
4260 4260
            if (mod != 3) {
4261 4261
                if (shift == 2) {
4262 4262
                    s->rip_offset = 1;
......
4310 4310
        mod = (modrm >> 6) & 3;
4311 4311
        rm = (modrm & 7) | REX_B(s);
4312 4312
        reg = ((modrm >> 3) & 7) | rex_r;
4313
        
4313
       
4314 4314
        if (mod != 3) {
4315 4315
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4316 4316
            gen_op_ld_T0_A0[ot + s->mem_index]();
......
4318 4318
            gen_op_mov_TN_reg[ot][0][rm]();
4319 4319
        }
4320 4320
        gen_op_mov_TN_reg[ot][1][reg]();
4321
        
4321
       
4322 4322
        if (shift) {
4323 4323
            val = ldub_code(s->pc++);
4324 4324
            if (ot == OT_QUAD)
......
4351 4351

  
4352 4352
        /************************/
4353 4353
        /* floats */
4354
    case 0xd8 ... 0xdf: 
4354
    case 0xd8 ... 0xdf:
4355 4355
        if (s->flags & (HF_EM_MASK | HF_TS_MASK)) {
4356 4356
            /* if CR0.EM or CR0.TS are set, generate an FPU exception */
4357 4357
            /* XXX: what to do if illegal op ? */
......
4389 4389
                        gen_op_fild_FT0_A0();
4390 4390
                        break;
4391 4391
                    }
4392
                    
4392
                   
4393 4393
                    gen_op_fp_arith_ST0_FT0[op1]();
4394 4394
                    if (op1 == 3) {
4395 4395
                        /* fcomp needs pop */
......
4646 4646
            case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
4647 4647
                {
4648 4648
                    int op1;
4649
                    
4649
                   
4650 4650
                    op1 = op & 7;
4651 4651
                    if (op >= 0x20) {
4652 4652
                        gen_op_fp_arith_STN_ST0[op1](opreg);
......
4716 4716
                break;
4717 4717
            case 0x28: /* ffree sti */
4718 4718
                gen_op_ffree_STN(opreg);
4719
                break; 
4719
                break;
4720 4720
            case 0x2a: /* fst sti */
4721 4721
                gen_op_fmov_STN_ST0(opreg);
4722 4722
                break;
......
4816 4816
            gen_movs(s, ot);
4817 4817
        }
4818 4818
        break;
4819
        
4819
       
4820 4820
    case 0xaa: /* stosS */
4821 4821
    case 0xab:
4822 4822
        if ((b & 1) == 0)
......
5042 5042
    case 0x9a: /* lcall im */
5043 5043
        {
5044 5044
            unsigned int selector, offset;
5045
            
5045
           
5046 5046
            if (CODE64(s))
5047 5047
                goto illegal_op;
5048 5048
            ot = dflag ? OT_LONG : OT_WORD;
5049 5049
            offset = insn_get(s, ot);
5050 5050
            selector = insn_get(s, OT_WORD);
5051
            
5051
           
5052 5052
            gen_op_movl_T0_im(selector);
5053 5053
            gen_op_movl_T1_imu(offset);
5054 5054
        }
......
5072 5072
            ot = dflag ? OT_LONG : OT_WORD;
5073 5073
            offset = insn_get(s, ot);
5074 5074
            selector = insn_get(s, OT_WORD);
5075
            
5075
           
5076 5076
            gen_op_movl_T0_im(selector);
5077 5077
            gen_op_movl_T1_imu(offset);
5078 5078
        }
......
5091 5091
        if (dflag) {
5092 5092
            tval = (int32_t)insn_get(s, OT_LONG);
5093 5093
        } else {
5094
            tval = (int16_t)insn_get(s, OT_WORD); 
5094
            tval = (int16_t)insn_get(s, OT_WORD);
5095 5095
        }
5096 5096
    do_jcc:
5097 5097
        next_eip = s->pc - s->cs_base;
......
5121 5121
        }
5122 5122
        gen_op_cmov_reg_T1_T0[ot - OT_WORD][reg]();
5123 5123
        break;
5124
        
5124
       
5125 5125
        /************************/
5126 5126
        /* flags */
5127 5127
    case 0x9c: /* pushf */
......
5350 5350
            goto illegal_op;
5351 5351
        break;
5352 5352
    case 0x9b: /* fwait */
5353
        if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) == 
5353
        if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) ==
5354 5354
            (HF_MP_MASK | HF_TS_MASK)) {
5355 5355
            gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
5356 5356
        } else {
......
5366 5366
    case 0xcd: /* int N */
5367 5367
        val = ldub_code(s->pc++);
5368 5368
        if (s->vm86 && s->iopl != 3) {
5369
            gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); 
5369
            gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5370 5370
        } else {
5371 5371
            gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
5372 5372
        }
......
5451 5451
            gen_op_mov_TN_reg[OT_QUAD][0][reg]();
5452 5452
            gen_op_bswapq_T0();
5453 5453
            gen_op_mov_reg_T0[OT_QUAD][reg]();
5454
        } else 
5454
        } else
5455 5455
#endif
5456 5456
        {
5457 5457
            gen_op_mov_TN_reg[OT_LONG][0][reg]();
......
5481 5481
            tval += next_eip;
5482 5482
            if (s->dflag == 0)
5483 5483
                tval &= 0xffff;
5484
            
5484
           
5485 5485
            l1 = gen_new_label();
5486 5486
            l2 = gen_new_label();
5487 5487
            b &= 3;
......
5681 5681
                    if (s->aflag == 2) {
5682 5682
                        gen_op_movq_A0_reg[R_EBX]();
5683 5683
                        gen_op_addq_A0_AL();
5684
                    } else 
5684
                    } else
5685 5685
#endif
5686 5686
                    {
5687 5687
                        gen_op_movl_A0_reg[R_EBX]();
......
5766 5766
                        gen_op_movtl_T1_env(offsetof(CPUX86State,kernelgsbase));
5767 5767
                        gen_op_movtl_env_T1(offsetof(CPUX86State,segs[R_GS].base));
5768 5768
                        gen_op_movtl_env_T0(offsetof(CPUX86State,kernelgsbase));
5769
                    } else 
5769
                    } else
5770 5770
#endif
5771 5771
                    {
5772 5772
                        goto illegal_op;
......
5802 5802
            reg = ((modrm >> 3) & 7) | rex_r;
5803 5803
            mod = (modrm >> 6) & 3;
5804 5804
            rm = (modrm & 7) | REX_B(s);
5805
            
5805
           
5806 5806
            if (mod == 3) {
5807 5807
                gen_op_mov_TN_reg[OT_LONG][0][rm]();
5808 5808
                /* sign extend */
......
5818 5818
                }
5819 5819
                gen_op_mov_reg_T0[d_ot][reg]();
5820 5820
            }
5821
        } else 
5821
        } else
5822 5822
#endif
5823 5823
        {
5824 5824
            if (!s->pe || s->vm86)
......
5913 5913
                    gen_jmp_im(s->pc - s->cs_base);
5914 5914
                    gen_eob(s);
5915 5915
                } else {
5916
#if !defined(CONFIG_USER_ONLY) 
5916
#if !defined(CONFIG_USER_ONLY)
5917 5917
                    if (reg == 8)
5918 5918
                        gen_op_movtl_T0_cr8();
5919 5919
                    else
......
5984 5984
        op = (modrm >> 3) & 7;
5985 5985
        switch(op) {
5986 5986
        case 0: /* fxsave */
5987
            if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) || 
5987
            if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
5988 5988
                (s->flags & HF_EM_MASK))
5989 5989
                goto illegal_op;
5990 5990
            if (s->flags & HF_TS_MASK) {
......
5995 5995
            gen_op_fxsave_A0((s->dflag == 2));
5996 5996
            break;
5997 5997
        case 1: /* fxrstor */
5998
            if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) || 
5998
            if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
5999 5999
                (s->flags & HF_EM_MASK))
6000 6000
                goto illegal_op;
6001 6001
            if (s->flags & HF_TS_MASK) {
......
6088 6088
#define CC_OSZAP (CC_O | CC_S | CC_Z | CC_A | CC_P)
6089 6089

  
6090 6090
/* flags read by an operation */
6091
static uint16_t opc_read_flags[NB_OPS] = { 
6091
static uint16_t opc_read_flags[NB_OPS] = {
6092 6092
    [INDEX_op_aas] = CC_A,
6093 6093
    [INDEX_op_aaa] = CC_A,
6094 6094
    [INDEX_op_das] = CC_A | CC_C,
6095 6095
    [INDEX_op_daa] = CC_A | CC_C,
6096 6096

  
6097 6097
    /* subtle: due to the incl/decl implementation, C is used */
6098
    [INDEX_op_update_inc_cc] = CC_C, 
6098
    [INDEX_op_update_inc_cc] = CC_C,
6099 6099

  
6100 6100
    [INDEX_op_into] = CC_O,
6101 6101

  
......
6221 6221
};
6222 6222

  
6223 6223
/* flags written by an operation */
6224
static uint16_t opc_write_flags[NB_OPS] = { 
6224
static uint16_t opc_write_flags[NB_OPS] = {
6225 6225
    [INDEX_op_update2_cc] = CC_OSZAPC,
6226 6226
    [INDEX_op_update1_cc] = CC_OSZAPC,
6227 6227
    [INDEX_op_cmpl_T0_T1_cc] = CC_OSZAPC,
6228 6228
    [INDEX_op_update_neg_cc] = CC_OSZAPC,
6229 6229
    /* subtle: due to the incl/decl implementation, C is used */
6230
    [INDEX_op_update_inc_cc] = CC_OSZAPC, 
6230
    [INDEX_op_update_inc_cc] = CC_OSZAPC,
6231 6231
    [INDEX_op_testl_T0_T1_cc] = CC_OSZAPC,
6232 6232

  
6233 6233
    [INDEX_op_mulb_AL_T0] = CC_OSZAPC,
......
6372 6372
};
6373 6373

  
6374 6374
/* simpler form of an operation if no flags need to be generated */
6375
static uint16_t opc_simpler[NB_OPS] = { 
6375
static uint16_t opc_simpler[NB_OPS] = {
6376 6376
    [INDEX_op_update2_cc] = INDEX_op_nop,
6377 6377
    [INDEX_op_update1_cc] = INDEX_op_nop,
6378 6378
    [INDEX_op_update_neg_cc] = INDEX_op_nop,
......
6456 6456
   basic block 'tb'. If search_pc is TRUE, also generate PC
6457 6457
   information for each intermediate instruction. */
6458 6458
static inline int gen_intermediate_code_internal(CPUState *env,
6459
                                                 TranslationBlock *tb, 
6459
                                                 TranslationBlock *tb,
6460 6460
                                                 int search_pc)
6461 6461
{
6462 6462
    DisasContext dc1, *dc = &dc1;
......
6465 6465
    int flags, j, lj, cflags;
6466 6466
    target_ulong pc_start;
6467 6467
    target_ulong cs_base;
6468
    
6468
   
6469 6469
    /* generate intermediate code */
6470 6470
    pc_start = tb->pc;
6471 6471
    cs_base = tb->cs_base;
......
6551 6551
        /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
6552 6552
           the flag and abort the translation to give the irqs a
6553 6553
           change to be happen */
6554
        if (dc->tf || dc->singlestep_enabled || 
6554
        if (dc->tf || dc->singlestep_enabled ||
6555 6555
            (flags & HF_INHIBIT_IRQ_MASK) ||
6556 6556
            (cflags & CF_SINGLE_INSN)) {
6557 6557
            gen_jmp_im(pc_ptr - dc->cs_base);
......
6574 6574
        while (lj <= j)
6575 6575
            gen_opc_instr_start[lj++] = 0;
6576 6576
    }
6577
        
6577
       
6578 6578
#ifdef DEBUG_DISAS
6579 6579
    if (loglevel & CPU_LOG_TB_CPU) {
6580 6580
        cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);

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