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/*
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 * dyngen helpers
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 *
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 *  Copyright (c) 2003 Fabrice Bellard
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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int __op_param1, __op_param2, __op_param3;
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#if defined(__sparc__) || defined(__arm__)
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  void __op_gen_label1(){}
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  void __op_gen_label2(){}
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  void __op_gen_label3(){}
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#else
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  int __op_gen_label1, __op_gen_label2, __op_gen_label3;
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#endif
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int __op_jmp0, __op_jmp1, __op_jmp2, __op_jmp3;
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#if defined(__i386__) || defined(__x86_64__) || defined(__s390__)
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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}
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#elif defined(__ia64__)
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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    while (start < stop) {
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        asm volatile ("fc %0" :: "r"(start));
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        start += 32;
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    }
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    asm volatile (";;sync.i;;srlz.i;;");
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}
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#elif defined(__powerpc__)
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#define MIN_CACHE_LINE_SIZE 8 /* conservative value */
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static void inline flush_icache_range(unsigned long start, unsigned long stop)
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{
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    unsigned long p;
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    start &= ~(MIN_CACHE_LINE_SIZE - 1);
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    stop = (stop + MIN_CACHE_LINE_SIZE - 1) & ~(MIN_CACHE_LINE_SIZE - 1);
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    for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
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        asm volatile ("dcbst 0,%0" : : "r"(p) : "memory");
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    }
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    asm volatile ("sync" : : : "memory");
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    for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
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        asm volatile ("icbi 0,%0" : : "r"(p) : "memory");
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    }
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    asm volatile ("sync" : : : "memory");
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    asm volatile ("isync" : : : "memory");
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}
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#elif defined(__alpha__)
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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    asm ("imb");
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}
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#elif defined(__sparc__)
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static void inline flush_icache_range(unsigned long start, unsigned long stop)
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{
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        unsigned long p;
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        p = start & ~(8UL - 1UL);
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        stop = (stop + (8UL - 1UL)) & ~(8UL - 1UL);
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        for (; p < stop; p += 8)
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                __asm__ __volatile__("flush\t%0" : : "r" (p));
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}
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#elif defined(__arm__)
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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    register unsigned long _beg __asm ("a1") = start;
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    register unsigned long _end __asm ("a2") = stop;
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    register unsigned long _flg __asm ("a3") = 0;
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    __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
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}
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#elif defined(__mc68000)
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# include <asm/cachectl.h>
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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    cacheflush(start,FLUSH_SCOPE_LINE,FLUSH_CACHE_BOTH,stop-start+16);
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}
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#elif defined(__mips__)
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#include <sys/cachectl.h>
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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    _flush_cache ((void *)start, stop - start, BCACHE);
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}
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#else
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#error unsupported CPU
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#endif
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#ifdef __alpha__
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register int gp asm("$29");
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static inline void immediate_ldah(void *p, int val) {
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    uint32_t *dest = p;
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    long high = ((val >> 16) + ((val >> 15) & 1)) & 0xffff;
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    *dest &= ~0xffff;
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    *dest |= high;
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    *dest |= 31 << 16;
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}
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static inline void immediate_lda(void *dest, int val) {
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    *(uint16_t *) dest = val;
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}
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void fix_bsr(void *p, int offset) {
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    uint32_t *dest = p;
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    *dest &= ~((1 << 21) - 1);
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    *dest |= (offset >> 2) & ((1 << 21) - 1);
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}
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#endif /* __alpha__ */
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#ifdef __arm__
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#define ARM_LDR_TABLE_SIZE 1024
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typedef struct LDREntry {
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    uint8_t *ptr;
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    uint32_t *data_ptr;
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    unsigned type:2;
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} LDREntry;
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static LDREntry arm_ldr_table[1024];
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static uint32_t arm_data_table[ARM_LDR_TABLE_SIZE];
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extern char exec_loop;
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static inline void arm_reloc_pc24(uint32_t *ptr, uint32_t insn, int val)
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{
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    *ptr = (insn & ~0xffffff) | ((insn + ((val - (int)ptr) >> 2)) & 0xffffff);
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}
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static uint8_t *arm_flush_ldr(uint8_t *gen_code_ptr,
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                              LDREntry *ldr_start, LDREntry *ldr_end,
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                              uint32_t *data_start, uint32_t *data_end,
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                              int gen_jmp)
154
{
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    LDREntry *le;
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    uint32_t *ptr;
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    int offset, data_size, target;
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    uint8_t *data_ptr;
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    uint32_t insn;
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    uint32_t mask;
161

    
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    data_size = (data_end - data_start) << 2;
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    if (gen_jmp) {
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        /* generate branch to skip the data */
166
        if (data_size == 0)
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            return gen_code_ptr;
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        target = (long)gen_code_ptr + data_size + 4;
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        arm_reloc_pc24((uint32_t *)gen_code_ptr, 0xeafffffe, target);
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        gen_code_ptr += 4;
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    }
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    /* copy the data */
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    data_ptr = gen_code_ptr;
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    memcpy(gen_code_ptr, data_start, data_size);
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    gen_code_ptr += data_size;
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    /* patch the ldr to point to the data */
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    for(le = ldr_start; le < ldr_end; le++) {
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        ptr = (uint32_t *)le->ptr;
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        offset = ((unsigned long)(le->data_ptr) - (unsigned long)data_start) +
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            (unsigned long)data_ptr -
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            (unsigned long)ptr - 8;
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        if (offset < 0) {
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            fprintf(stderr, "Negative constant pool offset\n");
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            abort();
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        }
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        switch (le->type) {
189
          case 0: /* ldr */
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            mask = ~0x00800fff;
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            if (offset >= 4096) {
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                fprintf(stderr, "Bad ldr offset\n");
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                abort();
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            }
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            break;
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          case 1: /* ldc */
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            mask = ~0x008000ff;
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            if (offset >= 1024 ) {
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                fprintf(stderr, "Bad ldc offset\n");
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                abort();
201
            }
202
            break;
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          case 2: /* add */
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            mask = ~0xfff;
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            if (offset >= 1024 ) {
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                fprintf(stderr, "Bad add offset\n");
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                abort();
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            }
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            break;
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          default:
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            fprintf(stderr, "Bad pc relative fixup\n");
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            abort();
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          }
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        insn = *ptr & mask;
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        switch (le->type) {
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          case 0: /* ldr */
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            insn |= offset | 0x00800000;
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            break;
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          case 1: /* ldc */
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            insn |= (offset >> 2) | 0x00800000;
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            break;
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          case 2: /* add */
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            insn |= (offset >> 2) | 0xf00;
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            break;
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          }
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        *ptr = insn;
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    }
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    return gen_code_ptr;
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}
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#endif /* __arm__ */
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#ifdef __ia64
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/* Patch instruction with "val" where "mask" has 1 bits. */
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static inline void ia64_patch (uint64_t insn_addr, uint64_t mask, uint64_t val)
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{
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    uint64_t m0, m1, v0, v1, b0, b1, *b = (uint64_t *) (insn_addr & -16);
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#   define insn_mask ((1UL << 41) - 1)
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    unsigned long shift;
241

    
242
    b0 = b[0]; b1 = b[1];
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    shift = 5 + 41 * (insn_addr % 16); /* 5 template, 3 x 41-bit insns */
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    if (shift >= 64) {
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        m1 = mask << (shift - 64);
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        v1 = val << (shift - 64);
247
    } else {
248
        m0 = mask << shift; m1 = mask >> (64 - shift);
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        v0 = val  << shift; v1 = val >> (64 - shift);
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        b[0] = (b0 & ~m0) | (v0 & m0);
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    }
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    b[1] = (b1 & ~m1) | (v1 & m1);
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}
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static inline void ia64_patch_imm60 (uint64_t insn_addr, uint64_t val)
256
{
257
        ia64_patch(insn_addr,
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                   0x011ffffe000UL,
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                   (  ((val & 0x0800000000000000UL) >> 23) /* bit 59 -> 36 */
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                    | ((val & 0x00000000000fffffUL) << 13) /* bit 0 -> 13 */));
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        ia64_patch(insn_addr - 1, 0x1fffffffffcUL, val >> 18);
262
}
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264
static inline void ia64_imm64 (void *insn, uint64_t val)
265
{
266
    /* Ignore the slot number of the relocation; GCC and Intel
267
       toolchains differed for some time on whether IMM64 relocs are
268
       against slot 1 (Intel) or slot 2 (GCC).  */
269
    uint64_t insn_addr = (uint64_t) insn & ~3UL;
270

    
271
    ia64_patch(insn_addr + 2,
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               0x01fffefe000UL,
273
               (  ((val & 0x8000000000000000UL) >> 27) /* bit 63 -> 36 */
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                | ((val & 0x0000000000200000UL) <<  0) /* bit 21 -> 21 */
275
                | ((val & 0x00000000001f0000UL) <<  6) /* bit 16 -> 22 */
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                | ((val & 0x000000000000ff80UL) << 20) /* bit  7 -> 27 */
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                | ((val & 0x000000000000007fUL) << 13) /* bit  0 -> 13 */)
278
            );
279
    ia64_patch(insn_addr + 1, 0x1ffffffffffUL, val >> 22);
280
}
281

    
282
static inline void ia64_imm60b (void *insn, uint64_t val)
283
{
284
    /* Ignore the slot number of the relocation; GCC and Intel
285
       toolchains differed for some time on whether IMM64 relocs are
286
       against slot 1 (Intel) or slot 2 (GCC).  */
287
    uint64_t insn_addr = (uint64_t) insn & ~3UL;
288

    
289
    if (val + ((uint64_t) 1 << 59) >= (1UL << 60))
290
        fprintf(stderr, "%s: value %ld out of IMM60 range\n",
291
                __FUNCTION__, (int64_t) val);
292
    ia64_patch_imm60(insn_addr + 2, val);
293
}
294

    
295
static inline void ia64_imm22 (void *insn, uint64_t val)
296
{
297
    if (val + (1 << 21) >= (1 << 22))
298
        fprintf(stderr, "%s: value %li out of IMM22 range\n",
299
                __FUNCTION__, (int64_t)val);
300
    ia64_patch((uint64_t) insn, 0x01fffcfe000UL,
301
               (  ((val & 0x200000UL) << 15) /* bit 21 -> 36 */
302
                | ((val & 0x1f0000UL) <<  6) /* bit 16 -> 22 */
303
                | ((val & 0x00ff80UL) << 20) /* bit  7 -> 27 */
304
                | ((val & 0x00007fUL) << 13) /* bit  0 -> 13 */));
305
}
306

    
307
/* Like ia64_imm22(), but also clear bits 20-21.  For addl, this has
308
   the effect of turning "addl rX=imm22,rY" into "addl
309
   rX=imm22,r0".  */
310
static inline void ia64_imm22_r0 (void *insn, uint64_t val)
311
{
312
    if (val + (1 << 21) >= (1 << 22))
313
        fprintf(stderr, "%s: value %li out of IMM22 range\n",
314
                __FUNCTION__, (int64_t)val);
315
    ia64_patch((uint64_t) insn, 0x01fffcfe000UL | (0x3UL << 20),
316
               (  ((val & 0x200000UL) << 15) /* bit 21 -> 36 */
317
                | ((val & 0x1f0000UL) <<  6) /* bit 16 -> 22 */
318
                | ((val & 0x00ff80UL) << 20) /* bit  7 -> 27 */
319
                | ((val & 0x00007fUL) << 13) /* bit  0 -> 13 */));
320
}
321

    
322
static inline void ia64_imm21b (void *insn, uint64_t val)
323
{
324
    if (val + (1 << 20) >= (1 << 21))
325
        fprintf(stderr, "%s: value %li out of IMM21b range\n",
326
                __FUNCTION__, (int64_t)val);
327
    ia64_patch((uint64_t) insn, 0x11ffffe000UL,
328
               (  ((val & 0x100000UL) << 16) /* bit 20 -> 36 */
329
                | ((val & 0x0fffffUL) << 13) /* bit  0 -> 13 */));
330
}
331

    
332
static inline void ia64_nop_b (void *insn)
333
{
334
    ia64_patch((uint64_t) insn, (1UL << 41) - 1, 2UL << 37);
335
}
336

    
337
static inline void ia64_ldxmov(void *insn, uint64_t val)
338
{
339
    if (val + (1 << 21) < (1 << 22))
340
        ia64_patch((uint64_t) insn, 0x1fff80fe000UL, 8UL << 37);
341
}
342

    
343
static inline int ia64_patch_ltoff(void *insn, uint64_t val,
344
                                   int relaxable)
345
{
346
    if (relaxable && (val + (1 << 21) < (1 << 22))) {
347
        ia64_imm22_r0(insn, val);
348
        return 0;
349
    }
350
    return 1;
351
}
352

    
353
struct ia64_fixup {
354
    struct ia64_fixup *next;
355
    void *addr;                        /* address that needs to be patched */
356
    long value;
357
};
358

    
359
#define IA64_PLT(insn, plt_index)                        \
360
do {                                                        \
361
    struct ia64_fixup *fixup = alloca(sizeof(*fixup));        \
362
    fixup->next = plt_fixes;                                \
363
    plt_fixes = fixup;                                        \
364
    fixup->addr = (insn);                                \
365
    fixup->value = (plt_index);                                \
366
    plt_offset[(plt_index)] = 1;                        \
367
} while (0)
368

    
369
#define IA64_LTOFF(insn, val, relaxable)                        \
370
do {                                                                \
371
    if (ia64_patch_ltoff(insn, val, relaxable)) {                \
372
        struct ia64_fixup *fixup = alloca(sizeof(*fixup));        \
373
        fixup->next = ltoff_fixes;                                \
374
        ltoff_fixes = fixup;                                        \
375
        fixup->addr = (insn);                                        \
376
        fixup->value = (val);                                        \
377
    }                                                                \
378
} while (0)
379

    
380
static inline void ia64_apply_fixes (uint8_t **gen_code_pp,
381
                                     struct ia64_fixup *ltoff_fixes,
382
                                     uint64_t gp,
383
                                     struct ia64_fixup *plt_fixes,
384
                                     int num_plts,
385
                                     unsigned long *plt_target,
386
                                     unsigned int *plt_offset)
387
{
388
    static const uint8_t plt_bundle[] = {
389
        0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,        /* nop 0; movl r1=GP */
390
        0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x60,
391

    
392
        0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,        /* nop 0; brl IP */
393
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0
394
    };
395
    uint8_t *gen_code_ptr = *gen_code_pp, *plt_start, *got_start;
396
    uint64_t *vp;
397
    struct ia64_fixup *fixup;
398
    unsigned int offset = 0;
399
    struct fdesc {
400
        long ip;
401
        long gp;
402
    } *fdesc;
403
    int i;
404

    
405
    if (plt_fixes) {
406
        plt_start = gen_code_ptr;
407

    
408
        for (i = 0; i < num_plts; ++i) {
409
            if (plt_offset[i]) {
410
                plt_offset[i] = offset;
411
                offset += sizeof(plt_bundle);
412

    
413
                fdesc = (struct fdesc *) plt_target[i];
414
                memcpy(gen_code_ptr, plt_bundle, sizeof(plt_bundle));
415
                ia64_imm64 (gen_code_ptr + 0x02, fdesc->gp);
416
                ia64_imm60b(gen_code_ptr + 0x12,
417
                            (fdesc->ip - (long) (gen_code_ptr + 0x10)) >> 4);
418
                gen_code_ptr += sizeof(plt_bundle);
419
            }
420
        }
421

    
422
        for (fixup = plt_fixes; fixup; fixup = fixup->next)
423
            ia64_imm21b(fixup->addr,
424
                        ((long) plt_start + plt_offset[fixup->value]
425
                         - ((long) fixup->addr & ~0xf)) >> 4);
426
    }
427

    
428
    got_start = gen_code_ptr;
429

    
430
    /* First, create the GOT: */
431
    for (fixup = ltoff_fixes; fixup; fixup = fixup->next) {
432
        /* first check if we already have this value in the GOT: */
433
        for (vp = (uint64_t *) got_start; vp < (uint64_t *) gen_code_ptr; ++vp)
434
            if (*vp == fixup->value)
435
                break;
436
        if (vp == (uint64_t *) gen_code_ptr) {
437
            /* Nope, we need to put the value in the GOT: */
438
            *vp = fixup->value;
439
            gen_code_ptr += 8;
440
        }
441
        ia64_imm22(fixup->addr, (long) vp - gp);
442
    }
443
    /* Keep code ptr aligned. */
444
    if ((long) gen_code_ptr & 15)
445
        gen_code_ptr += 8;
446
    *gen_code_pp = gen_code_ptr;
447
}
448

    
449
#endif