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/*
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 * ACPI implementation
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 *
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 * Copyright (c) 2006 Fabrice Bellard
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License version 2 as published by the Free Software Foundation.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include "vl.h"
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//#define DEBUG
22

    
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/* i82731AB (PIIX4) compatible power management function */
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#define PM_FREQ 3579545
25

    
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#define ACPI_DBG_IO_ADDR  0xb044
27

    
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typedef struct PIIX4PMState {
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    PCIDevice dev;
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    uint16_t pmsts;
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    uint16_t pmen;
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    uint16_t pmcntrl;
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    uint8_t apmc;
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    uint8_t apms;
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    QEMUTimer *tmr_timer;
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    int64_t tmr_overflow_time;
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    i2c_bus *smbus;
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    uint8_t smb_stat;
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    uint8_t smb_ctl;
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    uint8_t smb_cmd;
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    uint8_t smb_addr;
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    uint8_t smb_data0;
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    uint8_t smb_data1;
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    uint8_t smb_data[32];
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    uint8_t smb_index;
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} PIIX4PMState;
47

    
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#define RTC_EN (1 << 10)
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#define PWRBTN_EN (1 << 8)
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#define GBL_EN (1 << 5)
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#define TMROF_EN (1 << 0)
52

    
53
#define SCI_EN (1 << 0)
54

    
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#define SUS_EN (1 << 13)
56

    
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#define ACPI_ENABLE 0xf1
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#define ACPI_DISABLE 0xf0
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#define SMBHSTSTS 0x00
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#define SMBHSTCNT 0x02
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#define SMBHSTCMD 0x03
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#define SMBHSTADD 0x04
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#define SMBHSTDAT0 0x05
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#define SMBHSTDAT1 0x06
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#define SMBBLKDAT 0x07
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static uint32_t get_pmtmr(PIIX4PMState *s)
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{
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    uint32_t d;
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    d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
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    return d & 0xffffff;
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}
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static int get_pmsts(PIIX4PMState *s)
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{
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    int64_t d;
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    int pmsts;
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    pmsts = s->pmsts;
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    d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
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    if (d >= s->tmr_overflow_time)
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        s->pmsts |= TMROF_EN;
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    return pmsts;
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}
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static void pm_update_sci(PIIX4PMState *s)
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{
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    int sci_level, pmsts;
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    int64_t expire_time;
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    pmsts = get_pmsts(s);
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    sci_level = (((pmsts & s->pmen) &
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                  (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
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    qemu_set_irq(s->dev.irq[0], sci_level);
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    /* schedule a timer interruption if needed */
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    if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
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        expire_time = muldiv64(s->tmr_overflow_time, ticks_per_sec, PM_FREQ);
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        qemu_mod_timer(s->tmr_timer, expire_time);
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    } else {
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        qemu_del_timer(s->tmr_timer);
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    }
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}
103

    
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static void pm_tmr_timer(void *opaque)
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{
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    PIIX4PMState *s = opaque;
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    pm_update_sci(s);
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}
109

    
110
static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
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{
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    PIIX4PMState *s = opaque;
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    addr &= 0x3f;
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    switch(addr) {
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    case 0x00:
116
        {
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            int64_t d;
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            int pmsts;
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            pmsts = get_pmsts(s);
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            if (pmsts & val & TMROF_EN) {
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                /* if TMRSTS is reset, then compute the new overflow time */
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                d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
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                s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
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            }
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            s->pmsts &= ~val;
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            pm_update_sci(s);
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        }
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        break;
129
    case 0x02:
130
        s->pmen = val;
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        pm_update_sci(s);
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        break;
133
    case 0x04:
134
        {
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            int sus_typ;
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            s->pmcntrl = val & ~(SUS_EN);
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            if (val & SUS_EN) {
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                /* change suspend type */
139
                sus_typ = (val >> 10) & 3;
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                switch(sus_typ) {
141
                case 0: /* soft power off */
142
                    qemu_system_shutdown_request();
143
                    break;
144
                default:
145
                    break;
146
                }
147
            }
148
        }
149
        break;
150
    default:
151
        break;
152
    }
153
#ifdef DEBUG
154
    printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
155
#endif
156
}
157

    
158
static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
159
{
160
    PIIX4PMState *s = opaque;
161
    uint32_t val;
162

    
163
    addr &= 0x3f;
164
    switch(addr) {
165
    case 0x00:
166
        val = get_pmsts(s);
167
        break;
168
    case 0x02:
169
        val = s->pmen;
170
        break;
171
    case 0x04:
172
        val = s->pmcntrl;
173
        break;
174
    default:
175
        val = 0;
176
        break;
177
    }
178
#ifdef DEBUG
179
    printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
180
#endif
181
    return val;
182
}
183

    
184
static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
185
{
186
    //    PIIX4PMState *s = opaque;
187
    addr &= 0x3f;
188
#ifdef DEBUG
189
    printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
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#endif
191
}
192

    
193
static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
194
{
195
    PIIX4PMState *s = opaque;
196
    uint32_t val;
197

    
198
    addr &= 0x3f;
199
    switch(addr) {
200
    case 0x08:
201
        val = get_pmtmr(s);
202
        break;
203
    default:
204
        val = 0;
205
        break;
206
    }
207
#ifdef DEBUG
208
    printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
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#endif
210
    return val;
211
}
212

    
213
static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val)
214
{
215
    PIIX4PMState *s = opaque;
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    addr &= 1;
217
#ifdef DEBUG
218
    printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
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#endif
220
    if (addr == 0) {
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        s->apmc = val;
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        /* ACPI specs 3.0, 4.7.2.5 */
224
        if (val == ACPI_ENABLE) {
225
            s->pmcntrl |= SCI_EN;
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        } else if (val == ACPI_DISABLE) {
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            s->pmcntrl &= ~SCI_EN;
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        }
229

    
230
        if (s->dev.config[0x5b] & (1 << 1)) {
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            cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
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        }
233
    } else {
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        s->apms = val;
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    }
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}
237

    
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static uint32_t pm_smi_readb(void *opaque, uint32_t addr)
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{
240
    PIIX4PMState *s = opaque;
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    uint32_t val;
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243
    addr &= 1;
244
    if (addr == 0) {
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        val = s->apmc;
246
    } else {
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        val = s->apms;
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    }
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#ifdef DEBUG
250
    printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
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#endif
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    return val;
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}
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static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
256
{
257
#if defined(DEBUG)
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    printf("ACPI: DBG: 0x%08x\n", val);
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#endif
260
}
261

    
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static void smb_transaction(PIIX4PMState *s)
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{
264
    uint8_t prot = (s->smb_ctl >> 2) & 0x07;
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    uint8_t read = s->smb_addr & 0x01;
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    uint8_t cmd = s->smb_cmd;
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    uint8_t addr = s->smb_addr >> 1;
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    i2c_bus *bus = s->smbus;
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270
#ifdef DEBUG
271
    printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
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#endif
273
    switch(prot) {
274
    case 0x0:
275
        smbus_quick_command(bus, addr, read);
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        break;
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    case 0x1:
278
        if (read) {
279
            s->smb_data0 = smbus_receive_byte(bus, addr);
280
        } else {
281
            smbus_send_byte(bus, addr, cmd);
282
        }
283
        break;
284
    case 0x2:
285
        if (read) {
286
            s->smb_data0 = smbus_read_byte(bus, addr, cmd);
287
        } else {
288
            smbus_write_byte(bus, addr, cmd, s->smb_data0);
289
        }
290
        break;
291
    case 0x3:
292
        if (read) {
293
            uint16_t val;
294
            val = smbus_read_word(bus, addr, cmd);
295
            s->smb_data0 = val;
296
            s->smb_data1 = val >> 8;
297
        } else {
298
            smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
299
        }
300
        break;
301
    case 0x5:
302
        if (read) {
303
            s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data);
304
        } else {
305
            smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0);
306
        }
307
        break;
308
    default:
309
        goto error;
310
    }
311
    return;
312

    
313
  error:
314
    s->smb_stat |= 0x04;
315
}
316

    
317
static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
318
{
319
    PIIX4PMState *s = opaque;
320
    addr &= 0x3f;
321
#ifdef DEBUG
322
    printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
323
#endif
324
    switch(addr) {
325
    case SMBHSTSTS:
326
        s->smb_stat = 0;
327
        s->smb_index = 0;
328
        break;
329
    case SMBHSTCNT:
330
        s->smb_ctl = val;
331
        if (val & 0x40)
332
            smb_transaction(s);
333
        break;
334
    case SMBHSTCMD:
335
        s->smb_cmd = val;
336
        break;
337
    case SMBHSTADD:
338
        s->smb_addr = val;
339
        break;
340
    case SMBHSTDAT0:
341
        s->smb_data0 = val;
342
        break;
343
    case SMBHSTDAT1:
344
        s->smb_data1 = val;
345
        break;
346
    case SMBBLKDAT:
347
        s->smb_data[s->smb_index++] = val;
348
        if (s->smb_index > 31)
349
            s->smb_index = 0;
350
        break;
351
    default:
352
        break;
353
    }
354
}
355

    
356
static uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
357
{
358
    PIIX4PMState *s = opaque;
359
    uint32_t val;
360

    
361
    addr &= 0x3f;
362
    switch(addr) {
363
    case SMBHSTSTS:
364
        val = s->smb_stat;
365
        break;
366
    case SMBHSTCNT:
367
        s->smb_index = 0;
368
        val = s->smb_ctl & 0x1f;
369
        break;
370
    case SMBHSTCMD:
371
        val = s->smb_cmd;
372
        break;
373
    case SMBHSTADD:
374
        val = s->smb_addr;
375
        break;
376
    case SMBHSTDAT0:
377
        val = s->smb_data0;
378
        break;
379
    case SMBHSTDAT1:
380
        val = s->smb_data1;
381
        break;
382
    case SMBBLKDAT:
383
        val = s->smb_data[s->smb_index++];
384
        if (s->smb_index > 31)
385
            s->smb_index = 0;
386
        break;
387
    default:
388
        val = 0;
389
        break;
390
    }
391
#ifdef DEBUG
392
    printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
393
#endif
394
    return val;
395
}
396

    
397
static void pm_io_space_update(PIIX4PMState *s)
398
{
399
    uint32_t pm_io_base;
400

    
401
    if (s->dev.config[0x80] & 1) {
402
        pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
403
        pm_io_base &= 0xfffe;
404

    
405
        /* XXX: need to improve memory and ioport allocation */
406
#if defined(DEBUG)
407
        printf("PM: mapping to 0x%x\n", pm_io_base);
408
#endif
409
        register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
410
        register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
411
        register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
412
        register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
413
    }
414
}
415

    
416
static void pm_write_config(PCIDevice *d,
417
                            uint32_t address, uint32_t val, int len)
418
{
419
    pci_default_write_config(d, address, val, len);
420
    if (address == 0x80)
421
        pm_io_space_update((PIIX4PMState *)d);
422
}
423

    
424
static void pm_save(QEMUFile* f,void *opaque)
425
{
426
    PIIX4PMState *s = opaque;
427

    
428
    pci_device_save(&s->dev, f);
429

    
430
    qemu_put_be16s(f, &s->pmsts);
431
    qemu_put_be16s(f, &s->pmen);
432
    qemu_put_be16s(f, &s->pmcntrl);
433
    qemu_put_8s(f, &s->apmc);
434
    qemu_put_8s(f, &s->apms);
435
    qemu_put_timer(f, s->tmr_timer);
436
    qemu_put_be64s(f, &s->tmr_overflow_time);
437
}
438

    
439
static int pm_load(QEMUFile* f,void* opaque,int version_id)
440
{
441
    PIIX4PMState *s = opaque;
442
    int ret;
443

    
444
    if (version_id > 1)
445
        return -EINVAL;
446

    
447
    ret = pci_device_load(&s->dev, f);
448
    if (ret < 0)
449
        return ret;
450

    
451
    qemu_get_be16s(f, &s->pmsts);
452
    qemu_get_be16s(f, &s->pmen);
453
    qemu_get_be16s(f, &s->pmcntrl);
454
    qemu_get_8s(f, &s->apmc);
455
    qemu_get_8s(f, &s->apms);
456
    qemu_get_timer(f, s->tmr_timer);
457
    qemu_get_be64s(f, &s->tmr_overflow_time);
458

    
459
    pm_io_space_update(s);
460

    
461
    return 0;
462
}
463

    
464
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
465
{
466
    PIIX4PMState *s;
467
    uint8_t *pci_conf;
468

    
469
    s = (PIIX4PMState *)pci_register_device(bus,
470
                                         "PM", sizeof(PIIX4PMState),
471
                                         devfn, NULL, pm_write_config);
472
    pci_conf = s->dev.config;
473
    pci_conf[0x00] = 0x86;
474
    pci_conf[0x01] = 0x80;
475
    pci_conf[0x02] = 0x13;
476
    pci_conf[0x03] = 0x71;
477
    pci_conf[0x08] = 0x00; // revision number
478
    pci_conf[0x09] = 0x00;
479
    pci_conf[0x0a] = 0x80; // other bridge device
480
    pci_conf[0x0b] = 0x06; // bridge device
481
    pci_conf[0x0e] = 0x00; // header_type
482
    pci_conf[0x3d] = 0x01; // interrupt pin 1
483
   
484
    pci_conf[0x40] = 0x01; /* PM io base read only bit */
485
   
486
    register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s);
487
    register_ioport_read(0xb2, 2, 1, pm_smi_readb, s);
488

    
489
    register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
490

    
491
    /* XXX: which specification is used ? The i82731AB has different
492
       mappings */
493
    pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
494
    pci_conf[0x63] = 0x60;
495
    pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
496
        (serial_hds[1] != NULL ? 0x90 : 0);
497

    
498
    pci_conf[0x90] = smb_io_base | 1;
499
    pci_conf[0x91] = smb_io_base >> 8;
500
    pci_conf[0xd2] = 0x09;
501
    register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s);
502
    register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s);
503

    
504
    s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
505

    
506
    register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s);
507

    
508
    s->smbus = i2c_init_bus();
509
    return s->smbus;
510
}