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1
/*
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 * QEMU NE2000 emulation
3
 *
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 * Copyright (c) 2003-2004 Fabrice Bellard
5
 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "vl.h"
25

    
26
/* debug NE2000 card */
27
//#define DEBUG_NE2000
28

    
29
#define MAX_ETH_FRAME_SIZE 1514
30

    
31
#define E8390_CMD        0x00  /* The command register (for all pages) */
32
/* Page 0 register offsets. */
33
#define EN0_CLDALO        0x01        /* Low byte of current local dma addr  RD */
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#define EN0_STARTPG        0x01        /* Starting page of ring bfr WR */
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#define EN0_CLDAHI        0x02        /* High byte of current local dma addr  RD */
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#define EN0_STOPPG        0x02        /* Ending page +1 of ring bfr WR */
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#define EN0_BOUNDARY        0x03        /* Boundary page of ring bfr RD WR */
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#define EN0_TSR                0x04        /* Transmit status reg RD */
39
#define EN0_TPSR        0x04        /* Transmit starting page WR */
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#define EN0_NCR                0x05        /* Number of collision reg RD */
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#define EN0_TCNTLO        0x05        /* Low  byte of tx byte count WR */
42
#define EN0_FIFO        0x06        /* FIFO RD */
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#define EN0_TCNTHI        0x06        /* High byte of tx byte count WR */
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#define EN0_ISR                0x07        /* Interrupt status reg RD WR */
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#define EN0_CRDALO        0x08        /* low byte of current remote dma address RD */
46
#define EN0_RSARLO        0x08        /* Remote start address reg 0 */
47
#define EN0_CRDAHI        0x09        /* high byte, current remote dma address RD */
48
#define EN0_RSARHI        0x09        /* Remote start address reg 1 */
49
#define EN0_RCNTLO        0x0a        /* Remote byte count reg WR */
50
#define EN0_RTL8029ID0        0x0a        /* Realtek ID byte #1 RD */
51
#define EN0_RCNTHI        0x0b        /* Remote byte count reg WR */
52
#define EN0_RTL8029ID1        0x0b        /* Realtek ID byte #2 RD */
53
#define EN0_RSR                0x0c        /* rx status reg RD */
54
#define EN0_RXCR        0x0c        /* RX configuration reg WR */
55
#define EN0_TXCR        0x0d        /* TX configuration reg WR */
56
#define EN0_COUNTER0        0x0d        /* Rcv alignment error counter RD */
57
#define EN0_DCFG        0x0e        /* Data configuration reg WR */
58
#define EN0_COUNTER1        0x0e        /* Rcv CRC error counter RD */
59
#define EN0_IMR                0x0f        /* Interrupt mask reg WR */
60
#define EN0_COUNTER2        0x0f        /* Rcv missed frame error counter RD */
61

    
62
#define EN1_PHYS        0x11
63
#define EN1_CURPAG      0x17
64
#define EN1_MULT        0x18
65

    
66
#define EN2_STARTPG        0x21        /* Starting page of ring bfr RD */
67
#define EN2_STOPPG        0x22        /* Ending page +1 of ring bfr RD */
68

    
69
#define EN3_CONFIG0        0x33
70
#define EN3_CONFIG1        0x34
71
#define EN3_CONFIG2        0x35
72
#define EN3_CONFIG3        0x36
73

    
74
/*  Register accessed at EN_CMD, the 8390 base addr.  */
75
#define E8390_STOP        0x01        /* Stop and reset the chip */
76
#define E8390_START        0x02        /* Start the chip, clear reset */
77
#define E8390_TRANS        0x04        /* Transmit a frame */
78
#define E8390_RREAD        0x08        /* Remote read */
79
#define E8390_RWRITE        0x10        /* Remote write  */
80
#define E8390_NODMA        0x20        /* Remote DMA */
81
#define E8390_PAGE0        0x00        /* Select page chip registers */
82
#define E8390_PAGE1        0x40        /* using the two high-order bits */
83
#define E8390_PAGE2        0x80        /* Page 3 is invalid. */
84

    
85
/* Bits in EN0_ISR - Interrupt status register */
86
#define ENISR_RX        0x01        /* Receiver, no error */
87
#define ENISR_TX        0x02        /* Transmitter, no error */
88
#define ENISR_RX_ERR        0x04        /* Receiver, with error */
89
#define ENISR_TX_ERR        0x08        /* Transmitter, with error */
90
#define ENISR_OVER        0x10        /* Receiver overwrote the ring */
91
#define ENISR_COUNTERS        0x20        /* Counters need emptying */
92
#define ENISR_RDC        0x40        /* remote dma complete */
93
#define ENISR_RESET        0x80        /* Reset completed */
94
#define ENISR_ALL        0x3f        /* Interrupts we will enable */
95

    
96
/* Bits in received packet status byte and EN0_RSR*/
97
#define ENRSR_RXOK        0x01        /* Received a good packet */
98
#define ENRSR_CRC        0x02        /* CRC error */
99
#define ENRSR_FAE        0x04        /* frame alignment error */
100
#define ENRSR_FO        0x08        /* FIFO overrun */
101
#define ENRSR_MPA        0x10        /* missed pkt */
102
#define ENRSR_PHY        0x20        /* physical/multicast address */
103
#define ENRSR_DIS        0x40        /* receiver disable. set in monitor mode */
104
#define ENRSR_DEF        0x80        /* deferring */
105

    
106
/* Transmitted packet status, EN0_TSR. */
107
#define ENTSR_PTX 0x01        /* Packet transmitted without error */
108
#define ENTSR_ND  0x02        /* The transmit wasn't deferred. */
109
#define ENTSR_COL 0x04        /* The transmit collided at least once. */
110
#define ENTSR_ABT 0x08  /* The transmit collided 16 times, and was deferred. */
111
#define ENTSR_CRS 0x10        /* The carrier sense was lost. */
112
#define ENTSR_FU  0x20  /* A "FIFO underrun" occurred during transmit. */
113
#define ENTSR_CDH 0x40        /* The collision detect "heartbeat" signal was lost. */
114
#define ENTSR_OWC 0x80  /* There was an out-of-window collision. */
115

    
116
#define NE2000_PMEM_SIZE    (32*1024)
117
#define NE2000_PMEM_START   (16*1024)
118
#define NE2000_PMEM_END     (NE2000_PMEM_SIZE+NE2000_PMEM_START)
119
#define NE2000_MEM_SIZE     NE2000_PMEM_END
120

    
121
typedef struct NE2000State {
122
    uint8_t cmd;
123
    uint32_t start;
124
    uint32_t stop;
125
    uint8_t boundary;
126
    uint8_t tsr;
127
    uint8_t tpsr;
128
    uint16_t tcnt;
129
    uint16_t rcnt;
130
    uint32_t rsar;
131
    uint8_t rsr;
132
    uint8_t rxcr;
133
    uint8_t isr;
134
    uint8_t dcfg;
135
    uint8_t imr;
136
    uint8_t phys[6]; /* mac address */
137
    uint8_t curpag;
138
    uint8_t mult[8]; /* multicast mask array */
139
    qemu_irq irq;
140
    PCIDevice *pci_dev;
141
    VLANClientState *vc;
142
    uint8_t macaddr[6];
143
    uint8_t mem[NE2000_MEM_SIZE];
144
} NE2000State;
145

    
146
static void ne2000_reset(NE2000State *s)
147
{
148
    int i;
149

    
150
    s->isr = ENISR_RESET;
151
    memcpy(s->mem, s->macaddr, 6);
152
    s->mem[14] = 0x57;
153
    s->mem[15] = 0x57;
154

    
155
    /* duplicate prom data */
156
    for(i = 15;i >= 0; i--) {
157
        s->mem[2 * i] = s->mem[i];
158
        s->mem[2 * i + 1] = s->mem[i];
159
    }
160
}
161

    
162
static void ne2000_update_irq(NE2000State *s)
163
{
164
    int isr;
165
    isr = (s->isr & s->imr) & 0x7f;
166
#if defined(DEBUG_NE2000)
167
    printf("NE2000: Set IRQ to %d (%02x %02x)\n",
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           isr ? 1 : 0, s->isr, s->imr);
169
#endif
170
    qemu_set_irq(s->irq, (isr != 0));
171
}
172

    
173
#define POLYNOMIAL 0x04c11db6
174

    
175
/* From FreeBSD */
176
/* XXX: optimize */
177
static int compute_mcast_idx(const uint8_t *ep)
178
{
179
    uint32_t crc;
180
    int carry, i, j;
181
    uint8_t b;
182

    
183
    crc = 0xffffffff;
184
    for (i = 0; i < 6; i++) {
185
        b = *ep++;
186
        for (j = 0; j < 8; j++) {
187
            carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
188
            crc <<= 1;
189
            b >>= 1;
190
            if (carry)
191
                crc = ((crc ^ POLYNOMIAL) | carry);
192
        }
193
    }
194
    return (crc >> 26);
195
}
196

    
197
static int ne2000_buffer_full(NE2000State *s)
198
{
199
    int avail, index, boundary;
200

    
201
    index = s->curpag << 8;
202
    boundary = s->boundary << 8;
203
    if (index < boundary)
204
        avail = boundary - index;
205
    else
206
        avail = (s->stop - s->start) - (index - boundary);
207
    if (avail < (MAX_ETH_FRAME_SIZE + 4))
208
        return 1;
209
    return 0;
210
}
211

    
212
static int ne2000_can_receive(void *opaque)
213
{
214
    NE2000State *s = opaque;
215
   
216
    if (s->cmd & E8390_STOP)
217
        return 1;
218
    return !ne2000_buffer_full(s);
219
}
220

    
221
#define MIN_BUF_SIZE 60
222

    
223
static void ne2000_receive(void *opaque, const uint8_t *buf, int size)
224
{
225
    NE2000State *s = opaque;
226
    uint8_t *p;
227
    unsigned int total_len, next, avail, len, index, mcast_idx;
228
    uint8_t buf1[60];
229
    static const uint8_t broadcast_macaddr[6] =
230
        { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
231
   
232
#if defined(DEBUG_NE2000)
233
    printf("NE2000: received len=%d\n", size);
234
#endif
235

    
236
    if (s->cmd & E8390_STOP || ne2000_buffer_full(s))
237
        return;
238
   
239
    /* XXX: check this */
240
    if (s->rxcr & 0x10) {
241
        /* promiscuous: receive all */
242
    } else {
243
        if (!memcmp(buf,  broadcast_macaddr, 6)) {
244
            /* broadcast address */
245
            if (!(s->rxcr & 0x04))
246
                return;
247
        } else if (buf[0] & 0x01) {
248
            /* multicast */
249
            if (!(s->rxcr & 0x08))
250
                return;
251
            mcast_idx = compute_mcast_idx(buf);
252
            if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
253
                return;
254
        } else if (s->mem[0] == buf[0] &&
255
                   s->mem[2] == buf[1] &&                  
256
                   s->mem[4] == buf[2] &&           
257
                   s->mem[6] == buf[3] &&           
258
                   s->mem[8] == buf[4] &&           
259
                   s->mem[10] == buf[5]) {
260
            /* match */
261
        } else {
262
            return;
263
        }
264
    }
265

    
266

    
267
    /* if too small buffer, then expand it */
268
    if (size < MIN_BUF_SIZE) {
269
        memcpy(buf1, buf, size);
270
        memset(buf1 + size, 0, MIN_BUF_SIZE - size);
271
        buf = buf1;
272
        size = MIN_BUF_SIZE;
273
    }
274

    
275
    index = s->curpag << 8;
276
    /* 4 bytes for header */
277
    total_len = size + 4;
278
    /* address for next packet (4 bytes for CRC) */
279
    next = index + ((total_len + 4 + 255) & ~0xff);
280
    if (next >= s->stop)
281
        next -= (s->stop - s->start);
282
    /* prepare packet header */
283
    p = s->mem + index;
284
    s->rsr = ENRSR_RXOK; /* receive status */
285
    /* XXX: check this */
286
    if (buf[0] & 0x01)
287
        s->rsr |= ENRSR_PHY;
288
    p[0] = s->rsr;
289
    p[1] = next >> 8;
290
    p[2] = total_len;
291
    p[3] = total_len >> 8;
292
    index += 4;
293

    
294
    /* write packet data */
295
    while (size > 0) {
296
        if (index <= s->stop)
297
            avail = s->stop - index;
298
        else
299
            avail = 0;
300
        len = size;
301
        if (len > avail)
302
            len = avail;
303
        memcpy(s->mem + index, buf, len);
304
        buf += len;
305
        index += len;
306
        if (index == s->stop)
307
            index = s->start;
308
        size -= len;
309
    }
310
    s->curpag = next >> 8;
311

    
312
    /* now we can signal we have received something */
313
    s->isr |= ENISR_RX;
314
    ne2000_update_irq(s);
315
}
316

    
317
static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
318
{
319
    NE2000State *s = opaque;
320
    int offset, page, index;
321

    
322
    addr &= 0xf;
323
#ifdef DEBUG_NE2000
324
    printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
325
#endif
326
    if (addr == E8390_CMD) {
327
        /* control register */
328
        s->cmd = val;
329
        if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */
330
            s->isr &= ~ENISR_RESET;
331
            /* test specific case: zero length transfer */
332
            if ((val & (E8390_RREAD | E8390_RWRITE)) &&
333
                s->rcnt == 0) {
334
                s->isr |= ENISR_RDC;
335
                ne2000_update_irq(s);
336
            }
337
            if (val & E8390_TRANS) {
338
                index = (s->tpsr << 8);
339
                /* XXX: next 2 lines are a hack to make netware 3.11 work */
340
                if (index >= NE2000_PMEM_END)
341
                    index -= NE2000_PMEM_SIZE;
342
                /* fail safe: check range on the transmitted length  */
343
                if (index + s->tcnt <= NE2000_PMEM_END) {
344
                    qemu_send_packet(s->vc, s->mem + index, s->tcnt);
345
                }
346
                /* signal end of transfer */
347
                s->tsr = ENTSR_PTX;
348
                s->isr |= ENISR_TX;
349
                s->cmd &= ~E8390_TRANS;
350
                ne2000_update_irq(s);
351
            }
352
        }
353
    } else {
354
        page = s->cmd >> 6;
355
        offset = addr | (page << 4);
356
        switch(offset) {
357
        case EN0_STARTPG:
358
            s->start = val << 8;
359
            break;
360
        case EN0_STOPPG:
361
            s->stop = val << 8;
362
            break;
363
        case EN0_BOUNDARY:
364
            s->boundary = val;
365
            break;
366
        case EN0_IMR:
367
            s->imr = val;
368
            ne2000_update_irq(s);
369
            break;
370
        case EN0_TPSR:
371
            s->tpsr = val;
372
            break;
373
        case EN0_TCNTLO:
374
            s->tcnt = (s->tcnt & 0xff00) | val;
375
            break;
376
        case EN0_TCNTHI:
377
            s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
378
            break;
379
        case EN0_RSARLO:
380
            s->rsar = (s->rsar & 0xff00) | val;
381
            break;
382
        case EN0_RSARHI:
383
            s->rsar = (s->rsar & 0x00ff) | (val << 8);
384
            break;
385
        case EN0_RCNTLO:
386
            s->rcnt = (s->rcnt & 0xff00) | val;
387
            break;
388
        case EN0_RCNTHI:
389
            s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
390
            break;
391
        case EN0_RXCR:
392
            s->rxcr = val;
393
            break;
394
        case EN0_DCFG:
395
            s->dcfg = val;
396
            break;
397
        case EN0_ISR:
398
            s->isr &= ~(val & 0x7f);
399
            ne2000_update_irq(s);
400
            break;
401
        case EN1_PHYS ... EN1_PHYS + 5:
402
            s->phys[offset - EN1_PHYS] = val;
403
            break;
404
        case EN1_CURPAG:
405
            s->curpag = val;
406
            break;
407
        case EN1_MULT ... EN1_MULT + 7:
408
            s->mult[offset - EN1_MULT] = val;
409
            break;
410
        }
411
    }
412
}
413

    
414
static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
415
{
416
    NE2000State *s = opaque;
417
    int offset, page, ret;
418

    
419
    addr &= 0xf;
420
    if (addr == E8390_CMD) {
421
        ret = s->cmd;
422
    } else {
423
        page = s->cmd >> 6;
424
        offset = addr | (page << 4);
425
        switch(offset) {
426
        case EN0_TSR:
427
            ret = s->tsr;
428
            break;
429
        case EN0_BOUNDARY:
430
            ret = s->boundary;
431
            break;
432
        case EN0_ISR:
433
            ret = s->isr;
434
            break;
435
        case EN0_RSARLO:
436
            ret = s->rsar & 0x00ff;
437
            break;
438
        case EN0_RSARHI:
439
            ret = s->rsar >> 8;
440
            break;
441
        case EN1_PHYS ... EN1_PHYS + 5:
442
            ret = s->phys[offset - EN1_PHYS];
443
            break;
444
        case EN1_CURPAG:
445
            ret = s->curpag;
446
            break;
447
        case EN1_MULT ... EN1_MULT + 7:
448
            ret = s->mult[offset - EN1_MULT];
449
            break;
450
        case EN0_RSR:
451
            ret = s->rsr;
452
            break;
453
        case EN2_STARTPG:
454
            ret = s->start >> 8;
455
            break;
456
        case EN2_STOPPG:
457
            ret = s->stop >> 8;
458
            break;
459
        case EN0_RTL8029ID0:
460
            ret = 0x50;
461
            break;
462
        case EN0_RTL8029ID1:
463
            ret = 0x43;
464
            break;
465
        case EN3_CONFIG0:
466
            ret = 0;                /* 10baseT media */
467
            break;
468
        case EN3_CONFIG2:
469
            ret = 0x40;                /* 10baseT active */
470
            break;
471
        case EN3_CONFIG3:
472
            ret = 0x40;                /* Full duplex */
473
            break;
474
        default:
475
            ret = 0x00;
476
            break;
477
        }
478
    }
479
#ifdef DEBUG_NE2000
480
    printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
481
#endif
482
    return ret;
483
}
484

    
485
static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr,
486
                                     uint32_t val)
487
{
488
    if (addr < 32 ||
489
        (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
490
        s->mem[addr] = val;
491
    }
492
}
493

    
494
static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr,
495
                                     uint32_t val)
496
{
497
    addr &= ~1; /* XXX: check exact behaviour if not even */
498
    if (addr < 32 ||
499
        (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
500
        *(uint16_t *)(s->mem + addr) = cpu_to_le16(val);
501
    }
502
}
503

    
504
static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr,
505
                                     uint32_t val)
506
{
507
    addr &= ~1; /* XXX: check exact behaviour if not even */
508
    if (addr < 32 ||
509
        (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
510
        cpu_to_le32wu((uint32_t *)(s->mem + addr), val);
511
    }
512
}
513

    
514
static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr)
515
{
516
    if (addr < 32 ||
517
        (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
518
        return s->mem[addr];
519
    } else {
520
        return 0xff;
521
    }
522
}
523

    
524
static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr)
525
{
526
    addr &= ~1; /* XXX: check exact behaviour if not even */
527
    if (addr < 32 ||
528
        (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
529
        return le16_to_cpu(*(uint16_t *)(s->mem + addr));
530
    } else {
531
        return 0xffff;
532
    }
533
}
534

    
535
static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr)
536
{
537
    addr &= ~1; /* XXX: check exact behaviour if not even */
538
    if (addr < 32 ||
539
        (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
540
        return le32_to_cpupu((uint32_t *)(s->mem + addr));
541
    } else {
542
        return 0xffffffff;
543
    }
544
}
545

    
546
static inline void ne2000_dma_update(NE2000State *s, int len)
547
{
548
    s->rsar += len;
549
    /* wrap */
550
    /* XXX: check what to do if rsar > stop */
551
    if (s->rsar == s->stop)
552
        s->rsar = s->start;
553

    
554
    if (s->rcnt <= len) {
555
        s->rcnt = 0;
556
        /* signal end of transfer */
557
        s->isr |= ENISR_RDC;
558
        ne2000_update_irq(s);
559
    } else {
560
        s->rcnt -= len;
561
    }
562
}
563

    
564
static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
565
{
566
    NE2000State *s = opaque;
567

    
568
#ifdef DEBUG_NE2000
569
    printf("NE2000: asic write val=0x%04x\n", val);
570
#endif
571
    if (s->rcnt == 0)
572
        return;
573
    if (s->dcfg & 0x01) {
574
        /* 16 bit access */
575
        ne2000_mem_writew(s, s->rsar, val);
576
        ne2000_dma_update(s, 2);
577
    } else {
578
        /* 8 bit access */
579
        ne2000_mem_writeb(s, s->rsar, val);
580
        ne2000_dma_update(s, 1);
581
    }
582
}
583

    
584
static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
585
{
586
    NE2000State *s = opaque;
587
    int ret;
588

    
589
    if (s->dcfg & 0x01) {
590
        /* 16 bit access */
591
        ret = ne2000_mem_readw(s, s->rsar);
592
        ne2000_dma_update(s, 2);
593
    } else {
594
        /* 8 bit access */
595
        ret = ne2000_mem_readb(s, s->rsar);
596
        ne2000_dma_update(s, 1);
597
    }
598
#ifdef DEBUG_NE2000
599
    printf("NE2000: asic read val=0x%04x\n", ret);
600
#endif
601
    return ret;
602
}
603

    
604
static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
605
{
606
    NE2000State *s = opaque;
607

    
608
#ifdef DEBUG_NE2000
609
    printf("NE2000: asic writel val=0x%04x\n", val);
610
#endif
611
    if (s->rcnt == 0)
612
        return;
613
    /* 32 bit access */
614
    ne2000_mem_writel(s, s->rsar, val);
615
    ne2000_dma_update(s, 4);
616
}
617

    
618
static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr)
619
{
620
    NE2000State *s = opaque;
621
    int ret;
622

    
623
    /* 32 bit access */
624
    ret = ne2000_mem_readl(s, s->rsar);
625
    ne2000_dma_update(s, 4);
626
#ifdef DEBUG_NE2000
627
    printf("NE2000: asic readl val=0x%04x\n", ret);
628
#endif
629
    return ret;
630
}
631

    
632
static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
633
{
634
    /* nothing to do (end of reset pulse) */
635
}
636

    
637
static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
638
{
639
    NE2000State *s = opaque;
640
    ne2000_reset(s);
641
    return 0;
642
}
643

    
644
static void ne2000_save(QEMUFile* f,void* opaque)
645
{
646
        NE2000State* s=(NE2000State*)opaque;
647
        int tmp;
648

    
649
        if (s->pci_dev)
650
            pci_device_save(s->pci_dev, f);
651

    
652
        qemu_put_8s(f, &s->rxcr);
653

    
654
        qemu_put_8s(f, &s->cmd);
655
        qemu_put_be32s(f, &s->start);
656
        qemu_put_be32s(f, &s->stop);
657
        qemu_put_8s(f, &s->boundary);
658
        qemu_put_8s(f, &s->tsr);
659
        qemu_put_8s(f, &s->tpsr);
660
        qemu_put_be16s(f, &s->tcnt);
661
        qemu_put_be16s(f, &s->rcnt);
662
        qemu_put_be32s(f, &s->rsar);
663
        qemu_put_8s(f, &s->rsr);
664
        qemu_put_8s(f, &s->isr);
665
        qemu_put_8s(f, &s->dcfg);
666
        qemu_put_8s(f, &s->imr);
667
        qemu_put_buffer(f, s->phys, 6);
668
        qemu_put_8s(f, &s->curpag);
669
        qemu_put_buffer(f, s->mult, 8);
670
        tmp = 0;
671
        qemu_put_be32s(f, &tmp); /* ignored, was irq */
672
        qemu_put_buffer(f, s->mem, NE2000_MEM_SIZE);
673
}
674

    
675
static int ne2000_load(QEMUFile* f,void* opaque,int version_id)
676
{
677
        NE2000State* s=(NE2000State*)opaque;
678
        int ret;
679
        int tmp;
680

    
681
        if (version_id > 3)
682
            return -EINVAL;
683

    
684
        if (s->pci_dev && version_id >= 3) {
685
            ret = pci_device_load(s->pci_dev, f);
686
            if (ret < 0)
687
                return ret;
688
        }
689

    
690
        if (version_id >= 2) {
691
            qemu_get_8s(f, &s->rxcr);
692
        } else {
693
            s->rxcr = 0x0c;
694
        }
695

    
696
        qemu_get_8s(f, &s->cmd);
697
        qemu_get_be32s(f, &s->start);
698
        qemu_get_be32s(f, &s->stop);
699
        qemu_get_8s(f, &s->boundary);
700
        qemu_get_8s(f, &s->tsr);
701
        qemu_get_8s(f, &s->tpsr);
702
        qemu_get_be16s(f, &s->tcnt);
703
        qemu_get_be16s(f, &s->rcnt);
704
        qemu_get_be32s(f, &s->rsar);
705
        qemu_get_8s(f, &s->rsr);
706
        qemu_get_8s(f, &s->isr);
707
        qemu_get_8s(f, &s->dcfg);
708
        qemu_get_8s(f, &s->imr);
709
        qemu_get_buffer(f, s->phys, 6);
710
        qemu_get_8s(f, &s->curpag);
711
        qemu_get_buffer(f, s->mult, 8);
712
        qemu_get_be32s(f, &tmp); /* ignored */
713
        qemu_get_buffer(f, s->mem, NE2000_MEM_SIZE);
714

    
715
        return 0;
716
}
717

    
718
void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd)
719
{
720
    NE2000State *s;
721
   
722
    s = qemu_mallocz(sizeof(NE2000State));
723
    if (!s)
724
        return;
725
   
726
    register_ioport_write(base, 16, 1, ne2000_ioport_write, s);
727
    register_ioport_read(base, 16, 1, ne2000_ioport_read, s);
728

    
729
    register_ioport_write(base + 0x10, 1, 1, ne2000_asic_ioport_write, s);
730
    register_ioport_read(base + 0x10, 1, 1, ne2000_asic_ioport_read, s);
731
    register_ioport_write(base + 0x10, 2, 2, ne2000_asic_ioport_write, s);
732
    register_ioport_read(base + 0x10, 2, 2, ne2000_asic_ioport_read, s);
733

    
734
    register_ioport_write(base + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
735
    register_ioport_read(base + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
736
    s->irq = irq;
737
    memcpy(s->macaddr, nd->macaddr, 6);
738

    
739
    ne2000_reset(s);
740

    
741
    s->vc = qemu_new_vlan_client(nd->vlan, ne2000_receive,
742
                                 ne2000_can_receive, s);
743

    
744
    snprintf(s->vc->info_str, sizeof(s->vc->info_str),
745
             "ne2000 macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
746
             s->macaddr[0],
747
             s->macaddr[1],
748
             s->macaddr[2],
749
             s->macaddr[3],
750
             s->macaddr[4],
751
             s->macaddr[5]);
752
            
753
    register_savevm("ne2000", 0, 2, ne2000_save, ne2000_load, s);
754
}
755

    
756
/***********************************************************/
757
/* PCI NE2000 definitions */
758

    
759
typedef struct PCINE2000State {
760
    PCIDevice dev;
761
    NE2000State ne2000;
762
} PCINE2000State;
763

    
764
static void ne2000_map(PCIDevice *pci_dev, int region_num,
765
                       uint32_t addr, uint32_t size, int type)
766
{
767
    PCINE2000State *d = (PCINE2000State *)pci_dev;
768
    NE2000State *s = &d->ne2000;
769

    
770
    register_ioport_write(addr, 16, 1, ne2000_ioport_write, s);
771
    register_ioport_read(addr, 16, 1, ne2000_ioport_read, s);
772

    
773
    register_ioport_write(addr + 0x10, 1, 1, ne2000_asic_ioport_write, s);
774
    register_ioport_read(addr + 0x10, 1, 1, ne2000_asic_ioport_read, s);
775
    register_ioport_write(addr + 0x10, 2, 2, ne2000_asic_ioport_write, s);
776
    register_ioport_read(addr + 0x10, 2, 2, ne2000_asic_ioport_read, s);
777
    register_ioport_write(addr + 0x10, 4, 4, ne2000_asic_ioport_writel, s);
778
    register_ioport_read(addr + 0x10, 4, 4, ne2000_asic_ioport_readl, s);
779

    
780
    register_ioport_write(addr + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
781
    register_ioport_read(addr + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
782
}
783

    
784
void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn)
785
{
786
    PCINE2000State *d;
787
    NE2000State *s;
788
    uint8_t *pci_conf;
789
   
790
    d = (PCINE2000State *)pci_register_device(bus,
791
                                              "NE2000", sizeof(PCINE2000State),
792
                                              devfn,
793
                                              NULL, NULL);
794
    pci_conf = d->dev.config;
795
    pci_conf[0x00] = 0xec; // Realtek 8029
796
    pci_conf[0x01] = 0x10;
797
    pci_conf[0x02] = 0x29;
798
    pci_conf[0x03] = 0x80;
799
    pci_conf[0x0a] = 0x00; // ethernet network controller
800
    pci_conf[0x0b] = 0x02;
801
    pci_conf[0x0e] = 0x00; // header_type
802
    pci_conf[0x3d] = 1; // interrupt pin 0
803
   
804
    pci_register_io_region(&d->dev, 0, 0x100,
805
                           PCI_ADDRESS_SPACE_IO, ne2000_map);
806
    s = &d->ne2000;
807
    s->irq = d->dev.irq[0];
808
    s->pci_dev = (PCIDevice *)d;
809
    memcpy(s->macaddr, nd->macaddr, 6);
810
    ne2000_reset(s);
811
    s->vc = qemu_new_vlan_client(nd->vlan, ne2000_receive,
812
                                 ne2000_can_receive, s);
813

    
814
    snprintf(s->vc->info_str, sizeof(s->vc->info_str),
815
             "ne2000 pci macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
816
             s->macaddr[0],
817
             s->macaddr[1],
818
             s->macaddr[2],
819
             s->macaddr[3],
820
             s->macaddr[4],
821
             s->macaddr[5]);
822
            
823
    /* XXX: instance number ? */
824
    register_savevm("ne2000", 0, 3, ne2000_save, ne2000_load, s);
825
}