Statistics
| Branch: | Revision:

root / hw / ppc_chrp.c @ 5fafdf24

History | View | Annotate | Download (19.9 kB)

1
/*
2
 * QEMU PPC CHRP/PMAC hardware System Emulator
3
 *
4
 * Copyright (c) 2004-2007 Fabrice Bellard
5
 *
6
 * Permission is hereby granted, free of charge, to any person obtaining a copy
7
 * of this software and associated documentation files (the "Software"), to deal
8
 * in the Software without restriction, including without limitation the rights
9
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10
 * copies of the Software, and to permit persons to whom the Software is
11
 * furnished to do so, subject to the following conditions:
12
 *
13
 * The above copyright notice and this permission notice shall be included in
14
 * all copies or substantial portions of the Software.
15
 *
16
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22
 * THE SOFTWARE.
23
 */
24
#include "vl.h"
25

    
26
/* SMP is not enabled, for now */
27
#define MAX_CPUS 1
28

    
29
#define BIOS_FILENAME "ppc_rom.bin"
30
#define VGABIOS_FILENAME "video.x"
31
#define NVRAM_SIZE        0x2000
32

    
33
#define KERNEL_LOAD_ADDR 0x01000000
34
#define INITRD_LOAD_ADDR 0x01800000
35

    
36
/* MacIO devices (mapped inside the MacIO address space): CUDA, DBDMA,
37
   NVRAM */
38

    
39
static int dbdma_mem_index;
40
static int cuda_mem_index;
41
static int ide0_mem_index = -1;
42
static int ide1_mem_index = -1;
43
static int openpic_mem_index = -1;
44
static int heathrow_pic_mem_index = -1;
45
static int macio_nvram_mem_index = -1;
46

    
47
/* DBDMA: currently no op - should suffice right now */
48

    
49
static void dbdma_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
50
{
51
    printf("%s: 0x" PADDRX " <= 0x%08x\n", __func__, addr, value);
52
}
53

    
54
static void dbdma_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
55
{
56
}
57

    
58
static void dbdma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
59
{
60
}
61

    
62
static uint32_t dbdma_readb (void *opaque, target_phys_addr_t addr)
63
{
64
    printf("%s: 0x" PADDRX " => 0x00000000\n", __func__, addr);
65
    return 0;
66
}
67

    
68
static uint32_t dbdma_readw (void *opaque, target_phys_addr_t addr)
69
{
70
    return 0;
71
}
72

    
73
static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr)
74
{
75
    return 0;
76
}
77

    
78
static CPUWriteMemoryFunc *dbdma_write[] = {
79
    &dbdma_writeb,
80
    &dbdma_writew,
81
    &dbdma_writel,
82
};
83

    
84
static CPUReadMemoryFunc *dbdma_read[] = {
85
    &dbdma_readb,
86
    &dbdma_readw,
87
    &dbdma_readl,
88
};
89

    
90
/* macio style NVRAM device */
91
typedef struct MacIONVRAMState {
92
    uint8_t data[0x2000];
93
} MacIONVRAMState;
94

    
95
static void macio_nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
96
{
97
    MacIONVRAMState *s = opaque;
98
    addr = (addr >> 4) & 0x1fff;
99
    s->data[addr] = value;
100
    //    printf("macio_nvram_writeb %04x = %02x\n", addr, value);
101
}
102

    
103
static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr)
104
{
105
    MacIONVRAMState *s = opaque;
106
    uint32_t value;
107

    
108
    addr = (addr >> 4) & 0x1fff;
109
    value = s->data[addr];
110
    //    printf("macio_nvram_readb %04x = %02x\n", addr, value);
111
    return value;
112
}
113

    
114
static CPUWriteMemoryFunc *macio_nvram_write[] = {
115
    &macio_nvram_writeb,
116
    &macio_nvram_writeb,
117
    &macio_nvram_writeb,
118
};
119

    
120
static CPUReadMemoryFunc *macio_nvram_read[] = {
121
    &macio_nvram_readb,
122
    &macio_nvram_readb,
123
    &macio_nvram_readb,
124
};
125

    
126
static MacIONVRAMState *macio_nvram_init(void)
127
{
128
    MacIONVRAMState *s;
129
    s = qemu_mallocz(sizeof(MacIONVRAMState));
130
    if (!s)
131
        return NULL;
132
    macio_nvram_mem_index = cpu_register_io_memory(0, macio_nvram_read,
133
                                                   macio_nvram_write, s);
134
    return s;
135
}
136

    
137
static void macio_map(PCIDevice *pci_dev, int region_num,
138
                      uint32_t addr, uint32_t size, int type)
139
{
140
    if (heathrow_pic_mem_index >= 0) {
141
        cpu_register_physical_memory(addr + 0x00000, 0x1000,
142
                                     heathrow_pic_mem_index);
143
    }
144
    cpu_register_physical_memory(addr + 0x08000, 0x1000, dbdma_mem_index);
145
    cpu_register_physical_memory(addr + 0x16000, 0x2000, cuda_mem_index);
146
    if (ide0_mem_index >= 0)
147
        cpu_register_physical_memory(addr + 0x1f000, 0x1000, ide0_mem_index);
148
    if (ide1_mem_index >= 0)
149
        cpu_register_physical_memory(addr + 0x20000, 0x1000, ide1_mem_index);
150
    if (openpic_mem_index >= 0) {
151
        cpu_register_physical_memory(addr + 0x40000, 0x40000,
152
                                     openpic_mem_index);
153
    }
154
    if (macio_nvram_mem_index >= 0)
155
        cpu_register_physical_memory(addr + 0x60000, 0x20000, macio_nvram_mem_index);
156
}
157

    
158
static void macio_init(PCIBus *bus, int device_id)
159
{
160
    PCIDevice *d;
161

    
162
    d = pci_register_device(bus, "macio", sizeof(PCIDevice),
163
                            -1, NULL, NULL);
164
    /* Note: this code is strongly inspirated from the corresponding code
165
       in PearPC */
166
    d->config[0x00] = 0x6b; // vendor_id
167
    d->config[0x01] = 0x10;
168
    d->config[0x02] = device_id;
169
    d->config[0x03] = device_id >> 8;
170

    
171
    d->config[0x0a] = 0x00; // class_sub = pci2pci
172
    d->config[0x0b] = 0xff; // class_base = bridge
173
    d->config[0x0e] = 0x00; // header_type
174

    
175
    d->config[0x3d] = 0x01; // interrupt on pin 1
176
   
177
    dbdma_mem_index = cpu_register_io_memory(0, dbdma_read, dbdma_write, NULL);
178

    
179
    pci_register_io_region(d, 0, 0x80000,
180
                           PCI_ADDRESS_SPACE_MEM, macio_map);
181
}
182

    
183
/* UniN device */
184
static void unin_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
185
{
186
}
187

    
188
static uint32_t unin_readl (void *opaque, target_phys_addr_t addr)
189
{
190
    return 0;
191
}
192

    
193
static CPUWriteMemoryFunc *unin_write[] = {
194
    &unin_writel,
195
    &unin_writel,
196
    &unin_writel,
197
};
198

    
199
static CPUReadMemoryFunc *unin_read[] = {
200
    &unin_readl,
201
    &unin_readl,
202
    &unin_readl,
203
};
204

    
205
/* temporary frame buffer OSI calls for the video.x driver. The right
206
   solution is to modify the driver to use VGA PCI I/Os */
207
static int vga_osi_call(CPUState *env)
208
{
209
    static int vga_vbl_enabled;
210
    int linesize;
211
   
212
    //    printf("osi_call R5=%d\n", env->gpr[5]);
213

    
214
    /* same handler as PearPC, coming from the original MOL video
215
       driver. */
216
    switch(env->gpr[5]) {
217
    case 4:
218
        break;
219
    case 28: /* set_vmode */
220
        if (env->gpr[6] != 1 || env->gpr[7] != 0)
221
            env->gpr[3] = 1;
222
        else
223
            env->gpr[3] = 0;
224
        break;
225
    case 29: /* get_vmode_info */
226
        if (env->gpr[6] != 0) {
227
            if (env->gpr[6] != 1 || env->gpr[7] != 0) {
228
                env->gpr[3] = 1;
229
                break;
230
            }
231
        }
232
        env->gpr[3] = 0;
233
        env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
234
        env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
235
        env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */
236
        env->gpr[7] = 85 << 16; /* refresh rate */
237
        env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */
238
        linesize = ((graphic_depth + 7) >> 3) * graphic_width;
239
        linesize = (linesize + 3) & ~3;
240
        env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */
241
        break;
242
    case 31: /* set_video power */
243
        env->gpr[3] = 0;
244
        break;
245
    case 39: /* video_ctrl */
246
        if (env->gpr[6] == 0 || env->gpr[6] == 1)
247
            vga_vbl_enabled = env->gpr[6];
248
        env->gpr[3] = 0;
249
        break;
250
    case 47:
251
        break;
252
    case 59: /* set_color */
253
        /* R6 = index, R7 = RGB */
254
        env->gpr[3] = 0;
255
        break;
256
    case 64: /* get color */
257
        /* R6 = index */
258
        env->gpr[3] = 0;
259
        break;
260
    case 116: /* set hwcursor */
261
        /* R6 = x, R7 = y, R8 = visible, R9 = data */
262
        break;
263
    default:
264
        fprintf(stderr, "unsupported OSI call R5=" REGX "\n", env->gpr[5]);
265
        break;
266
    }
267
    return 1; /* osi_call handled */
268
}
269

    
270
static uint8_t nvram_chksum(const uint8_t *buf, int n)
271
{
272
    int sum, i;
273
    sum = 0;
274
    for(i = 0; i < n; i++)
275
        sum += buf[i];
276
    return (sum & 0xff) + (sum >> 8);
277
}
278

    
279
/* set a free Mac OS NVRAM partition */
280
void pmac_format_nvram_partition(uint8_t *buf, int len)
281
{
282
    char partition_name[12] = "wwwwwwwwwwww";
283
   
284
    buf[0] = 0x7f; /* free partition magic */
285
    buf[1] = 0; /* checksum */
286
    buf[2] = len >> 8;
287
    buf[3] = len;
288
    memcpy(buf + 4, partition_name, 12);
289
    buf[1] = nvram_chksum(buf, 16);
290
}   
291

    
292
/* PowerPC CHRP hardware initialisation */
293
static void ppc_chrp_init (int ram_size, int vga_ram_size, int boot_device,
294
                           DisplayState *ds, const char **fd_filename,
295
                           int snapshot,
296
                           const char *kernel_filename,
297
                           const char *kernel_cmdline,
298
                           const char *initrd_filename,
299
                           const char *cpu_model,
300
                           int is_heathrow)
301
{
302
    CPUState *env, *envs[MAX_CPUS];
303
    char buf[1024];
304
    qemu_irq *pic, **openpic_irqs;
305
    m48t59_t *nvram;
306
    int unin_memory;
307
    int linux_boot, i;
308
    unsigned long bios_offset, vga_bios_offset;
309
    uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
310
    ppc_def_t *def;
311
    PCIBus *pci_bus;
312
    const char *arch_name;
313
    int vga_bios_size, bios_size;
314
    qemu_irq *dummy_irq;
315

    
316
    linux_boot = (kernel_filename != NULL);
317

    
318
    /* init CPUs */
319
    env = cpu_init();
320
    qemu_register_reset(&cpu_ppc_reset, env);
321
    register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
322

    
323
    /* Default CPU is a generic 74x/75x */
324
    if (cpu_model == NULL)
325
        cpu_model = "750";
326
    /* XXX: CPU model (or PVR) should be provided on command line */
327
    //    ppc_find_by_name("750gx", &def); // Linux boot OK
328
    //    ppc_find_by_name("750fx", &def); // Linux boot OK
329
    /* Linux does not boot on 750cxe (and probably other 750cx based)
330
     * because it assumes it has 8 IBAT & DBAT pairs as it only have 4.
331
     */
332
    ppc_find_by_name(cpu_model, &def);
333
    if (def == NULL) {
334
        cpu_abort(env, "Unable to find PowerPC CPU definition\n");
335
    }
336
    for (i = 0; i < smp_cpus; i++) {
337
        cpu_ppc_register(env, def);
338
        /* Set time-base frequency to 100 Mhz */
339
        cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
340
        env->osi_call = vga_osi_call;
341
        envs[i] = env;
342
    }
343

    
344
    /* allocate RAM */
345
    cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
346

    
347
    /* allocate and load BIOS */
348
    bios_offset = ram_size + vga_ram_size;
349
    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
350
    bios_size = load_image(buf, phys_ram_base + bios_offset);
351
    if (bios_size < 0 || bios_size > BIOS_SIZE) {
352
        cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf);
353
        exit(1);
354
    }
355
    bios_size = (bios_size + 0xfff) & ~0xfff;
356
    cpu_register_physical_memory((uint32_t)(-bios_size),
357
                                 bios_size, bios_offset | IO_MEM_ROM);
358
   
359
    /* allocate and load VGA BIOS */
360
    vga_bios_offset = bios_offset + bios_size;
361
    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
362
    vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8);
363
    if (vga_bios_size < 0) {
364
        /* if no bios is present, we can still work */
365
        fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf);
366
        vga_bios_size = 0;
367
    } else {
368
        /* set a specific header (XXX: find real Apple format for NDRV
369
           drivers) */
370
        phys_ram_base[vga_bios_offset] = 'N';
371
        phys_ram_base[vga_bios_offset + 1] = 'D';
372
        phys_ram_base[vga_bios_offset + 2] = 'R';
373
        phys_ram_base[vga_bios_offset + 3] = 'V';
374
        cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4),
375
                     vga_bios_size);
376
        vga_bios_size += 8;
377
    }
378
    vga_bios_size = (vga_bios_size + 0xfff) & ~0xfff;
379
   
380
    if (linux_boot) {
381
        kernel_base = KERNEL_LOAD_ADDR;
382
        /* now we can load the kernel */
383
        kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
384
        if (kernel_size < 0) {
385
            cpu_abort(env, "qemu: could not load kernel '%s'\n",
386
                      kernel_filename);
387
            exit(1);
388
        }
389
        /* load initrd */
390
        if (initrd_filename) {
391
            initrd_base = INITRD_LOAD_ADDR;
392
            initrd_size = load_image(initrd_filename,
393
                                     phys_ram_base + initrd_base);
394
            if (initrd_size < 0) {
395
                cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
396
                          initrd_filename);
397
                exit(1);
398
            }
399
        } else {
400
            initrd_base = 0;
401
            initrd_size = 0;
402
        }
403
        boot_device = 'm';
404
    } else {
405
        kernel_base = 0;
406
        kernel_size = 0;
407
        initrd_base = 0;
408
        initrd_size = 0;
409
    }
410

    
411
    if (is_heathrow) {
412
        isa_mem_base = 0x80000000;
413

    
414
        /* Register 2 MB of ISA IO space */
415
        isa_mmio_init(0xfe000000, 0x00200000);
416

    
417
        /* init basic PC hardware */
418
        if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
419
            cpu_abort(env, "Only 6xx bus is supported on heathrow machine\n");
420
            exit(1);
421
        }
422
        pic = heathrow_pic_init(&heathrow_pic_mem_index);
423
        pci_bus = pci_grackle_init(0xfec00000, pic);
424
        pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,
425
                     ram_size, vga_ram_size,
426
                     vga_bios_offset, vga_bios_size);
427

    
428
        /* XXX: suppress that */
429
        dummy_irq = i8259_init(NULL);
430
       
431
        /* XXX: use Mac Serial port */
432
        serial_init(0x3f8, dummy_irq[4], serial_hds[0]);
433
       
434
        for(i = 0; i < nb_nics; i++) {
435
            if (!nd_table[i].model)
436
                nd_table[i].model = "ne2k_pci";
437
            pci_nic_init(pci_bus, &nd_table[i], -1);
438
        }
439
       
440
        pci_cmd646_ide_init(pci_bus, &bs_table[0], 0);
441

    
442
        /* cuda also initialize ADB */
443
        cuda_mem_index = cuda_init(pic[0x12]);
444
       
445
        adb_kbd_init(&adb_bus);
446
        adb_mouse_init(&adb_bus);
447
       
448
        {
449
            MacIONVRAMState *nvr;
450
            nvr = macio_nvram_init();
451
            pmac_format_nvram_partition(nvr->data, 0x2000);
452
        }
453

    
454
        macio_init(pci_bus, 0x0017);
455

    
456
        nvram = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
457

    
458
        arch_name = "HEATHROW";
459
    } else {
460
        isa_mem_base = 0x80000000;
461

    
462
        /* Register 8 MB of ISA IO space */
463
        isa_mmio_init(0xf2000000, 0x00800000);
464

    
465
        /* UniN init */
466
        unin_memory = cpu_register_io_memory(0, unin_read, unin_write, NULL);
467
        cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory);
468

    
469
        openpic_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
470
        openpic_irqs[0] =
471
            qemu_mallocz(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
472
        for (i = 0; i < smp_cpus; i++) {
473
            /* Mac99 IRQ connection between OpenPIC outputs pins
474
             * and PowerPC input pins
475
             */
476
            switch (PPC_INPUT(env)) {
477
            case PPC_FLAGS_INPUT_6xx:
478
                openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
479
                openpic_irqs[i][OPENPIC_OUTPUT_INT] =
480
                    ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
481
                openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
482
                    ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
483
                openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
484
                    ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP];
485
                /* Not connected ? */
486
                openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
487
                /* Check this */
488
                openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
489
                    ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET];
490
                break;
491
            case PPC_FLAGS_INPUT_970:
492
                openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
493
                openpic_irqs[i][OPENPIC_OUTPUT_INT] =
494
                    ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
495
                openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
496
                    ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
497
                openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
498
                    ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP];
499
                /* Not connected ? */
500
                openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
501
                /* Check this */
502
                openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
503
                    ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];
504
                break;
505
            default:
506
                cpu_abort(env,
507
                          "Only bus model not supported on mac99 machine\n");
508
                exit(1);
509
            }
510
        }
511
        pic = openpic_init(NULL, &openpic_mem_index, smp_cpus,
512
                           openpic_irqs, NULL);
513
        pci_bus = pci_pmac_init(pic);
514
        /* init basic PC hardware */
515
        pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,
516
                     ram_size, vga_ram_size,
517
                     vga_bios_offset, vga_bios_size);
518

    
519
        /* XXX: suppress that */
520
        dummy_irq = i8259_init(NULL);
521

    
522
        /* XXX: use Mac Serial port */
523
        serial_init(0x3f8, dummy_irq[4], serial_hds[0]);
524
        for(i = 0; i < nb_nics; i++) {
525
            if (!nd_table[i].model)
526
                nd_table[i].model = "ne2k_pci";
527
            pci_nic_init(pci_bus, &nd_table[i], -1);
528
        }
529
#if 1
530
        ide0_mem_index = pmac_ide_init(&bs_table[0], pic[0x13]);
531
        ide1_mem_index = pmac_ide_init(&bs_table[2], pic[0x14]);
532
#else
533
        pci_cmd646_ide_init(pci_bus, &bs_table[0], 0);
534
#endif
535
        /* cuda also initialize ADB */
536
        cuda_mem_index = cuda_init(pic[0x19]);
537
       
538
        adb_kbd_init(&adb_bus);
539
        adb_mouse_init(&adb_bus);
540
       
541
        macio_init(pci_bus, 0x0022);
542
       
543
        nvram = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
544
       
545
        arch_name = "MAC99";
546
    }
547

    
548
    if (usb_enabled) {
549
        usb_ohci_init_pci(pci_bus, 3, -1);
550
    }
551

    
552
    if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
553
        graphic_depth = 15;
554

    
555
    PPC_NVRAM_set_params(nvram, NVRAM_SIZE, arch_name, ram_size, boot_device,
556
                         kernel_base, kernel_size,
557
                         kernel_cmdline,
558
                         initrd_base, initrd_size,
559
                         /* XXX: need an option to load a NVRAM image */
560
                         0,
561
                         graphic_width, graphic_height, graphic_depth);
562
    /* No PCI init: the BIOS will do it */
563

    
564
    /* Special port to get debug messages from Open-Firmware */
565
    register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
566
}
567

    
568
static void ppc_core99_init (int ram_size, int vga_ram_size, int boot_device,
569
                             DisplayState *ds, const char **fd_filename,
570
                             int snapshot,
571
                             const char *kernel_filename,
572
                             const char *kernel_cmdline,
573
                             const char *initrd_filename,
574
                             const char *cpu_model)
575
{
576
    ppc_chrp_init(ram_size, vga_ram_size, boot_device,
577
                  ds, fd_filename, snapshot,
578
                  kernel_filename, kernel_cmdline,
579
                  initrd_filename, cpu_model, 0);
580
}
581
   
582
static void ppc_heathrow_init (int ram_size, int vga_ram_size, int boot_device,
583
                               DisplayState *ds, const char **fd_filename,
584
                               int snapshot,
585
                               const char *kernel_filename,
586
                               const char *kernel_cmdline,
587
                               const char *initrd_filename,
588
                               const char *cpu_model)
589
{
590
    ppc_chrp_init(ram_size, vga_ram_size, boot_device,
591
                  ds, fd_filename, snapshot,
592
                  kernel_filename, kernel_cmdline,
593
                  initrd_filename, cpu_model, 1);
594
}
595

    
596
QEMUMachine core99_machine = {
597
    "mac99",
598
    "Mac99 based PowerMAC",
599
    ppc_core99_init,
600
};
601

    
602
QEMUMachine heathrow_machine = {
603
    "g3bw",
604
    "Heathrow based PowerMAC",
605
    ppc_heathrow_init,
606
};