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/*
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 * QEMU PREP PCI host
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 *
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 * Copyright (c) 2006 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "vl.h"
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typedef uint32_t pci_addr_t;
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#include "pci_host.h"
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typedef PCIHostState PREPPCIState;
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static void pci_prep_addr_writel(void* opaque, uint32_t addr, uint32_t val)
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{
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    PREPPCIState *s = opaque;
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    s->config_reg = val;
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}
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static uint32_t pci_prep_addr_readl(void* opaque, uint32_t addr)
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{
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    PREPPCIState *s = opaque;
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    return s->config_reg;
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}
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static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr)
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{
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    int i;
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    for(i = 0; i < 11; i++) {
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        if ((addr & (1 << (11 + i))) != 0)
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            break;
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    }
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    return (addr & 0x7ff) |  (i << 11);
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}
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static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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    PREPPCIState *s = opaque;
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    pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 1);
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}
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static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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    PREPPCIState *s = opaque;
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#ifdef TARGET_WORDS_BIGENDIAN
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    val = bswap16(val);
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#endif
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    pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 2);
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}
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static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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    PREPPCIState *s = opaque;
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#ifdef TARGET_WORDS_BIGENDIAN
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    val = bswap32(val);
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#endif
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    pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 4);
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}
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static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr)
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{
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    PREPPCIState *s = opaque;
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    uint32_t val;
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    val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 1);
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    return val;
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}
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static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr)
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{
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    PREPPCIState *s = opaque;
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    uint32_t val;
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    val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 2);
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#ifdef TARGET_WORDS_BIGENDIAN
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    val = bswap16(val);
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#endif
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    return val;
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}
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static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)
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{
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    PREPPCIState *s = opaque;
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    uint32_t val;
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    val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 4);
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#ifdef TARGET_WORDS_BIGENDIAN
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    val = bswap32(val);
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#endif
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    return val;
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}
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static CPUWriteMemoryFunc *PPC_PCIIO_write[] = {
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    &PPC_PCIIO_writeb,
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    &PPC_PCIIO_writew,
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    &PPC_PCIIO_writel,
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};
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static CPUReadMemoryFunc *PPC_PCIIO_read[] = {
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    &PPC_PCIIO_readb,
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    &PPC_PCIIO_readw,
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    &PPC_PCIIO_readl,
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};
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/* Don't know if this matches real hardware, but it agrees with OHW.  */
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static int prep_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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    return (irq_num + (pci_dev->devfn >> 3)) & 1;
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}
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static void prep_set_irq(qemu_irq *pic, int irq_num, int level)
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{
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    qemu_set_irq(pic[irq_num ? 11 : 9], level);
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}
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PCIBus *pci_prep_init(qemu_irq *pic)
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{
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    PREPPCIState *s;
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    PCIDevice *d;
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    int PPC_io_memory;
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    s = qemu_mallocz(sizeof(PREPPCIState));
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    s->bus = pci_register_bus(prep_set_irq, prep_map_irq, pic, 0, 2);
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    register_ioport_write(0xcf8, 4, 4, pci_prep_addr_writel, s);
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    register_ioport_read(0xcf8, 4, 4, pci_prep_addr_readl, s);
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    register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s);
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    register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s);
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    register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s);
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    register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s);
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    register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
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    register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
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    PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read,
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                                           PPC_PCIIO_write, s);
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    cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);
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    /* PCI host bridge */
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    d = pci_register_device(s->bus, "PREP Host Bridge - Motorola Raven",
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                            sizeof(PCIDevice), 0, NULL, NULL);
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    d->config[0x00] = 0x57; // vendor_id : Motorola
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    d->config[0x01] = 0x10;
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    d->config[0x02] = 0x01; // device_id : Raven
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    d->config[0x03] = 0x48;
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    d->config[0x08] = 0x00; // revision
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    d->config[0x0A] = 0x00; // class_sub = pci host
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    d->config[0x0B] = 0x06; // class_base = PCI_bridge
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    d->config[0x0C] = 0x08; // cache_line_size
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    d->config[0x0D] = 0x10; // latency_timer
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    d->config[0x0E] = 0x00; // header_type
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    d->config[0x34] = 0x00; // capabilities_pointer
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    return s->bus;
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}
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