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/*
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 * QEMU Sparc SLAVIO timer controller emulation
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 *
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 * Copyright (c) 2003-2005 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "vl.h"
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//#define DEBUG_TIMER
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#ifdef DEBUG_TIMER
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#define DPRINTF(fmt, args...) \
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do { printf("TIMER: " fmt , ##args); } while (0)
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#else
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#define DPRINTF(fmt, args...)
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#endif
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/*
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 * Registers of hardware timer in sun4m.
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 *
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 * This is the timer/counter part of chip STP2001 (Slave I/O), also
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 * produced as NCR89C105. See
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 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
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 *
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 * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
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 * are zero. Bit 31 is 1 when count has been reached.
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 *
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 * Per-CPU timers interrupt local CPU, system timer uses normal
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 * interrupt routing.
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 *
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 */
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typedef struct SLAVIO_TIMERState {
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    qemu_irq irq;
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    ptimer_state *timer;
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    uint32_t count, counthigh, reached;
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    uint64_t limit;
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    int stopped;
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    int mode; // 0 = processor, 1 = user, 2 = system
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} SLAVIO_TIMERState;
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#define TIMER_MAXADDR 0x1f
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#define TIMER_SIZE (TIMER_MAXADDR + 1)
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// Update count, set irq, update expire_time
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// Convert from ptimer countdown units
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static void slavio_timer_get_out(SLAVIO_TIMERState *s)
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{
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    uint64_t count;
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    count = s->limit - (ptimer_get_count(s->timer) << 9);
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    DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", s->limit, s->counthigh,
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            s->count);
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    s->count = count & 0xfffffe00;
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    s->counthigh = count >> 32;
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}
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// timer callback
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static void slavio_timer_irq(void *opaque)
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{
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    SLAVIO_TIMERState *s = opaque;
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    slavio_timer_get_out(s);
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    DPRINTF("callback: count %x%08x\n", s->counthigh, s->count);
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    s->reached = 0x80000000;
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    if (s->mode != 1)
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        qemu_irq_raise(s->irq);
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}
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static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
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{
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    SLAVIO_TIMERState *s = opaque;
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    uint32_t saddr, ret;
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    saddr = (addr & TIMER_MAXADDR) >> 2;
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    switch (saddr) {
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    case 0:
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        // read limit (system counter mode) or read most signifying
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        // part of counter (user mode)
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        if (s->mode != 1) {
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            // clear irq
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            qemu_irq_lower(s->irq);
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            s->reached = 0;
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            ret = s->limit & 0x7fffffff;
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        }
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        else {
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            slavio_timer_get_out(s);
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            ret = s->counthigh & 0x7fffffff;
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        }
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        break;
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    case 1:
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        // read counter and reached bit (system mode) or read lsbits
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        // of counter (user mode)
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        slavio_timer_get_out(s);
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        if (s->mode != 1)
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            ret = (s->count & 0x7fffffff) | s->reached;
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        else
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            ret = s->count;
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        break;
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    case 3:
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        // read start/stop status
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        ret = s->stopped;
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        break;
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    case 4:
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        // read user/system mode
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        ret = s->mode & 1;
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        break;
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    default:
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        ret = 0;
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        break;
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    }
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    DPRINTF("read " TARGET_FMT_plx " = %08x\n", addr, ret);
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    return ret;
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}
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static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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    SLAVIO_TIMERState *s = opaque;
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    uint32_t saddr;
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    int reload = 0;
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    DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val);
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    saddr = (addr & TIMER_MAXADDR) >> 2;
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    switch (saddr) {
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    case 0:
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        // set limit, reset counter
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        reload = 1;
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        qemu_irq_lower(s->irq);
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        // fall through
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    case 2:
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        // set limit without resetting counter
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        s->limit = val & 0x7ffffe00ULL;
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        if (!s->limit)
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            s->limit = 0x7ffffe00ULL;
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        ptimer_set_limit(s->timer, s->limit >> 9, reload);
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        break;
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    case 3:
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        // start/stop user counter
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        if (s->mode == 1) {
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            if (val & 1) {
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                ptimer_stop(s->timer);
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                s->stopped = 1;
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            }
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            else {
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                ptimer_run(s->timer, 0);
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                s->stopped = 0;
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            }
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        }
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        break;
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    case 4:
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        // bit 0: user (1) or system (0) counter mode
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        if (s->mode == 0 || s->mode == 1)
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            s->mode = val & 1;
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        if (s->mode == 1) {
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            qemu_irq_lower(s->irq);
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            s->limit = -1ULL;
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        }
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        ptimer_set_limit(s->timer, s->limit >> 9, 1);
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        break;
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    default:
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        break;
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    }
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}
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static CPUReadMemoryFunc *slavio_timer_mem_read[3] = {
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    slavio_timer_mem_readl,
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    slavio_timer_mem_readl,
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    slavio_timer_mem_readl,
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};
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static CPUWriteMemoryFunc *slavio_timer_mem_write[3] = {
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    slavio_timer_mem_writel,
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    slavio_timer_mem_writel,
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    slavio_timer_mem_writel,
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};
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static void slavio_timer_save(QEMUFile *f, void *opaque)
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{
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    SLAVIO_TIMERState *s = opaque;
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    qemu_put_be64s(f, &s->limit);
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    qemu_put_be32s(f, &s->count);
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    qemu_put_be32s(f, &s->counthigh);
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    qemu_put_be32(f, 0); // Was irq
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    qemu_put_be32s(f, &s->reached);
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    qemu_put_be32s(f, &s->stopped);
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    qemu_put_be32s(f, &s->mode);
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    qemu_put_ptimer(f, s->timer);
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}
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static int slavio_timer_load(QEMUFile *f, void *opaque, int version_id)
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{
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    SLAVIO_TIMERState *s = opaque;
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    uint32_t tmp;
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    if (version_id != 2)
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        return -EINVAL;
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    qemu_get_be64s(f, &s->limit);
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    qemu_get_be32s(f, &s->count);
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    qemu_get_be32s(f, &s->counthigh);
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    qemu_get_be32s(f, &tmp); // Was irq
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    qemu_get_be32s(f, &s->reached);
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    qemu_get_be32s(f, &s->stopped);
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    qemu_get_be32s(f, &s->mode);
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    qemu_get_ptimer(f, s->timer);
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    return 0;
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}
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static void slavio_timer_reset(void *opaque)
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{
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    SLAVIO_TIMERState *s = opaque;
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    s->limit = 0x7ffffe00ULL;
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    s->count = 0;
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    s->reached = 0;
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    s->mode &= 2;
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    ptimer_set_limit(s->timer, s->limit >> 9, 1);
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    ptimer_run(s->timer, 0);
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    s->stopped = 1;
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    qemu_irq_lower(s->irq);
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}
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void slavio_timer_init(target_phys_addr_t addr, qemu_irq irq, int mode)
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{
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    int slavio_timer_io_memory;
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    SLAVIO_TIMERState *s;
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    QEMUBH *bh;
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    s = qemu_mallocz(sizeof(SLAVIO_TIMERState));
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    if (!s)
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        return;
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    s->irq = irq;
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    s->mode = mode;
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    bh = qemu_bh_new(slavio_timer_irq, s);
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    s->timer = ptimer_init(bh);
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    ptimer_set_period(s->timer, 500ULL);
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    slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,
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                                                    slavio_timer_mem_write, s);
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    cpu_register_physical_memory(addr, TIMER_SIZE, slavio_timer_io_memory);
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    register_savevm("slavio_timer", addr, 2, slavio_timer_save, slavio_timer_load, s);
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    qemu_register_reset(slavio_timer_reset, s);
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    slavio_timer_reset(s);
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}