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/*
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 * ARM Versatile Platform/Application Baseboard System emulation.
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 *
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 * Copyright (c) 2005-2007 CodeSourcery.
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 * Written by Paul Brook
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 *
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 * This code is licenced under the GPL.
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 */
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#include "vl.h"
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#include "arm_pic.h"
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/* Primary interrupt controller.  */
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typedef struct vpb_sic_state
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{
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  uint32_t base;
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  uint32_t level;
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  uint32_t mask;
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  uint32_t pic_enable;
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  qemu_irq *parent;
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  int irq;
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} vpb_sic_state;
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static void vpb_sic_update(vpb_sic_state *s)
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{
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    uint32_t flags;
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    flags = s->level & s->mask;
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    qemu_set_irq(s->parent[s->irq], flags != 0);
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}
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static void vpb_sic_update_pic(vpb_sic_state *s)
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{
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    int i;
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    uint32_t mask;
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    for (i = 21; i <= 30; i++) {
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        mask = 1u << i;
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        if (!(s->pic_enable & mask))
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            continue;
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        qemu_set_irq(s->parent[i], (s->level & mask) != 0);
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    }
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}
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static void vpb_sic_set_irq(void *opaque, int irq, int level)
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{
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    vpb_sic_state *s = (vpb_sic_state *)opaque;
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    if (level)
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        s->level |= 1u << irq;
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    else
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        s->level &= ~(1u << irq);
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    if (s->pic_enable & (1u << irq))
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        qemu_set_irq(s->parent[irq], level);
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    vpb_sic_update(s);
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}
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static uint32_t vpb_sic_read(void *opaque, target_phys_addr_t offset)
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{
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    vpb_sic_state *s = (vpb_sic_state *)opaque;
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    offset -= s->base;
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    switch (offset >> 2) {
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    case 0: /* STATUS */
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        return s->level & s->mask;
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    case 1: /* RAWSTAT */
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        return s->level;
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    case 2: /* ENABLE */
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        return s->mask;
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    case 4: /* SOFTINT */
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        return s->level & 1;
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    case 8: /* PICENABLE */
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        return s->pic_enable;
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    default:
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        printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset);
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        return 0;
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    }
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}
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static void vpb_sic_write(void *opaque, target_phys_addr_t offset,
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                          uint32_t value)
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{
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    vpb_sic_state *s = (vpb_sic_state *)opaque;
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    offset -= s->base;
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    switch (offset >> 2) {
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    case 2: /* ENSET */
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        s->mask |= value;
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        break;
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    case 3: /* ENCLR */
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        s->mask &= ~value;
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        break;
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    case 4: /* SOFTINTSET */
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        if (value)
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            s->mask |= 1;
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        break;
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    case 5: /* SOFTINTCLR */
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        if (value)
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            s->mask &= ~1u;
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        break;
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    case 8: /* PICENSET */
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        s->pic_enable |= (value & 0x7fe00000);
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        vpb_sic_update_pic(s);
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        break;
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    case 9: /* PICENCLR */
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        s->pic_enable &= ~value;
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        vpb_sic_update_pic(s);
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        break;
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    default:
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        printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset);
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        return;
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    }
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    vpb_sic_update(s);
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}
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static CPUReadMemoryFunc *vpb_sic_readfn[] = {
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   vpb_sic_read,
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   vpb_sic_read,
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   vpb_sic_read
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};
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static CPUWriteMemoryFunc *vpb_sic_writefn[] = {
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   vpb_sic_write,
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   vpb_sic_write,
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   vpb_sic_write
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};
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static qemu_irq *vpb_sic_init(uint32_t base, qemu_irq *parent, int irq)
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{
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    vpb_sic_state *s;
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    qemu_irq *qi;
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    int iomemtype;
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    s = (vpb_sic_state *)qemu_mallocz(sizeof(vpb_sic_state));
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    if (!s)
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        return NULL;
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    qi = qemu_allocate_irqs(vpb_sic_set_irq, s, 32);
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    s->base = base;
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    s->parent = parent;
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    s->irq = irq;
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    iomemtype = cpu_register_io_memory(0, vpb_sic_readfn,
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                                       vpb_sic_writefn, s);
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    cpu_register_physical_memory(base, 0x00001000, iomemtype);
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    /* ??? Save/restore.  */
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    return qi;
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}
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/* Board init.  */
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/* The AB and PB boards both use the same core, just with different
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   peripherans and expansion busses.  For now we emulate a subset of the
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   PB peripherals and just change the board ID.  */
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static void versatile_init(int ram_size, int vga_ram_size, int boot_device,
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                     DisplayState *ds, const char **fd_filename, int snapshot,
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                     const char *kernel_filename, const char *kernel_cmdline,
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                     const char *initrd_filename, const char *cpu_model,
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                     int board_id)
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{
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    CPUState *env;
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    qemu_irq *pic;
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    qemu_irq *sic;
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    void *scsi_hba;
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    PCIBus *pci_bus;
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    NICInfo *nd;
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    int n;
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    int done_smc = 0;
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    env = cpu_init();
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    if (!cpu_model)
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        cpu_model = "arm926";
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    cpu_arm_set_model(env, cpu_model);
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    /* ??? RAM shoud repeat to fill physical memory space.  */
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    /* SDRAM at address zero.  */
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    cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
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    arm_sysctl_init(0x10000000, 0x41007004);
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    pic = arm_pic_init_cpu(env);
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    pic = pl190_init(0x10140000, pic[0], pic[1]);
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    sic = vpb_sic_init(0x10003000, pic, 31);
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    pl050_init(0x10006000, sic[3], 0);
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    pl050_init(0x10007000, sic[4], 1);
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    pci_bus = pci_vpb_init(sic, 27, 0);
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    /* The Versatile PCI bridge does not provide access to PCI IO space,
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       so many of the qemu PCI devices are not useable.  */
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    for(n = 0; n < nb_nics; n++) {
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        nd = &nd_table[n];
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        if (!nd->model)
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            nd->model = done_smc ? "rtl8139" : "smc91c111";
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        if (strcmp(nd->model, "smc91c111") == 0) {
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            smc91c111_init(nd, 0x10010000, sic[25]);
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        } else {
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            pci_nic_init(pci_bus, nd, -1);
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        }
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    }
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    if (usb_enabled) {
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        usb_ohci_init_pci(pci_bus, 3, -1);
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    }
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    scsi_hba = lsi_scsi_init(pci_bus, -1);
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    for (n = 0; n < MAX_DISKS; n++) {
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        if (bs_table[n]) {
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            lsi_scsi_attach(scsi_hba, bs_table[n], n);
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        }
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    }
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    pl011_init(0x101f1000, pic[12], serial_hds[0]);
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    pl011_init(0x101f2000, pic[13], serial_hds[1]);
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    pl011_init(0x101f3000, pic[14], serial_hds[2]);
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    pl011_init(0x10009000, sic[6], serial_hds[3]);
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    pl080_init(0x10130000, pic[17], 8);
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    sp804_init(0x101e2000, pic[4]);
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    sp804_init(0x101e3000, pic[5]);
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    /* The versatile/PB actually has a modified Color LCD controller
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       that includes hardware cursor support from the PL111.  */
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    pl110_init(ds, 0x10120000, pic[16], 1);
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    pl181_init(0x10005000, sd_bdrv, sic[22], sic[1]);
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#if 0
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    /* Disabled because there's no way of specifying a block device.  */
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    pl181_init(0x1000b000, NULL, sic, 23, 2);
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#endif
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    /* Add PL031 Real Time Clock. */
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    pl031_init(0x101e8000,pic[10]);
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    /* Memory map for Versatile/PB:  */
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    /* 0x10000000 System registers.  */
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    /* 0x10001000 PCI controller config registers.  */
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    /* 0x10002000 Serial bus interface.  */
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    /*  0x10003000 Secondary interrupt controller.  */
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    /* 0x10004000 AACI (audio).  */
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    /*  0x10005000 MMCI0.  */
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    /*  0x10006000 KMI0 (keyboard).  */
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    /*  0x10007000 KMI1 (mouse).  */
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    /* 0x10008000 Character LCD Interface.  */
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    /*  0x10009000 UART3.  */
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    /* 0x1000a000 Smart card 1.  */
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    /*  0x1000b000 MMCI1.  */
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    /*  0x10010000 Ethernet.  */
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    /* 0x10020000 USB.  */
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    /* 0x10100000 SSMC.  */
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    /* 0x10110000 MPMC.  */
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    /*  0x10120000 CLCD Controller.  */
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    /*  0x10130000 DMA Controller.  */
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    /*  0x10140000 Vectored interrupt controller.  */
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    /* 0x101d0000 AHB Monitor Interface.  */
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    /* 0x101e0000 System Controller.  */
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    /* 0x101e1000 Watchdog Interface.  */
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    /* 0x101e2000 Timer 0/1.  */
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    /* 0x101e3000 Timer 2/3.  */
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    /* 0x101e4000 GPIO port 0.  */
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    /* 0x101e5000 GPIO port 1.  */
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    /* 0x101e6000 GPIO port 2.  */
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    /* 0x101e7000 GPIO port 3.  */
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    /* 0x101e8000 RTC.  */
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    /* 0x101f0000 Smart card 0.  */
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    /*  0x101f1000 UART0.  */
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    /*  0x101f2000 UART1.  */
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    /*  0x101f3000 UART2.  */
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    /* 0x101f4000 SSPI.  */
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    arm_load_kernel(env, ram_size, kernel_filename, kernel_cmdline,
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                    initrd_filename, board_id, 0x0);
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}
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static void vpb_init(int ram_size, int vga_ram_size, int boot_device,
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                     DisplayState *ds, const char **fd_filename, int snapshot,
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                     const char *kernel_filename, const char *kernel_cmdline,
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                     const char *initrd_filename, const char *cpu_model)
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{
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    versatile_init(ram_size, vga_ram_size, boot_device,
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                   ds, fd_filename, snapshot,
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                   kernel_filename, kernel_cmdline,
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                   initrd_filename, cpu_model, 0x183);
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}
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static void vab_init(int ram_size, int vga_ram_size, int boot_device,
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                     DisplayState *ds, const char **fd_filename, int snapshot,
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                     const char *kernel_filename, const char *kernel_cmdline,
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                     const char *initrd_filename, const char *cpu_model)
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{
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    versatile_init(ram_size, vga_ram_size, boot_device,
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                   ds, fd_filename, snapshot,
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                   kernel_filename, kernel_cmdline,
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                   initrd_filename, cpu_model, 0x25e);
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}
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QEMUMachine versatilepb_machine = {
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    "versatilepb",
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    "ARM Versatile/PB (ARM926EJ-S)",
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    vpb_init,
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};
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QEMUMachine versatileab_machine = {
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    "versatileab",
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    "ARM Versatile/AB (ARM926EJ-S)",
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    vab_init,
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};