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/* Print mips instructions for GDB, the GNU debugger, or for objdump.
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   Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
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   2000, 2001, 2002, 2003
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   Free Software Foundation, Inc.
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   Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
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This file is part of GDB, GAS, and the GNU binutils.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
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#include "dis-asm.h"
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/* mips.h.  Mips opcode list for GDB, the GNU debugger.
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   Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
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   Free Software Foundation, Inc.
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   Contributed by Ralph Campbell and OSF
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   Commented and modified by Ian Lance Taylor, Cygnus Support
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This file is part of GDB, GAS, and the GNU binutils.
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GDB, GAS, and the GNU binutils are free software; you can redistribute
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them and/or modify them under the terms of the GNU General Public
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License as published by the Free Software Foundation; either version
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1, or (at your option) any later version.
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GDB, GAS, and the GNU binutils are distributed in the hope that they
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will be useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
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the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
44
along with this file; see the file COPYING.  If not, write to the Free
45
Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
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/* mips.h.  Mips opcode list for GDB, the GNU debugger.
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   Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
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   Free Software Foundation, Inc.
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   Contributed by Ralph Campbell and OSF
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   Commented and modified by Ian Lance Taylor, Cygnus Support
52

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This file is part of GDB, GAS, and the GNU binutils.
54

55
GDB, GAS, and the GNU binutils are free software; you can redistribute
56
them and/or modify them under the terms of the GNU General Public
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License as published by the Free Software Foundation; either version
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1, or (at your option) any later version.
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GDB, GAS, and the GNU binutils are distributed in the hope that they
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will be useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
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the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
66
along with this file; see the file COPYING.  If not, write to the Free
67
Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
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/* These are bit masks and shift counts to use to access the various
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   fields of an instruction.  To retrieve the X field of an
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   instruction, use the expression
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        (i >> OP_SH_X) & OP_MASK_X
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   To set the same field (to j), use
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        i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
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   Make sure you use fields that are appropriate for the instruction,
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   of course.
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   The 'i' format uses OP, RS, RT and IMMEDIATE.
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   The 'j' format uses OP and TARGET.
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   The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
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   The 'b' format uses OP, RS, RT and DELTA.
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   The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
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   The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
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   A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
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   breakpoint instruction are not defined; Kane says the breakpoint
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   code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
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   only use ten bits).  An optional two-operand form of break/sdbbp
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   allows the lower ten bits to be set too, and MIPS32 and later
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   architectures allow 20 bits to be set with a signal operand
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   (using CODE20).
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   The syscall instruction uses CODE20.
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   The general coprocessor instructions use COPZ.  */
102

    
103
#define OP_MASK_OP                0x3f
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#define OP_SH_OP                26
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#define OP_MASK_RS                0x1f
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#define OP_SH_RS                21
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#define OP_MASK_FR                0x1f
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#define OP_SH_FR                21
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#define OP_MASK_FMT                0x1f
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#define OP_SH_FMT                21
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#define OP_MASK_BCC                0x7
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#define OP_SH_BCC                18
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#define OP_MASK_CODE                0x3ff
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#define OP_SH_CODE                16
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#define OP_MASK_CODE2                0x3ff
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#define OP_SH_CODE2                6
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#define OP_MASK_RT                0x1f
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#define OP_SH_RT                16
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#define OP_MASK_FT                0x1f
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#define OP_SH_FT                16
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#define OP_MASK_CACHE                0x1f
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#define OP_SH_CACHE                16
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#define OP_MASK_RD                0x1f
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#define OP_SH_RD                11
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#define OP_MASK_FS                0x1f
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#define OP_SH_FS                11
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#define OP_MASK_PREFX                0x1f
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#define OP_SH_PREFX                11
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#define OP_MASK_CCC                0x7
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#define OP_SH_CCC                8
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#define OP_MASK_CODE20                0xfffff /* 20 bit syscall/breakpoint code.  */
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#define OP_SH_CODE20                6
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#define OP_MASK_SHAMT                0x1f
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#define OP_SH_SHAMT                6
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#define OP_MASK_FD                0x1f
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#define OP_SH_FD                6
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#define OP_MASK_TARGET                0x3ffffff
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#define OP_SH_TARGET                0
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#define OP_MASK_COPZ                0x1ffffff
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#define OP_SH_COPZ                0
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#define OP_MASK_IMMEDIATE        0xffff
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#define OP_SH_IMMEDIATE                0
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#define OP_MASK_DELTA                0xffff
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#define OP_SH_DELTA                0
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#define OP_MASK_FUNCT                0x3f
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#define OP_SH_FUNCT                0
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#define OP_MASK_SPEC                0x3f
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#define OP_SH_SPEC                0
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#define OP_SH_LOCC              8       /* FP condition code.  */
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#define OP_SH_HICC              18      /* FP condition code.  */
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#define OP_MASK_CC              0x7
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#define OP_SH_COP1NORM          25      /* Normal COP1 encoding.  */
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#define OP_MASK_COP1NORM        0x1     /* a single bit.  */
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#define OP_SH_COP1SPEC          21      /* COP1 encodings.  */
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#define OP_MASK_COP1SPEC        0xf
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#define OP_MASK_COP1SCLR        0x4
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#define OP_MASK_COP1CMP         0x3
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#define OP_SH_COP1CMP           4
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#define OP_SH_FORMAT            21      /* FP short format field.  */
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#define OP_MASK_FORMAT          0x7
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#define OP_SH_TRUE              16
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#define OP_MASK_TRUE            0x1
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#define OP_SH_GE                17
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#define OP_MASK_GE              0x01
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#define OP_SH_UNSIGNED          16
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#define OP_MASK_UNSIGNED        0x1
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#define OP_SH_HINT              16
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#define OP_MASK_HINT            0x1f
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#define OP_SH_MMI               0       /* Multimedia (parallel) op.  */
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#define OP_MASK_MMI             0x3f
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#define OP_SH_MMISUB            6
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#define OP_MASK_MMISUB          0x1f
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#define OP_MASK_PERFREG                0x1f        /* Performance monitoring.  */
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#define OP_SH_PERFREG                1
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#define OP_SH_SEL                0        /* Coprocessor select field.  */
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#define OP_MASK_SEL                0x7        /* The sel field of mfcZ and mtcZ.  */
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#define OP_SH_CODE19                6       /* 19 bit wait code.  */
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#define OP_MASK_CODE19                0x7ffff
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#define OP_SH_ALN                21
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#define OP_MASK_ALN                0x7
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#define OP_SH_VSEL                21
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#define OP_MASK_VSEL                0x1f
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#define OP_MASK_VECBYTE                0x7        /* Selector field is really 4 bits,
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                                           but 0x8-0xf don't select bytes.  */
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#define OP_SH_VECBYTE                22
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#define OP_MASK_VECALIGN        0x7        /* Vector byte-align (alni.ob) op.  */
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#define OP_SH_VECALIGN                21
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#define OP_MASK_INSMSB                0x1f        /* "ins" MSB.  */
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#define OP_SH_INSMSB                11
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#define OP_MASK_EXTMSBD                0x1f        /* "ext" MSBD.  */
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#define OP_SH_EXTMSBD                11
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#define        OP_OP_COP0                0x10
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#define        OP_OP_COP1                0x11
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#define        OP_OP_COP2                0x12
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#define        OP_OP_COP3                0x13
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#define        OP_OP_LWC1                0x31
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#define        OP_OP_LWC2                0x32
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#define        OP_OP_LWC3                0x33        /* a.k.a. pref */
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#define        OP_OP_LDC1                0x35
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#define        OP_OP_LDC2                0x36
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#define        OP_OP_LDC3                0x37        /* a.k.a. ld */
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#define        OP_OP_SWC1                0x39
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#define        OP_OP_SWC2                0x3a
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#define        OP_OP_SWC3                0x3b
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#define        OP_OP_SDC1                0x3d
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#define        OP_OP_SDC2                0x3e
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#define        OP_OP_SDC3                0x3f        /* a.k.a. sd */
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/* MIPS DSP ASE */
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#define OP_SH_DSPACC                11
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#define OP_MASK_DSPACC          0x3
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#define OP_SH_DSPACC_S          21
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#define OP_MASK_DSPACC_S        0x3
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#define OP_SH_DSPSFT                20
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#define OP_MASK_DSPSFT          0x3f
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#define OP_SH_DSPSFT_7          19
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#define OP_MASK_DSPSFT_7        0x7f
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#define OP_SH_SA3                21
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#define OP_MASK_SA3                0x7
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#define OP_SH_SA4                21
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#define OP_MASK_SA4                0xf
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#define OP_SH_IMM8                16
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#define OP_MASK_IMM8                0xff
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#define OP_SH_IMM10                16
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#define OP_MASK_IMM10                0x3ff
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#define OP_SH_WRDSP                11
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#define OP_MASK_WRDSP                0x3f
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#define OP_SH_RDDSP                16
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#define OP_MASK_RDDSP                0x3f
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#define OP_SH_BP                11
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#define OP_MASK_BP                0x3
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/* MIPS MT ASE */
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#define OP_SH_MT_U                5
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#define OP_MASK_MT_U                0x1
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#define OP_SH_MT_H                4
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#define OP_MASK_MT_H                0x1
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#define OP_SH_MTACC_T                18
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#define OP_MASK_MTACC_T                0x3
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#define OP_SH_MTACC_D                13
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#define OP_MASK_MTACC_D                0x3
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#define        OP_OP_COP0                0x10
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#define        OP_OP_COP1                0x11
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#define        OP_OP_COP2                0x12
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#define        OP_OP_COP3                0x13
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#define        OP_OP_LWC1                0x31
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#define        OP_OP_LWC2                0x32
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#define        OP_OP_LWC3                0x33        /* a.k.a. pref */
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#define        OP_OP_LDC1                0x35
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#define        OP_OP_LDC2                0x36
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#define        OP_OP_LDC3                0x37        /* a.k.a. ld */
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#define        OP_OP_SWC1                0x39
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#define        OP_OP_SWC2                0x3a
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#define        OP_OP_SWC3                0x3b
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#define        OP_OP_SDC1                0x3d
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#define        OP_OP_SDC2                0x3e
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#define        OP_OP_SDC3                0x3f        /* a.k.a. sd */
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/* Values in the 'VSEL' field.  */
262
#define MDMX_FMTSEL_IMM_QH        0x1d
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#define MDMX_FMTSEL_IMM_OB        0x1e
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#define MDMX_FMTSEL_VEC_QH        0x15
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#define MDMX_FMTSEL_VEC_OB        0x16
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/* UDI */
268
#define OP_SH_UDI1                6
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#define OP_MASK_UDI1                0x1f
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#define OP_SH_UDI2                6
271
#define OP_MASK_UDI2                0x3ff
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#define OP_SH_UDI3                6
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#define OP_MASK_UDI3                0x7fff
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#define OP_SH_UDI4                6
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#define OP_MASK_UDI4                0xfffff
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/* This structure holds information for a particular instruction.  */
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struct mips_opcode
279
{
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  /* The name of the instruction.  */
281
  const char *name;
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  /* A string describing the arguments for this instruction.  */
283
  const char *args;
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  /* The basic opcode for the instruction.  When assembling, this
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     opcode is modified by the arguments to produce the actual opcode
286
     that is used.  If pinfo is INSN_MACRO, then this is 0.  */
287
  unsigned long match;
288
  /* If pinfo is not INSN_MACRO, then this is a bit mask for the
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     relevant portions of the opcode when disassembling.  If the
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     actual opcode anded with the match field equals the opcode field,
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     then we have found the correct instruction.  If pinfo is
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     INSN_MACRO, then this field is the macro identifier.  */
293
  unsigned long mask;
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  /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
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     of bits describing the instruction, notably any relevant hazard
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     information.  */
297
  unsigned long pinfo;
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  /* A collection of additional bits describing the instruction. */
299
  unsigned long pinfo2;
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  /* A collection of bits describing the instruction sets of which this
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     instruction or macro is a member. */
302
  unsigned long membership;
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};
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/* These are the characters which may appear in the args field of an
306
   instruction.  They appear in the order in which the fields appear
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   when the instruction is used.  Commas and parentheses in the args
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   string are ignored when assembling, and written into the output
309
   when disassembling.
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311
   Each of these characters corresponds to a mask field defined above.
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313
   "<" 5 bit shift amount (OP_*_SHAMT)
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   ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
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   "a" 26 bit target address (OP_*_TARGET)
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   "b" 5 bit base register (OP_*_RS)
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   "c" 10 bit breakpoint code (OP_*_CODE)
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   "d" 5 bit destination register specifier (OP_*_RD)
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   "h" 5 bit prefx hint (OP_*_PREFX)
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   "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
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   "j" 16 bit signed immediate (OP_*_DELTA)
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   "k" 5 bit cache opcode in target register position (OP_*_CACHE)
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       Also used for immediate operands in vr5400 vector insns.
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   "o" 16 bit signed offset (OP_*_DELTA)
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   "p" 16 bit PC relative branch target address (OP_*_DELTA)
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   "q" 10 bit extra breakpoint code (OP_*_CODE2)
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   "r" 5 bit same register used as both source and target (OP_*_RS)
328
   "s" 5 bit source register specifier (OP_*_RS)
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   "t" 5 bit target register (OP_*_RT)
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   "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
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   "v" 5 bit same register used as both source and destination (OP_*_RS)
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   "w" 5 bit same register used as both target and destination (OP_*_RT)
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   "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
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       (used by clo and clz)
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   "C" 25 bit coprocessor function code (OP_*_COPZ)
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   "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
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   "J" 19 bit wait function code (OP_*_CODE19)
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   "x" accept and ignore register name
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   "z" must be zero register
340
   "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
341
   "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
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        LSB (OP_*_SHAMT).
343
        Enforces: 0 <= pos < 32.
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   "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
345
        Requires that "+A" or "+E" occur first to set position.
346
        Enforces: 0 < (pos+size) <= 32.
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   "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
348
        Requires that "+A" or "+E" occur first to set position.
349
        Enforces: 0 < (pos+size) <= 32.
350
        (Also used by "dext" w/ different limits, but limits for
351
        that are checked by the M_DEXT macro.)
352
   "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
353
        Enforces: 32 <= pos < 64.
354
   "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
355
        Requires that "+A" or "+E" occur first to set position.
356
        Enforces: 32 < (pos+size) <= 64.
357
   "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
358
        Requires that "+A" or "+E" occur first to set position.
359
        Enforces: 32 < (pos+size) <= 64.
360
   "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
361
        Requires that "+A" or "+E" occur first to set position.
362
        Enforces: 32 < (pos+size) <= 64.
363

364
   Floating point instructions:
365
   "D" 5 bit destination register (OP_*_FD)
366
   "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
367
   "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
368
   "S" 5 bit fs source 1 register (OP_*_FS)
369
   "T" 5 bit ft source 2 register (OP_*_FT)
370
   "R" 5 bit fr source 3 register (OP_*_FR)
371
   "V" 5 bit same register used as floating source and destination (OP_*_FS)
372
   "W" 5 bit same register used as floating target and destination (OP_*_FT)
373

374
   Coprocessor instructions:
375
   "E" 5 bit target register (OP_*_RT)
376
   "G" 5 bit destination register (OP_*_RD)
377
   "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
378
   "P" 5 bit performance-monitor register (OP_*_PERFREG)
379
   "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
380
   "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
381
   see also "k" above
382
   "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
383
        for pretty-printing in disassembly only.
384

385
   Macro instructions:
386
   "A" General 32 bit expression
387
   "I" 32 bit immediate (value placed in imm_expr).
388
   "+I" 32 bit immediate (value placed in imm2_expr).
389
   "F" 64 bit floating point constant in .rdata
390
   "L" 64 bit floating point constant in .lit8
391
   "f" 32 bit floating point constant
392
   "l" 32 bit floating point constant in .lit4
393

394
   MDMX instruction operands (note that while these use the FP register
395
   fields, they accept both $fN and $vN names for the registers): 
396
   "O"        MDMX alignment offset (OP_*_ALN)
397
   "Q"        MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
398
   "X"        MDMX destination register (OP_*_FD)
399
   "Y"        MDMX source register (OP_*_FS)
400
   "Z"        MDMX source register (OP_*_FT)
401

402
   DSP ASE usage:
403
   "2" 2 bit unsigned immediate for byte align (OP_*_BP)
404
   "3" 3 bit unsigned immediate (OP_*_SA3)
405
   "4" 4 bit unsigned immediate (OP_*_SA4)
406
   "5" 8 bit unsigned immediate (OP_*_IMM8)
407
   "6" 5 bit unsigned immediate (OP_*_RS)
408
   "7" 2 bit dsp accumulator register (OP_*_DSPACC)
409
   "8" 6 bit unsigned immediate (OP_*_WRDSP)
410
   "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
411
   "0" 6 bit signed immediate (OP_*_DSPSFT)
412
   ":" 7 bit signed immediate (OP_*_DSPSFT_7)
413
   "'" 6 bit unsigned immediate (OP_*_RDDSP)
414
   "@" 10 bit signed immediate (OP_*_IMM10)
415

416
   MT ASE usage:
417
   "!" 1 bit usermode flag (OP_*_MT_U)
418
   "$" 1 bit load high flag (OP_*_MT_H)
419
   "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
420
   "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
421
   "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
422
   "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
423
   "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
424

425
   UDI immediates:
426
   "+1" UDI immediate bits 6-10
427
   "+2" UDI immediate bits 6-15
428
   "+3" UDI immediate bits 6-20
429
   "+4" UDI immediate bits 6-25
430

431
   Other:
432
   "()" parens surrounding optional value
433
   ","  separates operands
434
   "[]" brackets around index for vector-op scalar operand specifier (vr5400)
435
   "+"  Start of extension sequence.
436

437
   Characters used so far, for quick reference when adding more:
438
   "234567890"
439
   "%[]<>(),+:'@!$*&"
440
   "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
441
   "abcdefghijklopqrstuvwxz"
442

443
   Extension character sequences used so far ("+" followed by the
444
   following), for quick reference when adding more:
445
   "1234"
446
   "ABCDEFGHIT"
447
   "t"
448
*/
449

    
450
/* These are the bits which may be set in the pinfo field of an
451
   instructions, if it is not equal to INSN_MACRO.  */
452

    
453
/* Modifies the general purpose register in OP_*_RD.  */
454
#define INSN_WRITE_GPR_D            0x00000001
455
/* Modifies the general purpose register in OP_*_RT.  */
456
#define INSN_WRITE_GPR_T            0x00000002
457
/* Modifies general purpose register 31.  */
458
#define INSN_WRITE_GPR_31           0x00000004
459
/* Modifies the floating point register in OP_*_FD.  */
460
#define INSN_WRITE_FPR_D            0x00000008
461
/* Modifies the floating point register in OP_*_FS.  */
462
#define INSN_WRITE_FPR_S            0x00000010
463
/* Modifies the floating point register in OP_*_FT.  */
464
#define INSN_WRITE_FPR_T            0x00000020
465
/* Reads the general purpose register in OP_*_RS.  */
466
#define INSN_READ_GPR_S             0x00000040
467
/* Reads the general purpose register in OP_*_RT.  */
468
#define INSN_READ_GPR_T             0x00000080
469
/* Reads the floating point register in OP_*_FS.  */
470
#define INSN_READ_FPR_S             0x00000100
471
/* Reads the floating point register in OP_*_FT.  */
472
#define INSN_READ_FPR_T             0x00000200
473
/* Reads the floating point register in OP_*_FR.  */
474
#define INSN_READ_FPR_R                    0x00000400
475
/* Modifies coprocessor condition code.  */
476
#define INSN_WRITE_COND_CODE        0x00000800
477
/* Reads coprocessor condition code.  */
478
#define INSN_READ_COND_CODE         0x00001000
479
/* TLB operation.  */
480
#define INSN_TLB                    0x00002000
481
/* Reads coprocessor register other than floating point register.  */
482
#define INSN_COP                    0x00004000
483
/* Instruction loads value from memory, requiring delay.  */
484
#define INSN_LOAD_MEMORY_DELAY      0x00008000
485
/* Instruction loads value from coprocessor, requiring delay.  */
486
#define INSN_LOAD_COPROC_DELAY            0x00010000
487
/* Instruction has unconditional branch delay slot.  */
488
#define INSN_UNCOND_BRANCH_DELAY    0x00020000
489
/* Instruction has conditional branch delay slot.  */
490
#define INSN_COND_BRANCH_DELAY      0x00040000
491
/* Conditional branch likely: if branch not taken, insn nullified.  */
492
#define INSN_COND_BRANCH_LIKELY            0x00080000
493
/* Moves to coprocessor register, requiring delay.  */
494
#define INSN_COPROC_MOVE_DELAY      0x00100000
495
/* Loads coprocessor register from memory, requiring delay.  */
496
#define INSN_COPROC_MEMORY_DELAY    0x00200000
497
/* Reads the HI register.  */
498
#define INSN_READ_HI                    0x00400000
499
/* Reads the LO register.  */
500
#define INSN_READ_LO                    0x00800000
501
/* Modifies the HI register.  */
502
#define INSN_WRITE_HI                    0x01000000
503
/* Modifies the LO register.  */
504
#define INSN_WRITE_LO                    0x02000000
505
/* Takes a trap (easier to keep out of delay slot).  */
506
#define INSN_TRAP                   0x04000000
507
/* Instruction stores value into memory.  */
508
#define INSN_STORE_MEMORY            0x08000000
509
/* Instruction uses single precision floating point.  */
510
#define FP_S                            0x10000000
511
/* Instruction uses double precision floating point.  */
512
#define FP_D                            0x20000000
513
/* Instruction is part of the tx39's integer multiply family.    */
514
#define INSN_MULT                   0x40000000
515
/* Instruction synchronize shared memory.  */
516
#define INSN_SYNC                    0x80000000
517

    
518
/* These are the bits which may be set in the pinfo2 field of an
519
   instruction. */
520

    
521
/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
522
#define        INSN2_ALIAS                    0x00000001
523
/* Instruction reads MDMX accumulator. */
524
#define INSN2_READ_MDMX_ACC            0x00000002
525
/* Instruction writes MDMX accumulator. */
526
#define INSN2_WRITE_MDMX_ACC            0x00000004
527

    
528
/* Instruction is actually a macro.  It should be ignored by the
529
   disassembler, and requires special treatment by the assembler.  */
530
#define INSN_MACRO                  0xffffffff
531

    
532
/* Masks used to mark instructions to indicate which MIPS ISA level
533
   they were introduced in.  ISAs, as defined below, are logical
534
   ORs of these bits, indicating that they support the instructions
535
   defined at the given level.  */
536

    
537
#define INSN_ISA_MASK                  0x00000fff
538
#define INSN_ISA1                 0x00000001
539
#define INSN_ISA2                 0x00000002
540
#define INSN_ISA3                 0x00000004
541
#define INSN_ISA4                 0x00000008
542
#define INSN_ISA5                 0x00000010
543
#define INSN_ISA32                0x00000020
544
#define INSN_ISA64                0x00000040
545
#define INSN_ISA32R2              0x00000080
546
#define INSN_ISA64R2              0x00000100
547

    
548
/* Masks used for MIPS-defined ASEs.  */
549
#define INSN_ASE_MASK                  0x0000f000
550

    
551
/* DSP ASE */
552
#define INSN_DSP                  0x00001000
553
#define INSN_DSP64                0x00002000
554
/* MIPS 16 ASE */
555
#define INSN_MIPS16               0x00004000
556
/* MIPS-3D ASE */
557
#define INSN_MIPS3D               0x00008000
558

    
559
/* Chip specific instructions.  These are bitmasks.  */
560

    
561
/* MIPS R4650 instruction.  */
562
#define INSN_4650                 0x00010000
563
/* LSI R4010 instruction.  */
564
#define INSN_4010                 0x00020000
565
/* NEC VR4100 instruction.  */
566
#define INSN_4100                 0x00040000
567
/* Toshiba R3900 instruction.  */
568
#define INSN_3900                 0x00080000
569
/* MIPS R10000 instruction.  */
570
#define INSN_10000                0x00100000
571
/* Broadcom SB-1 instruction.  */
572
#define INSN_SB1                  0x00200000
573
/* NEC VR4111/VR4181 instruction.  */
574
#define INSN_4111                 0x00400000
575
/* NEC VR4120 instruction.  */
576
#define INSN_4120                 0x00800000
577
/* NEC VR5400 instruction.  */
578
#define INSN_5400                  0x01000000
579
/* NEC VR5500 instruction.  */
580
#define INSN_5500                  0x02000000
581

    
582
/* MDMX ASE */
583
#define INSN_MDMX                 0x04000000
584
/* MT ASE */
585
#define INSN_MT                   0x08000000
586
/* SmartMIPS ASE  */
587
#define INSN_SMARTMIPS            0x10000000
588
/* DSP R2 ASE  */
589
#define INSN_DSPR2                0x20000000
590

    
591
/* MIPS ISA defines, use instead of hardcoding ISA level.  */
592

    
593
#define       ISA_UNKNOWN     0               /* Gas internal use.  */
594
#define       ISA_MIPS1       (INSN_ISA1)
595
#define       ISA_MIPS2       (ISA_MIPS1 | INSN_ISA2)
596
#define       ISA_MIPS3       (ISA_MIPS2 | INSN_ISA3)
597
#define       ISA_MIPS4       (ISA_MIPS3 | INSN_ISA4)
598
#define       ISA_MIPS5       (ISA_MIPS4 | INSN_ISA5)
599

    
600
#define       ISA_MIPS32      (ISA_MIPS2 | INSN_ISA32)
601
#define       ISA_MIPS64      (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
602

    
603
#define       ISA_MIPS32R2    (ISA_MIPS32 | INSN_ISA32R2)
604
#define       ISA_MIPS64R2    (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2)
605

    
606

    
607
/* CPU defines, use instead of hardcoding processor number. Keep this
608
   in sync with bfd/archures.c in order for machine selection to work.  */
609
#define CPU_UNKNOWN        0               /* Gas internal use.  */
610
#define CPU_R3000        3000
611
#define CPU_R3900        3900
612
#define CPU_R4000        4000
613
#define CPU_R4010        4010
614
#define CPU_VR4100        4100
615
#define CPU_R4111        4111
616
#define CPU_VR4120        4120
617
#define CPU_R4300        4300
618
#define CPU_R4400        4400
619
#define CPU_R4600        4600
620
#define CPU_R4650        4650
621
#define CPU_R5000        5000
622
#define CPU_VR5400        5400
623
#define CPU_VR5500        5500
624
#define CPU_R6000        6000
625
#define CPU_RM7000        7000
626
#define CPU_R8000        8000
627
#define CPU_R10000        10000
628
#define CPU_R12000        12000
629
#define CPU_MIPS16        16
630
#define CPU_MIPS32        32
631
#define CPU_MIPS32R2        33
632
#define CPU_MIPS5       5
633
#define CPU_MIPS64      64
634
#define CPU_MIPS64R2        65
635
#define CPU_SB1         12310201        /* octal 'SB', 01.  */
636

    
637
/* Test for membership in an ISA including chip specific ISAs.  INSN
638
   is pointer to an element of the opcode table; ISA is the specified
639
   ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
640
   test, or zero if no CPU specific ISA test is desired.  */
641

    
642
#if 0
643
#define OPCODE_IS_MEMBER(insn, isa, cpu)                                \
644
    (((insn)->membership & isa) != 0                                        \
645
     || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0)        \
646
     || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0)        \
647
     || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0)        \
648
     || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0)        \
649
     || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0)        \
650
     || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)        \
651
     || ((cpu == CPU_R10000 || cpu == CPU_R12000)                        \
652
         && ((insn)->membership & INSN_10000) != 0)                        \
653
     || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0)        \
654
     || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0)        \
655
     || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0)        \
656
     || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0)        \
657
     || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0)        \
658
     || 0)        /* Please keep this term for easier source merging.  */
659
#else
660
#define OPCODE_IS_MEMBER(insn, isa, cpu)                               \
661
    (1 != 0)
662
#endif
663

    
664
/* This is a list of macro expanded instructions.
665

666
   _I appended means immediate
667
   _A appended means address
668
   _AB appended means address with base register
669
   _D appended means 64 bit floating point constant
670
   _S appended means 32 bit floating point constant.  */
671

    
672
enum
673
{
674
  M_ABS,
675
  M_ADD_I,
676
  M_ADDU_I,
677
  M_AND_I,
678
  M_BALIGN,
679
  M_BEQ,
680
  M_BEQ_I,
681
  M_BEQL_I,
682
  M_BGE,
683
  M_BGEL,
684
  M_BGE_I,
685
  M_BGEL_I,
686
  M_BGEU,
687
  M_BGEUL,
688
  M_BGEU_I,
689
  M_BGEUL_I,
690
  M_BGT,
691
  M_BGTL,
692
  M_BGT_I,
693
  M_BGTL_I,
694
  M_BGTU,
695
  M_BGTUL,
696
  M_BGTU_I,
697
  M_BGTUL_I,
698
  M_BLE,
699
  M_BLEL,
700
  M_BLE_I,
701
  M_BLEL_I,
702
  M_BLEU,
703
  M_BLEUL,
704
  M_BLEU_I,
705
  M_BLEUL_I,
706
  M_BLT,
707
  M_BLTL,
708
  M_BLT_I,
709
  M_BLTL_I,
710
  M_BLTU,
711
  M_BLTUL,
712
  M_BLTU_I,
713
  M_BLTUL_I,
714
  M_BNE,
715
  M_BNE_I,
716
  M_BNEL_I,
717
  M_CACHE_AB,
718
  M_DABS,
719
  M_DADD_I,
720
  M_DADDU_I,
721
  M_DDIV_3,
722
  M_DDIV_3I,
723
  M_DDIVU_3,
724
  M_DDIVU_3I,
725
  M_DEXT,
726
  M_DINS,
727
  M_DIV_3,
728
  M_DIV_3I,
729
  M_DIVU_3,
730
  M_DIVU_3I,
731
  M_DLA_AB,
732
  M_DLCA_AB,
733
  M_DLI,
734
  M_DMUL,
735
  M_DMUL_I,
736
  M_DMULO,
737
  M_DMULO_I,
738
  M_DMULOU,
739
  M_DMULOU_I,
740
  M_DREM_3,
741
  M_DREM_3I,
742
  M_DREMU_3,
743
  M_DREMU_3I,
744
  M_DSUB_I,
745
  M_DSUBU_I,
746
  M_DSUBU_I_2,
747
  M_J_A,
748
  M_JAL_1,
749
  M_JAL_2,
750
  M_JAL_A,
751
  M_L_DOB,
752
  M_L_DAB,
753
  M_LA_AB,
754
  M_LB_A,
755
  M_LB_AB,
756
  M_LBU_A,
757
  M_LBU_AB,
758
  M_LCA_AB,
759
  M_LD_A,
760
  M_LD_OB,
761
  M_LD_AB,
762
  M_LDC1_AB,
763
  M_LDC2_AB,
764
  M_LDC3_AB,
765
  M_LDL_AB,
766
  M_LDR_AB,
767
  M_LH_A,
768
  M_LH_AB,
769
  M_LHU_A,
770
  M_LHU_AB,
771
  M_LI,
772
  M_LI_D,
773
  M_LI_DD,
774
  M_LI_S,
775
  M_LI_SS,
776
  M_LL_AB,
777
  M_LLD_AB,
778
  M_LS_A,
779
  M_LW_A,
780
  M_LW_AB,
781
  M_LWC0_A,
782
  M_LWC0_AB,
783
  M_LWC1_A,
784
  M_LWC1_AB,
785
  M_LWC2_A,
786
  M_LWC2_AB,
787
  M_LWC3_A,
788
  M_LWC3_AB,
789
  M_LWL_A,
790
  M_LWL_AB,
791
  M_LWR_A,
792
  M_LWR_AB,
793
  M_LWU_AB,
794
  M_MOVE,
795
  M_MUL,
796
  M_MUL_I,
797
  M_MULO,
798
  M_MULO_I,
799
  M_MULOU,
800
  M_MULOU_I,
801
  M_NOR_I,
802
  M_OR_I,
803
  M_REM_3,
804
  M_REM_3I,
805
  M_REMU_3,
806
  M_REMU_3I,
807
  M_DROL,
808
  M_ROL,
809
  M_DROL_I,
810
  M_ROL_I,
811
  M_DROR,
812
  M_ROR,
813
  M_DROR_I,
814
  M_ROR_I,
815
  M_S_DA,
816
  M_S_DOB,
817
  M_S_DAB,
818
  M_S_S,
819
  M_SC_AB,
820
  M_SCD_AB,
821
  M_SD_A,
822
  M_SD_OB,
823
  M_SD_AB,
824
  M_SDC1_AB,
825
  M_SDC2_AB,
826
  M_SDC3_AB,
827
  M_SDL_AB,
828
  M_SDR_AB,
829
  M_SEQ,
830
  M_SEQ_I,
831
  M_SGE,
832
  M_SGE_I,
833
  M_SGEU,
834
  M_SGEU_I,
835
  M_SGT,
836
  M_SGT_I,
837
  M_SGTU,
838
  M_SGTU_I,
839
  M_SLE,
840
  M_SLE_I,
841
  M_SLEU,
842
  M_SLEU_I,
843
  M_SLT_I,
844
  M_SLTU_I,
845
  M_SNE,
846
  M_SNE_I,
847
  M_SB_A,
848
  M_SB_AB,
849
  M_SH_A,
850
  M_SH_AB,
851
  M_SW_A,
852
  M_SW_AB,
853
  M_SWC0_A,
854
  M_SWC0_AB,
855
  M_SWC1_A,
856
  M_SWC1_AB,
857
  M_SWC2_A,
858
  M_SWC2_AB,
859
  M_SWC3_A,
860
  M_SWC3_AB,
861
  M_SWL_A,
862
  M_SWL_AB,
863
  M_SWR_A,
864
  M_SWR_AB,
865
  M_SUB_I,
866
  M_SUBU_I,
867
  M_SUBU_I_2,
868
  M_TEQ_I,
869
  M_TGE_I,
870
  M_TGEU_I,
871
  M_TLT_I,
872
  M_TLTU_I,
873
  M_TNE_I,
874
  M_TRUNCWD,
875
  M_TRUNCWS,
876
  M_ULD,
877
  M_ULD_A,
878
  M_ULH,
879
  M_ULH_A,
880
  M_ULHU,
881
  M_ULHU_A,
882
  M_ULW,
883
  M_ULW_A,
884
  M_USH,
885
  M_USH_A,
886
  M_USW,
887
  M_USW_A,
888
  M_USD,
889
  M_USD_A,
890
  M_XOR_I,
891
  M_COP0,
892
  M_COP1,
893
  M_COP2,
894
  M_COP3,
895
  M_NUM_MACROS
896
};
897

    
898

    
899
/* The order of overloaded instructions matters.  Label arguments and
900
   register arguments look the same. Instructions that can have either
901
   for arguments must apear in the correct order in this table for the
902
   assembler to pick the right one. In other words, entries with
903
   immediate operands must apear after the same instruction with
904
   registers.
905

906
   Many instructions are short hand for other instructions (i.e., The
907
   jal <register> instruction is short for jalr <register>).  */
908

    
909
extern const struct mips_opcode mips_builtin_opcodes[];
910
extern const int bfd_mips_num_builtin_opcodes;
911
extern struct mips_opcode *mips_opcodes;
912
extern int bfd_mips_num_opcodes;
913
#define NUMOPCODES bfd_mips_num_opcodes
914

    
915
 
916
/* The rest of this file adds definitions for the mips16 TinyRISC
917
   processor.  */
918

    
919
/* These are the bitmasks and shift counts used for the different
920
   fields in the instruction formats.  Other than OP, no masks are
921
   provided for the fixed portions of an instruction, since they are
922
   not needed.
923

924
   The I format uses IMM11.
925

926
   The RI format uses RX and IMM8.
927

928
   The RR format uses RX, and RY.
929

930
   The RRI format uses RX, RY, and IMM5.
931

932
   The RRR format uses RX, RY, and RZ.
933

934
   The RRI_A format uses RX, RY, and IMM4.
935

936
   The SHIFT format uses RX, RY, and SHAMT.
937

938
   The I8 format uses IMM8.
939

940
   The I8_MOVR32 format uses RY and REGR32.
941

942
   The IR_MOV32R format uses REG32R and MOV32Z.
943

944
   The I64 format uses IMM8.
945

946
   The RI64 format uses RY and IMM5.
947
   */
948

    
949
#define MIPS16OP_MASK_OP        0x1f
950
#define MIPS16OP_SH_OP                11
951
#define MIPS16OP_MASK_IMM11        0x7ff
952
#define MIPS16OP_SH_IMM11        0
953
#define MIPS16OP_MASK_RX        0x7
954
#define MIPS16OP_SH_RX                8
955
#define MIPS16OP_MASK_IMM8        0xff
956
#define MIPS16OP_SH_IMM8        0
957
#define MIPS16OP_MASK_RY        0x7
958
#define MIPS16OP_SH_RY                5
959
#define MIPS16OP_MASK_IMM5        0x1f
960
#define MIPS16OP_SH_IMM5        0
961
#define MIPS16OP_MASK_RZ        0x7
962
#define MIPS16OP_SH_RZ                2
963
#define MIPS16OP_MASK_IMM4        0xf
964
#define MIPS16OP_SH_IMM4        0
965
#define MIPS16OP_MASK_REGR32        0x1f
966
#define MIPS16OP_SH_REGR32        0
967
#define MIPS16OP_MASK_REG32R        0x1f
968
#define MIPS16OP_SH_REG32R        3
969
#define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
970
#define MIPS16OP_MASK_MOVE32Z        0x7
971
#define MIPS16OP_SH_MOVE32Z        0
972
#define MIPS16OP_MASK_IMM6        0x3f
973
#define MIPS16OP_SH_IMM6        5
974

    
975
/* These are the characters which may appears in the args field of an
976
   instruction.  They appear in the order in which the fields appear
977
   when the instruction is used.  Commas and parentheses in the args
978
   string are ignored when assembling, and written into the output
979
   when disassembling.
980

981
   "y" 3 bit register (MIPS16OP_*_RY)
982
   "x" 3 bit register (MIPS16OP_*_RX)
983
   "z" 3 bit register (MIPS16OP_*_RZ)
984
   "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
985
   "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
986
   "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
987
   "0" zero register ($0)
988
   "S" stack pointer ($sp or $29)
989
   "P" program counter
990
   "R" return address register ($ra or $31)
991
   "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
992
   "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
993
   "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
994
   "a" 26 bit jump address
995
   "e" 11 bit extension value
996
   "l" register list for entry instruction
997
   "L" register list for exit instruction
998

999
   The remaining codes may be extended.  Except as otherwise noted,
1000
   the full extended operand is a 16 bit signed value.
1001
   "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
1002
   ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
1003
   "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
1004
   "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
1005
   "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
1006
   "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
1007
   "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
1008
   "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
1009
   "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
1010
   "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
1011
   "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
1012
   "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
1013
   "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
1014
   "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
1015
   "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
1016
   "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
1017
   "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
1018
   "q" 11 bit branch address (MIPS16OP_*_IMM11)
1019
   "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
1020
   "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
1021
   "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
1022
   */
1023

    
1024
/* Save/restore encoding for the args field when all 4 registers are
1025
   either saved as arguments or saved/restored as statics.  */
1026
#define MIPS16_ALL_ARGS    0xe
1027
#define MIPS16_ALL_STATICS 0xb
1028

    
1029
/* For the mips16, we use the same opcode table format and a few of
1030
   the same flags.  However, most of the flags are different.  */
1031

    
1032
/* Modifies the register in MIPS16OP_*_RX.  */
1033
#define MIPS16_INSN_WRITE_X                    0x00000001
1034
/* Modifies the register in MIPS16OP_*_RY.  */
1035
#define MIPS16_INSN_WRITE_Y                    0x00000002
1036
/* Modifies the register in MIPS16OP_*_RZ.  */
1037
#define MIPS16_INSN_WRITE_Z                    0x00000004
1038
/* Modifies the T ($24) register.  */
1039
#define MIPS16_INSN_WRITE_T                    0x00000008
1040
/* Modifies the SP ($29) register.  */
1041
#define MIPS16_INSN_WRITE_SP                    0x00000010
1042
/* Modifies the RA ($31) register.  */
1043
#define MIPS16_INSN_WRITE_31                    0x00000020
1044
/* Modifies the general purpose register in MIPS16OP_*_REG32R.  */
1045
#define MIPS16_INSN_WRITE_GPR_Y                    0x00000040
1046
/* Reads the register in MIPS16OP_*_RX.  */
1047
#define MIPS16_INSN_READ_X                    0x00000080
1048
/* Reads the register in MIPS16OP_*_RY.  */
1049
#define MIPS16_INSN_READ_Y                    0x00000100
1050
/* Reads the register in MIPS16OP_*_MOVE32Z.  */
1051
#define MIPS16_INSN_READ_Z                    0x00000200
1052
/* Reads the T ($24) register.  */
1053
#define MIPS16_INSN_READ_T                    0x00000400
1054
/* Reads the SP ($29) register.  */
1055
#define MIPS16_INSN_READ_SP                    0x00000800
1056
/* Reads the RA ($31) register.  */
1057
#define MIPS16_INSN_READ_31                    0x00001000
1058
/* Reads the program counter.  */
1059
#define MIPS16_INSN_READ_PC                    0x00002000
1060
/* Reads the general purpose register in MIPS16OP_*_REGR32.  */
1061
#define MIPS16_INSN_READ_GPR_X                    0x00004000
1062
/* Is a branch insn. */
1063
#define MIPS16_INSN_BRANCH                  0x00010000
1064

    
1065
/* The following flags have the same value for the mips16 opcode
1066
   table:
1067
   INSN_UNCOND_BRANCH_DELAY
1068
   INSN_COND_BRANCH_DELAY
1069
   INSN_COND_BRANCH_LIKELY (never used)
1070
   INSN_READ_HI
1071
   INSN_READ_LO
1072
   INSN_WRITE_HI
1073
   INSN_WRITE_LO
1074
   INSN_TRAP
1075
   INSN_ISA3
1076
   */
1077

    
1078
extern const struct mips_opcode mips16_opcodes[];
1079
extern const int bfd_mips16_num_opcodes;
1080

    
1081
/* Short hand so the lines aren't too long.  */
1082

    
1083
#define LDD     INSN_LOAD_MEMORY_DELAY
1084
#define LCD        INSN_LOAD_COPROC_DELAY
1085
#define UBD     INSN_UNCOND_BRANCH_DELAY
1086
#define CBD        INSN_COND_BRANCH_DELAY
1087
#define COD     INSN_COPROC_MOVE_DELAY
1088
#define CLD        INSN_COPROC_MEMORY_DELAY
1089
#define CBL        INSN_COND_BRANCH_LIKELY
1090
#define TRAP        INSN_TRAP
1091
#define SM        INSN_STORE_MEMORY
1092

    
1093
#define WR_d    INSN_WRITE_GPR_D
1094
#define WR_t    INSN_WRITE_GPR_T
1095
#define WR_31   INSN_WRITE_GPR_31
1096
#define WR_D    INSN_WRITE_FPR_D
1097
#define WR_T        INSN_WRITE_FPR_T
1098
#define WR_S        INSN_WRITE_FPR_S
1099
#define RD_s    INSN_READ_GPR_S
1100
#define RD_b    INSN_READ_GPR_S
1101
#define RD_t    INSN_READ_GPR_T
1102
#define RD_S    INSN_READ_FPR_S
1103
#define RD_T    INSN_READ_FPR_T
1104
#define RD_R        INSN_READ_FPR_R
1105
#define WR_CC        INSN_WRITE_COND_CODE
1106
#define RD_CC        INSN_READ_COND_CODE
1107
#define RD_C0   INSN_COP
1108
#define RD_C1        INSN_COP
1109
#define RD_C2   INSN_COP
1110
#define RD_C3   INSN_COP
1111
#define WR_C0   INSN_COP
1112
#define WR_C1        INSN_COP
1113
#define WR_C2   INSN_COP
1114
#define WR_C3   INSN_COP
1115

    
1116
#define WR_HI        INSN_WRITE_HI
1117
#define RD_HI        INSN_READ_HI
1118
#define MOD_HI  WR_HI|RD_HI
1119

    
1120
#define WR_LO        INSN_WRITE_LO
1121
#define RD_LO        INSN_READ_LO
1122
#define MOD_LO  WR_LO|RD_LO
1123

    
1124
#define WR_HILO WR_HI|WR_LO
1125
#define RD_HILO RD_HI|RD_LO
1126
#define MOD_HILO WR_HILO|RD_HILO
1127

    
1128
#define IS_M    INSN_MULT
1129

    
1130
#define WR_MACC INSN2_WRITE_MDMX_ACC
1131
#define RD_MACC INSN2_READ_MDMX_ACC
1132

    
1133
#define I1        INSN_ISA1
1134
#define I2        INSN_ISA2
1135
#define I3        INSN_ISA3
1136
#define I4        INSN_ISA4
1137
#define I5        INSN_ISA5
1138
#define I32        INSN_ISA32
1139
#define I64     INSN_ISA64
1140
#define I33        INSN_ISA32R2
1141
#define I65        INSN_ISA64R2
1142

    
1143
/* MIPS64 MIPS-3D ASE support.  */
1144
#define I16     INSN_MIPS16
1145

    
1146
/* MIPS32 SmartMIPS ASE support.  */
1147
#define SMT        INSN_SMARTMIPS
1148

    
1149
/* MIPS64 MIPS-3D ASE support.  */
1150
#define M3D     INSN_MIPS3D
1151

    
1152
/* MIPS64 MDMX ASE support.  */
1153
#define MX      INSN_MDMX
1154

    
1155
#define P3        INSN_4650
1156
#define L1        INSN_4010
1157
#define V1        (INSN_4100 | INSN_4111 | INSN_4120)
1158
#define T3      INSN_3900
1159
#define M1        INSN_10000
1160
#define SB1     INSN_SB1
1161
#define N411        INSN_4111
1162
#define N412        INSN_4120
1163
#define N5        (INSN_5400 | INSN_5500)
1164
#define N54        INSN_5400
1165
#define N55        INSN_5500
1166

    
1167
#define G1      (T3             \
1168
                 )
1169

    
1170
#define G2      (T3             \
1171
                 )
1172

    
1173
#define G3      (I4             \
1174
                 )
1175

    
1176
/* MIPS DSP ASE support.
1177
   NOTE:
1178
   1. MIPS DSP ASE includes 4 accumulators ($ac0 - $ac3).  $ac0 is the pair
1179
   of original HI and LO.  $ac1, $ac2 and $ac3 are new registers, and have
1180
   the same structure as $ac0 (HI + LO).  For DSP instructions that write or
1181
   read accumulators (that may be $ac0), we add WR_a (WR_HILO) or RD_a
1182
   (RD_HILO) attributes, such that HILO dependencies are maintained
1183
   conservatively.
1184

1185
   2. For some mul. instructions that use integer registers as destinations
1186
   but destroy HI+LO as side-effect, we add WR_HILO to their attributes.
1187

1188
   3. MIPS DSP ASE includes a new DSP control register, which has 6 fields
1189
   (ccond, outflag, EFI, c, scount, pos).  Many DSP instructions read or write
1190
   certain fields of the DSP control register.  For simplicity, we decide not
1191
   to track dependencies of these fields.
1192
   However, "bposge32" is a branch instruction that depends on the "pos"
1193
   field.  In order to make sure that GAS does not reorder DSP instructions
1194
   that writes the "pos" field and "bposge32", we add DSP_VOLA (INSN_TRAP)
1195
   attribute to those instructions that write the "pos" field.  */
1196

    
1197
#define WR_a        WR_HILO        /* Write dsp accumulators (reuse WR_HILO)  */
1198
#define RD_a        RD_HILO        /* Read dsp accumulators (reuse RD_HILO)  */
1199
#define MOD_a        WR_a|RD_a
1200
#define DSP_VOLA        INSN_TRAP
1201
#define D32        INSN_DSP
1202
#define D33        INSN_DSPR2
1203
#define D64        INSN_DSP64
1204

    
1205
/* MIPS MT ASE support.  */
1206
#define MT32        INSN_MT
1207

    
1208
/* The order of overloaded instructions matters.  Label arguments and
1209
   register arguments look the same. Instructions that can have either
1210
   for arguments must apear in the correct order in this table for the
1211
   assembler to pick the right one. In other words, entries with
1212
   immediate operands must apear after the same instruction with
1213
   registers.
1214

1215
   Because of the lookup algorithm used, entries with the same opcode
1216
   name must be contiguous.
1217

1218
   Many instructions are short hand for other instructions (i.e., The
1219
   jal <register> instruction is short for jalr <register>).  */
1220

    
1221
const struct mips_opcode mips_builtin_opcodes[] =
1222
{
1223
/* These instructions appear first so that the disassembler will find
1224
   them first.  The assemblers uses a hash table based on the
1225
   instruction name anyhow.  */
1226
/* name,    args,        match,            mask,        pinfo,                  membership */
1227
{"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,                   0,                I4|I32|G3        },
1228
{"prefx",   "h,t(b)",        0x4c00000f, 0xfc0007ff, RD_b|RD_t,                0,                I4|I33        },
1229
{"nop",     "",         0x00000000, 0xffffffff, 0,                      INSN2_ALIAS,        I1      }, /* sll */
1230
{"ssnop",   "",         0x00000040, 0xffffffff, 0,                      INSN2_ALIAS,        I32|N55        }, /* sll */
1231
{"ehb",     "",         0x000000c0, 0xffffffff, 0,                      INSN2_ALIAS,        I33        }, /* sll */
1232
{"li",      "t,j",      0x24000000, 0xffe00000, WR_t,                        INSN2_ALIAS,        I1        }, /* addiu */
1233
{"li",            "t,i",        0x34000000, 0xffe00000, WR_t,                        INSN2_ALIAS,        I1        }, /* ori */
1234
{"li",      "t,I",        0,    (int) M_LI,        INSN_MACRO,                0,                I1        },
1235
{"move",    "d,s",        0,    (int) M_MOVE,        INSN_MACRO,                0,                I1        },
1236
{"move",    "d,s",        0x0000002d, 0xfc1f07ff, WR_d|RD_s,                INSN2_ALIAS,        I3        },/* daddu */
1237
{"move",    "d,s",        0x00000021, 0xfc1f07ff, WR_d|RD_s,                INSN2_ALIAS,        I1        },/* addu */
1238
{"move",    "d,s",        0x00000025, 0xfc1f07ff,        WR_d|RD_s,                INSN2_ALIAS,        I1        },/* or */
1239
{"b",       "p",        0x10000000, 0xffff0000,        UBD,                        INSN2_ALIAS,        I1        },/* beq 0,0 */
1240
{"b",       "p",        0x04010000, 0xffff0000,        UBD,                        INSN2_ALIAS,        I1        },/* bgez 0 */
1241
{"bal",     "p",        0x04110000, 0xffff0000,        UBD|WR_31,                INSN2_ALIAS,        I1        },/* bgezal 0*/
1242

    
1243
{"abs",     "d,v",        0,    (int) M_ABS,        INSN_MACRO,                0,                I1        },
1244
{"abs.s",   "D,V",        0x46000005, 0xffff003f,        WR_D|RD_S|FP_S,                0,                I1        },
1245
{"abs.d",   "D,V",        0x46200005, 0xffff003f,        WR_D|RD_S|FP_D,                0,                I1        },
1246
{"abs.ps",  "D,V",        0x46c00005, 0xffff003f,        WR_D|RD_S|FP_D,                0,                I5|I33        },
1247
{"add",     "d,v,t",        0x00000020, 0xfc0007ff,        WR_d|RD_s|RD_t,                0,                I1        },
1248
{"add",     "t,r,I",        0,    (int) M_ADD_I,        INSN_MACRO,                0,                I1        },
1249
{"add.s",   "D,V,T",        0x46000000, 0xffe0003f,        WR_D|RD_S|RD_T|FP_S,        0,                I1        },
1250
{"add.d",   "D,V,T",        0x46200000, 0xffe0003f,        WR_D|RD_S|RD_T|FP_D,        0,                I1        },
1251
{"add.ob",  "X,Y,Q",        0x7800000b, 0xfc20003f,        WR_D|RD_S|RD_T|FP_D,        0,                MX|SB1        },
1252
{"add.ob",  "D,S,T",        0x4ac0000b, 0xffe0003f,        WR_D|RD_S|RD_T,                0,                N54        },
1253
{"add.ob",  "D,S,T[e]",        0x4800000b, 0xfe20003f,        WR_D|RD_S|RD_T,                0,                N54        },
1254
{"add.ob",  "D,S,k",        0x4bc0000b, 0xffe0003f,        WR_D|RD_S|RD_T,                0,                N54        },
1255
{"add.ps",  "D,V,T",        0x46c00000, 0xffe0003f,        WR_D|RD_S|RD_T|FP_D,        0,                I5|I33        },
1256
{"add.qh",  "X,Y,Q",        0x7820000b, 0xfc20003f,        WR_D|RD_S|RD_T|FP_D,        0,                MX        },
1257
{"adda.ob", "Y,Q",        0x78000037, 0xfc2007ff,        RD_S|RD_T|FP_D,                WR_MACC,        MX|SB1        },
1258
{"adda.qh", "Y,Q",        0x78200037, 0xfc2007ff,        RD_S|RD_T|FP_D,                WR_MACC,        MX        },
1259
{"addi",    "t,r,j",        0x20000000, 0xfc000000,        WR_t|RD_s,                0,                I1        },
1260
{"addiu",   "t,r,j",        0x24000000, 0xfc000000,        WR_t|RD_s,                0,                I1        },
1261
{"addl.ob", "Y,Q",        0x78000437, 0xfc2007ff,        RD_S|RD_T|FP_D,                WR_MACC,        MX|SB1        },
1262
{"addl.qh", "Y,Q",        0x78200437, 0xfc2007ff,        RD_S|RD_T|FP_D,                WR_MACC,        MX        },
1263
{"addr.ps", "D,S,T",        0x46c00018, 0xffe0003f,        WR_D|RD_S|RD_T|FP_D,        0,                M3D        },
1264
{"addu",    "d,v,t",        0x00000021, 0xfc0007ff,        WR_d|RD_s|RD_t,                0,                I1        },
1265
{"addu",    "t,r,I",        0,    (int) M_ADDU_I,        INSN_MACRO,                0,                I1        },
1266
{"alni.ob", "X,Y,Z,O",        0x78000018, 0xff00003f,        WR_D|RD_S|RD_T|FP_D,        0,                MX|SB1        },
1267
{"alni.ob", "D,S,T,%",        0x48000018, 0xff00003f,        WR_D|RD_S|RD_T,         0,                N54        },
1268
{"alni.qh", "X,Y,Z,O",        0x7800001a, 0xff00003f,        WR_D|RD_S|RD_T|FP_D,        0,                MX        },
1269
{"alnv.ps", "D,V,T,s",        0x4c00001e, 0xfc00003f,        WR_D|RD_S|RD_T|FP_D,        0,                I5|I33        },
1270
{"alnv.ob", "X,Y,Z,s",        0x78000019, 0xfc00003f,        WR_D|RD_S|RD_T|RD_s|FP_D, 0,                MX|SB1        },
1271
{"alnv.qh", "X,Y,Z,s",        0x7800001b, 0xfc00003f,        WR_D|RD_S|RD_T|RD_s|FP_D, 0,                MX        },
1272
{"and",     "d,v,t",        0x00000024, 0xfc0007ff,        WR_d|RD_s|RD_t,                0,                I1        },
1273
{"and",     "t,r,I",        0,    (int) M_AND_I,        INSN_MACRO,                0,                I1        },
1274
{"and.ob",  "X,Y,Q",        0x7800000c, 0xfc20003f,        WR_D|RD_S|RD_T|FP_D,        0,                MX|SB1        },
1275
{"and.ob",  "D,S,T",        0x4ac0000c, 0xffe0003f,        WR_D|RD_S|RD_T,                0,                N54        },
1276
{"and.ob",  "D,S,T[e]",        0x4800000c, 0xfe20003f,        WR_D|RD_S|RD_T,                0,                N54        },
1277
{"and.ob",  "D,S,k",        0x4bc0000c, 0xffe0003f,        WR_D|RD_S|RD_T,                0,                N54        },
1278
{"and.qh",  "X,Y,Q",        0x7820000c, 0xfc20003f,        WR_D|RD_S|RD_T|FP_D,        0,                MX        },
1279
{"andi",    "t,r,i",        0x30000000, 0xfc000000,        WR_t|RD_s,                0,                I1        },
1280
/* b is at the top of the table.  */
1281
/* bal is at the top of the table.  */
1282
/* bc0[tf]l? are at the bottom of the table.  */
1283
{"bc1any2f", "N,p",        0x45200000, 0xffe30000,        CBD|RD_CC|FP_S,                0,                M3D        },
1284
{"bc1any2t", "N,p",        0x45210000, 0xffe30000,        CBD|RD_CC|FP_S,                0,                M3D        },
1285
{"bc1any4f", "N,p",        0x45400000, 0xffe30000,        CBD|RD_CC|FP_S,                0,                M3D        },
1286
{"bc1any4t", "N,p",        0x45410000, 0xffe30000,        CBD|RD_CC|FP_S,                0,                M3D        },
1287
{"bc1f",    "p",        0x45000000, 0xffff0000,        CBD|RD_CC|FP_S,                0,                I1        },
1288
{"bc1f",    "N,p",      0x45000000, 0xffe30000, CBD|RD_CC|FP_S,         0,                I4|I32        },
1289
{"bc1fl",   "p",        0x45020000, 0xffff0000,        CBL|RD_CC|FP_S,                0,                I2|T3        },
1290
{"bc1fl",   "N,p",      0x45020000, 0xffe30000, CBL|RD_CC|FP_S,         0,                I4|I32        },
1291
{"bc1t",    "p",        0x45010000, 0xffff0000,        CBD|RD_CC|FP_S,                0,                I1        },
1292
{"bc1t",    "N,p",      0x45010000, 0xffe30000, CBD|RD_CC|FP_S,         0,                I4|I32        },
1293
{"bc1tl",   "p",        0x45030000, 0xffff0000,        CBL|RD_CC|FP_S,                0,                I2|T3        },
1294
{"bc1tl",   "N,p",      0x45030000, 0xffe30000, CBL|RD_CC|FP_S,         0,                I4|I32        },
1295
/* bc2* are at the bottom of the table.  */
1296
/* bc3* are at the bottom of the table.  */
1297
{"beqz",    "s,p",        0x10000000, 0xfc1f0000,        CBD|RD_s,                0,                I1        },
1298
{"beqzl",   "s,p",        0x50000000, 0xfc1f0000,        CBL|RD_s,                0,                I2|T3        },
1299
{"beq",     "s,t,p",        0x10000000, 0xfc000000,        CBD|RD_s|RD_t,                0,                I1        },
1300
{"beq",     "s,I,p",        0,    (int) M_BEQ_I,        INSN_MACRO,                0,                I1        },
1301
{"beql",    "s,t,p",        0x50000000, 0xfc000000,        CBL|RD_s|RD_t,                0,                I2|T3        },
1302
{"beql",    "s,I,p",        0,    (int) M_BEQL_I,        INSN_MACRO,                0,                I2|T3        },
1303
{"bge",     "s,t,p",        0,    (int) M_BGE,        INSN_MACRO,                0,                I1        },
1304
{"bge",     "s,I,p",        0,    (int) M_BGE_I,        INSN_MACRO,                0,                I1        },
1305
{"bgel",    "s,t,p",        0,    (int) M_BGEL,        INSN_MACRO,                0,                I2|T3        },
1306
{"bgel",    "s,I,p",        0,    (int) M_BGEL_I,        INSN_MACRO,                0,                I2|T3        },
1307
{"bgeu",    "s,t,p",        0,    (int) M_BGEU,        INSN_MACRO,                0,                I1        },
1308
{"bgeu",    "s,I,p",        0,    (int) M_BGEU_I,        INSN_MACRO,                0,                I1        },
1309
{"bgeul",   "s,t,p",        0,    (int) M_BGEUL,        INSN_MACRO,                0,                I2|T3        },
1310
{"bgeul",   "s,I,p",        0,    (int) M_BGEUL_I,        INSN_MACRO,                0,                I2|T3        },
1311
{"bgez",    "s,p",        0x04010000, 0xfc1f0000,        CBD|RD_s,                0,                I1        },
1312
{"bgezl",   "s,p",        0x04030000, 0xfc1f0000,        CBL|RD_s,                0,                I2|T3        },
1313
{"bgezal",  "s,p",        0x04110000, 0xfc1f0000,        CBD|RD_s|WR_31,                0,                I1        },
1314
{"bgezall", "s,p",        0x04130000, 0xfc1f0000,        CBL|RD_s|WR_31,                0,                I2|T3        },
1315
{"bgt",     "s,t,p",        0,    (int) M_BGT,        INSN_MACRO,                0,                I1        },
1316
{"bgt",     "s,I,p",        0,    (int) M_BGT_I,        INSN_MACRO,                0,                I1        },
1317
{"bgtl",    "s,t,p",        0,    (int) M_BGTL,        INSN_MACRO,                0,                I2|T3        },
1318
{"bgtl",    "s,I,p",        0,    (int) M_BGTL_I,        INSN_MACRO,                0,                I2|T3        },
1319
{"bgtu",    "s,t,p",        0,    (int) M_BGTU,        INSN_MACRO,                0,                I1        },
1320
{"bgtu",    "s,I,p",        0,    (int) M_BGTU_I,        INSN_MACRO,                0,                I1        },
1321
{"bgtul",   "s,t,p",        0,    (int) M_BGTUL,        INSN_MACRO,                0,                I2|T3        },
1322
{"bgtul",   "s,I,p",        0,    (int) M_BGTUL_I,        INSN_MACRO,                0,                I2|T3        },
1323
{"bgtz",    "s,p",        0x1c000000, 0xfc1f0000,        CBD|RD_s,                0,                I1        },
1324
{"bgtzl",   "s,p",        0x5c000000, 0xfc1f0000,        CBL|RD_s,                0,                I2|T3        },
1325
{"ble",     "s,t,p",        0,    (int) M_BLE,        INSN_MACRO,                0,                I1        },
1326
{"ble",     "s,I,p",        0,    (int) M_BLE_I,        INSN_MACRO,                0,                I1        },
1327
{"blel",    "s,t,p",        0,    (int) M_BLEL,        INSN_MACRO,                0,                I2|T3        },
1328
{"blel",    "s,I,p",        0,    (int) M_BLEL_I,        INSN_MACRO,                0,                I2|T3        },
1329
{"bleu",    "s,t,p",        0,    (int) M_BLEU,        INSN_MACRO,                0,                I1        },
1330
{"bleu",    "s,I,p",        0,    (int) M_BLEU_I,        INSN_MACRO,                0,                I1        },
1331
{"bleul",   "s,t,p",        0,    (int) M_BLEUL,        INSN_MACRO,                0,                I2|T3        },
1332
{"bleul",   "s,I,p",        0,    (int) M_BLEUL_I,        INSN_MACRO,                0,                I2|T3        },
1333
{"blez",    "s,p",        0x18000000, 0xfc1f0000,        CBD|RD_s,                0,                I1        },
1334
{"blezl",   "s,p",        0x58000000, 0xfc1f0000,        CBL|RD_s,                0,                I2|T3        },
1335
{"blt",     "s,t,p",        0,    (int) M_BLT,        INSN_MACRO,                0,                I1        },
1336
{"blt",     "s,I,p",        0,    (int) M_BLT_I,        INSN_MACRO,                0,                I1        },
1337
{"bltl",    "s,t,p",        0,    (int) M_BLTL,        INSN_MACRO,                0,                I2|T3        },
1338
{"bltl",    "s,I,p",        0,    (int) M_BLTL_I,        INSN_MACRO,                0,                I2|T3        },
1339
{"bltu",    "s,t,p",        0,    (int) M_BLTU,        INSN_MACRO,                0,                I1        },
1340
{"bltu",    "s,I,p",        0,    (int) M_BLTU_I,        INSN_MACRO,                0,                I1        },
1341
{"bltul",   "s,t,p",        0,    (int) M_BLTUL,        INSN_MACRO,                0,                I2|T3        },
1342
{"bltul",   "s,I,p",        0,    (int) M_BLTUL_I,        INSN_MACRO,                0,                I2|T3        },
1343
{"bltz",    "s,p",        0x04000000, 0xfc1f0000,        CBD|RD_s,                0,                I1        },
1344
{"bltzl",   "s,p",        0x04020000, 0xfc1f0000,        CBL|RD_s,                0,                I2|T3        },
1345
{"bltzal",  "s,p",        0x04100000, 0xfc1f0000,        CBD|RD_s|WR_31,                0,                I1        },
1346
{"bltzall", "s,p",        0x04120000, 0xfc1f0000,        CBL|RD_s|WR_31,                0,                I2|T3        },
1347
{"bnez",    "s,p",        0x14000000, 0xfc1f0000,        CBD|RD_s,                0,                I1        },
1348
{"bnezl",   "s,p",        0x54000000, 0xfc1f0000,        CBL|RD_s,                0,                I2|T3        },
1349
{"bne",     "s,t,p",        0x14000000, 0xfc000000,        CBD|RD_s|RD_t,                0,                I1        },
1350
{"bne",     "s,I,p",        0,    (int) M_BNE_I,        INSN_MACRO,                0,                I1        },
1351
{"bnel",    "s,t,p",        0x54000000, 0xfc000000,        CBL|RD_s|RD_t,                 0,                I2|T3        },
1352
{"bnel",    "s,I,p",        0,    (int) M_BNEL_I,        INSN_MACRO,                0,                I2|T3        },
1353
{"break",   "",                0x0000000d, 0xffffffff,        TRAP,                        0,                I1        },
1354
{"break",   "c",        0x0000000d, 0xfc00ffff,        TRAP,                        0,                I1        },
1355
{"break",   "c,q",        0x0000000d, 0xfc00003f,        TRAP,                        0,                I1        },
1356
{"c.f.d",   "S,T",        0x46200030, 0xffe007ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I1        },
1357
{"c.f.d",   "M,S,T",    0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,                I4|I32        },
1358
{"c.f.s",   "S,T",      0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,                I1      },
1359
{"c.f.s",   "M,S,T",    0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,                I4|I32        },
1360
{"c.f.ps",  "S,T",        0x46c00030, 0xffe007ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I5|I33        },
1361
{"c.f.ps",  "M,S,T",        0x46c00030, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I5|I33        },
1362
{"c.un.d",  "S,T",        0x46200031, 0xffe007ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I1        },
1363
{"c.un.d",  "M,S,T",    0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,                I4|I32        },
1364
{"c.un.s",  "S,T",      0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,                I1      },
1365
{"c.un.s",  "M,S,T",    0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,                I4|I32        },
1366
{"c.un.ps", "S,T",        0x46c00031, 0xffe007ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I5|I33        },
1367
{"c.un.ps", "M,S,T",        0x46c00031, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I5|I33        },
1368
{"c.eq.d",  "S,T",        0x46200032, 0xffe007ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I1        },
1369
{"c.eq.d",  "M,S,T",    0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,                I4|I32        },
1370
{"c.eq.s",  "S,T",      0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,                I1      },
1371
{"c.eq.s",  "M,S,T",    0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,                I4|I32        },
1372
{"c.eq.ob", "Y,Q",        0x78000001, 0xfc2007ff,        WR_CC|RD_S|RD_T|FP_D,        0,                MX|SB1        },
1373
{"c.eq.ob", "S,T",        0x4ac00001, 0xffe007ff,        WR_CC|RD_S|RD_T,        0,                N54        },
1374
{"c.eq.ob", "S,T[e]",        0x48000001, 0xfe2007ff,        WR_CC|RD_S|RD_T,        0,                N54        },
1375
{"c.eq.ob", "S,k",        0x4bc00001, 0xffe007ff,        WR_CC|RD_S|RD_T,        0,                N54        },
1376
{"c.eq.ps", "S,T",        0x46c00032, 0xffe007ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I5|I33        },
1377
{"c.eq.ps", "M,S,T",        0x46c00032, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I5|I33        },
1378
{"c.eq.qh", "Y,Q",        0x78200001, 0xfc2007ff,        WR_CC|RD_S|RD_T|FP_D,        0,                MX        },
1379
{"c.ueq.d", "S,T",        0x46200033, 0xffe007ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I1        },
1380
{"c.ueq.d", "M,S,T",    0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,                I4|I32        },
1381
{"c.ueq.s", "S,T",      0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,                I1      },
1382
{"c.ueq.s", "M,S,T",    0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,                I4|I32        },
1383
{"c.ueq.ps","S,T",        0x46c00033, 0xffe007ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I5|I33        },
1384
{"c.ueq.ps","M,S,T",        0x46c00033, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I5|I33        },
1385
{"c.olt.d", "S,T",      0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,                I1      },
1386
{"c.olt.d", "M,S,T",    0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,                I4|I32        },
1387
{"c.olt.s", "S,T",        0x46000034, 0xffe007ff,        RD_S|RD_T|WR_CC|FP_S,        0,                I1        },
1388
{"c.olt.s", "M,S,T",    0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,                I4|I32        },
1389
{"c.olt.ps","S,T",        0x46c00034, 0xffe007ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I5|I33        },
1390
{"c.olt.ps","M,S,T",        0x46c00034, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I5|I33        },
1391
{"c.ult.d", "S,T",        0x46200035, 0xffe007ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I1        },
1392
{"c.ult.d", "M,S,T",    0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,                I4|I32        },
1393
{"c.ult.s", "S,T",      0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,                I1      },
1394
{"c.ult.s", "M,S,T",    0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,                I4|I32        },
1395
{"c.ult.ps","S,T",        0x46c00035, 0xffe007ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I5|I33        },
1396
{"c.ult.ps","M,S,T",        0x46c00035, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I5|I33        },
1397
{"c.ole.d", "S,T",      0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,                I1      },
1398
{"c.ole.d", "M,S,T",    0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,                I4|I32        },
1399
{"c.ole.s", "S,T",      0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,                I1      },
1400
{"c.ole.s", "M,S,T",    0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,                I4|I32        },
1401
{"c.ole.ps","S,T",        0x46c00036, 0xffe007ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I5|I33        },
1402
{"c.ole.ps","M,S,T",        0x46c00036, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I5|I33        },
1403
{"c.ule.d", "S,T",        0x46200037, 0xffe007ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I1        },
1404
{"c.ule.d", "M,S,T",    0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,                I4|I32        },
1405
{"c.ule.s", "S,T",      0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,                I1      },
1406
{"c.ule.s", "M,S,T",    0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,                I4|I32        },
1407
{"c.ule.ps","S,T",        0x46c00037, 0xffe007ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I5|I33        },
1408
{"c.ule.ps","M,S,T",        0x46c00037, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I5|I33        },
1409
{"c.sf.d",  "S,T",        0x46200038, 0xffe007ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I1        },
1410
{"c.sf.d",  "M,S,T",    0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,                I4|I32        },
1411
{"c.sf.s",  "S,T",      0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,                I1      },
1412
{"c.sf.s",  "M,S,T",    0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,                I4|I32        },
1413
{"c.sf.ps", "S,T",        0x46c00038, 0xffe007ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I5|I33        },
1414
{"c.sf.ps", "M,S,T",        0x46c00038, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I5|I33        },
1415
{"c.ngle.d","S,T",        0x46200039, 0xffe007ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I1        },
1416
{"c.ngle.d","M,S,T",    0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,                I4|I32        },
1417
{"c.ngle.s","S,T",      0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,                I1      },
1418
{"c.ngle.s","M,S,T",    0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,                I4|I32        },
1419
{"c.ngle.ps","S,T",        0x46c00039, 0xffe007ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I5|I33        },
1420
{"c.ngle.ps","M,S,T",        0x46c00039, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I5|I33        },
1421
{"c.seq.d", "S,T",        0x4620003a, 0xffe007ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I1        },
1422
{"c.seq.d", "M,S,T",    0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,                I4|I32        },
1423
{"c.seq.s", "S,T",      0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,                I1      },
1424
{"c.seq.s", "M,S,T",    0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,                I4|I32        },
1425
{"c.seq.ps","S,T",        0x46c0003a, 0xffe007ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I5|I33        },
1426
{"c.seq.ps","M,S,T",        0x46c0003a, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I5|I33        },
1427
{"c.ngl.d", "S,T",        0x4620003b, 0xffe007ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I1        },
1428
{"c.ngl.d", "M,S,T",    0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,                I4|I32        },
1429
{"c.ngl.s", "S,T",      0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,                I1      },
1430
{"c.ngl.s", "M,S,T",    0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,                I4|I32        },
1431
{"c.ngl.ps","S,T",        0x46c0003b, 0xffe007ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I5|I33        },
1432
{"c.ngl.ps","M,S,T",        0x46c0003b, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I5|I33        },
1433
{"c.lt.d",  "S,T",        0x4620003c, 0xffe007ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I1        },
1434
{"c.lt.d",  "M,S,T",    0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,                I4|I32        },
1435
{"c.lt.s",  "S,T",        0x4600003c, 0xffe007ff,        RD_S|RD_T|WR_CC|FP_S,        0,                I1        },
1436
{"c.lt.s",  "M,S,T",    0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,                I4|I32        },
1437
{"c.lt.ob", "Y,Q",        0x78000004, 0xfc2007ff,        WR_CC|RD_S|RD_T|FP_D,        0,                MX|SB1        },
1438
{"c.lt.ob", "S,T",        0x4ac00004, 0xffe007ff,        WR_CC|RD_S|RD_T,        0,                N54        },
1439
{"c.lt.ob", "S,T[e]",        0x48000004, 0xfe2007ff,        WR_CC|RD_S|RD_T,        0,                N54        },
1440
{"c.lt.ob", "S,k",        0x4bc00004, 0xffe007ff,        WR_CC|RD_S|RD_T,        0,                N54        },
1441
{"c.lt.ps", "S,T",        0x46c0003c, 0xffe007ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I5|I33        },
1442
{"c.lt.ps", "M,S,T",        0x46c0003c, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I5|I33        },
1443
{"c.lt.qh", "Y,Q",        0x78200004, 0xfc2007ff,        WR_CC|RD_S|RD_T|FP_D,        0,                MX        },
1444
{"c.nge.d", "S,T",        0x4620003d, 0xffe007ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I1        },
1445
{"c.nge.d", "M,S,T",    0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,                I4|I32        },
1446
{"c.nge.s", "S,T",      0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,                I1      },
1447
{"c.nge.s", "M,S,T",    0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,                I4|I32        },
1448
{"c.nge.ps","S,T",        0x46c0003d, 0xffe007ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I5|I33        },
1449
{"c.nge.ps","M,S,T",        0x46c0003d, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I5|I33        },
1450
{"c.le.d",  "S,T",        0x4620003e, 0xffe007ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I1        },
1451
{"c.le.d",  "M,S,T",    0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,                I4|I32        },
1452
{"c.le.s",  "S,T",        0x4600003e, 0xffe007ff,        RD_S|RD_T|WR_CC|FP_S,        0,                I1        },
1453
{"c.le.s",  "M,S,T",    0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,                I4|I32        },
1454
{"c.le.ob", "Y,Q",        0x78000005, 0xfc2007ff,        WR_CC|RD_S|RD_T|FP_D,        0,                MX|SB1        },
1455
{"c.le.ob", "S,T",        0x4ac00005, 0xffe007ff,        WR_CC|RD_S|RD_T,        0,                N54        },
1456
{"c.le.ob", "S,T[e]",        0x48000005, 0xfe2007ff,        WR_CC|RD_S|RD_T,        0,                N54        },
1457
{"c.le.ob", "S,k",        0x4bc00005, 0xffe007ff,        WR_CC|RD_S|RD_T,        0,                N54        },
1458
{"c.le.ps", "S,T",        0x46c0003e, 0xffe007ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I5|I33        },
1459
{"c.le.ps", "M,S,T",        0x46c0003e, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I5|I33        },
1460
{"c.le.qh", "Y,Q",        0x78200005, 0xfc2007ff,        WR_CC|RD_S|RD_T|FP_D,        0,                MX        },
1461
{"c.ngt.d", "S,T",        0x4620003f, 0xffe007ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I1        },
1462
{"c.ngt.d", "M,S,T",    0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,                I4|I32        },
1463
{"c.ngt.s", "S,T",      0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,                I1      },
1464
{"c.ngt.s", "M,S,T",    0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,                I4|I32        },
1465
{"c.ngt.ps","S,T",        0x46c0003f, 0xffe007ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I5|I33        },
1466
{"c.ngt.ps","M,S,T",        0x46c0003f, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                I5|I33        },
1467
{"cabs.eq.d",  "M,S,T",        0x46200072, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                M3D        },
1468
{"cabs.eq.ps", "M,S,T",        0x46c00072, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                M3D        },
1469
{"cabs.eq.s",  "M,S,T",        0x46000072, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_S,        0,                M3D        },
1470
{"cabs.f.d",   "M,S,T",        0x46200070, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                M3D        },
1471
{"cabs.f.ps",  "M,S,T",        0x46c00070, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                M3D        },
1472
{"cabs.f.s",   "M,S,T",        0x46000070, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_S,        0,                M3D        },
1473
{"cabs.le.d",  "M,S,T",        0x4620007e, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                M3D        },
1474
{"cabs.le.ps", "M,S,T",        0x46c0007e, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                M3D        },
1475
{"cabs.le.s",  "M,S,T",        0x4600007e, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_S,        0,                M3D        },
1476
{"cabs.lt.d",  "M,S,T",        0x4620007c, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                M3D        },
1477
{"cabs.lt.ps", "M,S,T",        0x46c0007c, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                M3D        },
1478
{"cabs.lt.s",  "M,S,T",        0x4600007c, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_S,        0,                M3D        },
1479
{"cabs.nge.d", "M,S,T",        0x4620007d, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                M3D        },
1480
{"cabs.nge.ps","M,S,T",        0x46c0007d, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                M3D        },
1481
{"cabs.nge.s", "M,S,T",        0x4600007d, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_S,        0,                M3D        },
1482
{"cabs.ngl.d", "M,S,T",        0x4620007b, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                M3D        },
1483
{"cabs.ngl.ps","M,S,T",        0x46c0007b, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                M3D        },
1484
{"cabs.ngl.s", "M,S,T",        0x4600007b, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_S,        0,                M3D        },
1485
{"cabs.ngle.d","M,S,T",        0x46200079, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                M3D        },
1486
{"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                M3D        },
1487
{"cabs.ngle.s","M,S,T",        0x46000079, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_S,        0,                M3D        },
1488
{"cabs.ngt.d", "M,S,T",        0x4620007f, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                M3D        },
1489
{"cabs.ngt.ps","M,S,T",        0x46c0007f, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                M3D        },
1490
{"cabs.ngt.s", "M,S,T",        0x4600007f, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_S,        0,                M3D        },
1491
{"cabs.ole.d", "M,S,T",        0x46200076, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                M3D        },
1492
{"cabs.ole.ps","M,S,T",        0x46c00076, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                M3D        },
1493
{"cabs.ole.s", "M,S,T",        0x46000076, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_S,        0,                M3D        },
1494
{"cabs.olt.d", "M,S,T",        0x46200074, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                M3D        },
1495
{"cabs.olt.ps","M,S,T",        0x46c00074, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                M3D        },
1496
{"cabs.olt.s", "M,S,T",        0x46000074, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_S,        0,                M3D        },
1497
{"cabs.seq.d", "M,S,T",        0x4620007a, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                M3D        },
1498
{"cabs.seq.ps","M,S,T",        0x46c0007a, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                M3D        },
1499
{"cabs.seq.s", "M,S,T",        0x4600007a, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_S,        0,                M3D        },
1500
{"cabs.sf.d",  "M,S,T",        0x46200078, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                M3D        },
1501
{"cabs.sf.ps", "M,S,T",        0x46c00078, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                M3D        },
1502
{"cabs.sf.s",  "M,S,T",        0x46000078, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_S,        0,                M3D        },
1503
{"cabs.ueq.d", "M,S,T",        0x46200073, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                M3D        },
1504
{"cabs.ueq.ps","M,S,T",        0x46c00073, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                M3D        },
1505
{"cabs.ueq.s", "M,S,T",        0x46000073, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_S,        0,                M3D        },
1506
{"cabs.ule.d", "M,S,T",        0x46200077, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                M3D        },
1507
{"cabs.ule.ps","M,S,T",        0x46c00077, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                M3D        },
1508
{"cabs.ule.s", "M,S,T",        0x46000077, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_S,        0,                M3D        },
1509
{"cabs.ult.d", "M,S,T",        0x46200075, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                M3D        },
1510
{"cabs.ult.ps","M,S,T",        0x46c00075, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                M3D        },
1511
{"cabs.ult.s", "M,S,T",        0x46000075, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_S,        0,                M3D        },
1512
{"cabs.un.d",  "M,S,T",        0x46200071, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                M3D        },
1513
{"cabs.un.ps", "M,S,T",        0x46c00071, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,        0,                M3D        },
1514
{"cabs.un.s",  "M,S,T",        0x46000071, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_S,        0,                M3D        },
1515
/* CW4010 instructions which are aliases for the cache instruction.  */
1516
{"flushi",  "",                0xbc010000, 0xffffffff, 0,                        0,                L1        },
1517
{"flushd",  "",                0xbc020000, 0xffffffff, 0,                         0,                L1        },
1518
{"flushid", "",                0xbc030000, 0xffffffff, 0,                         0,                L1        },
1519
{"wb",             "o(b)",        0xbc040000, 0xfc1f0000, SM|RD_b,                0,                L1        },
1520
{"cache",   "k,o(b)",   0xbc000000, 0xfc000000, RD_b,                   0,                I3|I32|T3},
1521
{"cache",   "k,A(b)",        0,    (int) M_CACHE_AB, INSN_MACRO,                0,                I3|I32|T3},
1522
{"ceil.l.d", "D,S",        0x4620000a, 0xffff003f, WR_D|RD_S|FP_D,                0,                I3|I33        },
1523
{"ceil.l.s", "D,S",        0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D,        0,                I3|I33        },
1524
{"ceil.w.d", "D,S",        0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D,        0,                I2        },
1525
{"ceil.w.s", "D,S",        0x4600000e, 0xffff003f, WR_D|RD_S|FP_S,                0,                I2        },
1526
{"cfc0",    "t,G",        0x40400000, 0xffe007ff,        LCD|WR_t|RD_C0,                0,                I1        },
1527
{"cfc1",    "t,G",        0x44400000, 0xffe007ff,        LCD|WR_t|RD_C1|FP_S,        0,                I1        },
1528
{"cfc1",    "t,S",        0x44400000, 0xffe007ff,        LCD|WR_t|RD_C1|FP_S,        0,                I1        },
1529
/* cfc2 is at the bottom of the table.  */
1530
/* cfc3 is at the bottom of the table.  */
1531
{"cftc1",   "d,E",        0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0,                MT32        },
1532
{"cftc1",   "d,T",        0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0,                MT32        },
1533
{"cftc2",   "d,E",        0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,        0,                MT32        },
1534
{"clo",     "U,s",      0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s,         0,                I32|N55 },
1535
{"clz",     "U,s",      0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s,         0,                I32|N55 },
1536
{"ctc0",    "t,G",        0x40c00000, 0xffe007ff,        COD|RD_t|WR_CC,                0,                I1        },
1537
{"ctc1",    "t,G",        0x44c00000, 0xffe007ff,        COD|RD_t|WR_CC|FP_S,        0,                I1        },
1538
{"ctc1",    "t,S",        0x44c00000, 0xffe007ff,        COD|RD_t|WR_CC|FP_S,        0,                I1        },
1539
/* ctc2 is at the bottom of the table.  */
1540
/* ctc3 is at the bottom of the table.  */
1541
{"cttc1",   "t,g",        0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0,                MT32        },
1542
{"cttc1",   "t,S",        0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0,                MT32        },
1543
{"cttc2",   "t,g",        0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC,        0,                MT32        },
1544
{"cvt.d.l", "D,S",        0x46a00021, 0xffff003f,        WR_D|RD_S|FP_D,                0,                I3|I33        },
1545
{"cvt.d.s", "D,S",        0x46000021, 0xffff003f,        WR_D|RD_S|FP_S|FP_D,        0,                I1        },
1546
{"cvt.d.w", "D,S",        0x46800021, 0xffff003f,        WR_D|RD_S|FP_S|FP_D,        0,                I1        },
1547
{"cvt.l.d", "D,S",        0x46200025, 0xffff003f,        WR_D|RD_S|FP_D,                0,                I3|I33        },
1548
{"cvt.l.s", "D,S",        0x46000025, 0xffff003f,        WR_D|RD_S|FP_S|FP_D,        0,                I3|I33        },
1549
{"cvt.s.l", "D,S",        0x46a00020, 0xffff003f,        WR_D|RD_S|FP_S|FP_D,        0,                I3|I33        },
1550
{"cvt.s.d", "D,S",        0x46200020, 0xffff003f,        WR_D|RD_S|FP_S|FP_D,        0,                I1        },
1551
{"cvt.s.w", "D,S",        0x46800020, 0xffff003f,        WR_D|RD_S|FP_S,                0,                I1        },
1552
{"cvt.s.pl","D,S",        0x46c00028, 0xffff003f,        WR_D|RD_S|FP_S|FP_D,        0,                I5|I33        },
1553
{"cvt.s.pu","D,S",        0x46c00020, 0xffff003f,        WR_D|RD_S|FP_S|FP_D,        0,                I5|I33        },
1554
{"cvt.w.d", "D,S",        0x46200024, 0xffff003f,        WR_D|RD_S|FP_S|FP_D,        0,                I1        },
1555
{"cvt.w.s", "D,S",        0x46000024, 0xffff003f,        WR_D|RD_S|FP_S,                0,                I1        },
1556
{"cvt.ps.pw", "D,S",        0x46800026, 0xffff003f,        WR_D|RD_S|FP_S|FP_D,        0,                M3D        },
1557
{"cvt.ps.s","D,V,T",        0x46000026, 0xffe0003f,        WR_D|RD_S|RD_T|FP_S|FP_D, 0,                I5|I33        },
1558
{"cvt.pw.ps", "D,S",        0x46c00024, 0xffff003f,        WR_D|RD_S|FP_S|FP_D,        0,                M3D        },
1559
{"dabs",    "d,v",        0,    (int) M_DABS,        INSN_MACRO,                0,                I3        },
1560
{"dadd",    "d,v,t",        0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t,                0,                I3        },
1561
{"dadd",    "t,r,I",        0,    (int) M_DADD_I,        INSN_MACRO,                0,                I3        },
1562
{"daddi",   "t,r,j",        0x60000000, 0xfc000000, WR_t|RD_s,                0,                I3        },
1563
{"daddiu",  "t,r,j",        0x64000000, 0xfc000000, WR_t|RD_s,                0,                I3        },
1564
{"daddu",   "d,v,t",        0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t,                0,                I3        },
1565
{"daddu",   "t,r,I",        0,    (int) M_DADDU_I,        INSN_MACRO,                0,                I3        },
1566
{"dbreak",  "",                0x7000003f, 0xffffffff,        0,                        0,                N5        },
1567
{"dclo",    "U,s",      0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t,         0,                I64|N55 },
1568
{"dclz",    "U,s",      0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t,         0,                I64|N55 },
1569
/* dctr and dctw are used on the r5000.  */
1570
{"dctr",    "o(b)",        0xbc050000, 0xfc1f0000, RD_b,                        0,                I3        },
1571
{"dctw",    "o(b)",        0xbc090000, 0xfc1f0000, RD_b,                        0,                I3        },
1572
{"deret",   "",         0x4200001f, 0xffffffff, 0,                         0,                I32|G2        },
1573
{"dext",    "t,r,I,+I",        0,    (int) M_DEXT,        INSN_MACRO,                0,                I65        },
1574
{"dext",    "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s,                    0,                I65        },
1575
{"dextm",   "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s,                    0,                I65        },
1576
{"dextu",   "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s,                    0,                I65        },
1577
/* For ddiv, see the comments about div.  */
1578
{"ddiv",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,                I3      },
1579
{"ddiv",    "d,v,t",        0,    (int) M_DDIV_3,        INSN_MACRO,                0,                I3        },
1580
{"ddiv",    "d,v,I",        0,    (int) M_DDIV_3I,        INSN_MACRO,                0,                I3        },
1581
/* For ddivu, see the comments about div.  */
1582
{"ddivu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,                I3      },
1583
{"ddivu",   "d,v,t",        0,    (int) M_DDIVU_3,        INSN_MACRO,                0,                I3        },
1584
{"ddivu",   "d,v,I",        0,    (int) M_DDIVU_3I,        INSN_MACRO,                0,                I3        },
1585
{"di",      "",                0x41606000, 0xffffffff,        WR_t|WR_C0,                0,                I33        },
1586
{"di",      "t",        0x41606000, 0xffe0ffff,        WR_t|WR_C0,                0,                I33        },
1587
{"dins",    "t,r,I,+I",        0,    (int) M_DINS,        INSN_MACRO,                0,                I65        },
1588
{"dins",    "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s,                    0,                I65        },
1589
{"dinsm",   "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s,                    0,                I65        },
1590
{"dinsu",   "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s,                    0,                I65        },
1591
/* The MIPS assembler treats the div opcode with two operands as
1592
   though the first operand appeared twice (the first operand is both
1593
   a source and a destination).  To get the div machine instruction,
1594
   you must use an explicit destination of $0.  */
1595
{"div",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,                I1      },
1596
{"div",     "z,t",      0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO,      0,                I1      },
1597
{"div",     "d,v,t",        0,    (int) M_DIV_3,        INSN_MACRO,                0,                I1        },
1598
{"div",     "d,v,I",        0,    (int) M_DIV_3I,        INSN_MACRO,                0,                I1        },
1599
{"div.d",   "D,V,T",        0x46200003, 0xffe0003f,        WR_D|RD_S|RD_T|FP_D,        0,                I1        },
1600
{"div.s",   "D,V,T",        0x46000003, 0xffe0003f,        WR_D|RD_S|RD_T|FP_S,        0,                I1        },
1601
{"div.ps",  "D,V,T",        0x46c00003, 0xffe0003f,        WR_D|RD_S|RD_T|FP_D,        0,                SB1        },
1602
/* For divu, see the comments about div.  */
1603
{"divu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,                I1      },
1604
{"divu",    "z,t",      0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO,      0,                I1      },
1605
{"divu",    "d,v,t",        0,    (int) M_DIVU_3,        INSN_MACRO,                0,                I1        },
1606
{"divu",    "d,v,I",        0,    (int) M_DIVU_3I,        INSN_MACRO,                0,                I1        },
1607
{"dla",     "t,A(b)",        0,    (int) M_DLA_AB,        INSN_MACRO,                0,                I3        },
1608
{"dlca",    "t,A(b)",        0,    (int) M_DLCA_AB,        INSN_MACRO,                0,                I3        },
1609
{"dli",     "t,j",      0x24000000, 0xffe00000, WR_t,                        0,                I3        }, /* addiu */
1610
{"dli",            "t,i",        0x34000000, 0xffe00000, WR_t,                        0,                I3        }, /* ori */
1611
{"dli",     "t,I",        0,    (int) M_DLI,        INSN_MACRO,                0,                I3        },
1612
{"dmacc",   "d,s,t",        0x00000029, 0xfc0007ff,        RD_s|RD_t|WR_LO|WR_d,        0,                N412        },
1613
{"dmacchi", "d,s,t",        0x00000229, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,        0,                N412        },
1614
{"dmacchis", "d,s,t",        0x00000629, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,        0,                N412        },
1615
{"dmacchiu", "d,s,t",        0x00000269, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,        0,                N412        },
1616
{"dmacchius", "d,s,t",        0x00000669, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,        0,                N412        },
1617
{"dmaccs",  "d,s,t",        0x00000429, 0xfc0007ff,        RD_s|RD_t|WR_LO|WR_d,        0,                N412        },
1618
{"dmaccu",  "d,s,t",        0x00000069, 0xfc0007ff,        RD_s|RD_t|WR_LO|WR_d,        0,                N412        },
1619
{"dmaccus", "d,s,t",        0x00000469, 0xfc0007ff,        RD_s|RD_t|WR_LO|WR_d,        0,                N412        },
1620
{"dmadd16", "s,t",      0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO,       0,                N411    },
1621
{"dmfc0",   "t,G",        0x40200000, 0xffe007ff, LCD|WR_t|RD_C0,                0,                I3        },
1622
{"dmfc0",   "t,+D",     0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,         0,                I64     },
1623
{"dmfc0",   "t,G,H",    0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,         0,                I64     },
1624
{"dmt",     "",                0x41600bc1, 0xffffffff, TRAP,                        0,                MT32        },
1625
{"dmt",     "t",        0x41600bc1, 0xffe0ffff, TRAP|WR_t,                0,                MT32        },
1626
{"dmtc0",   "t,G",        0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,        0,                I3        },
1627
{"dmtc0",   "t,+D",     0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,                I64     },
1628
{"dmtc0",   "t,G,H",    0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,                I64     },
1629
{"dmfc1",   "t,S",        0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,        0,                I3        },
1630
{"dmfc1",   "t,G",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,                I3      },
1631
{"dmtc1",   "t,S",        0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,        0,                I3        },
1632
{"dmtc1",   "t,G",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,                I3      },
1633
/* dmfc2 is at the bottom of the table.  */
1634
/* dmtc2 is at the bottom of the table.  */
1635
/* dmfc3 is at the bottom of the table.  */
1636
/* dmtc3 is at the bottom of the table.  */
1637
{"dmul",    "d,v,t",        0,    (int) M_DMUL,        INSN_MACRO,                0,                I3        },
1638
{"dmul",    "d,v,I",        0,    (int) M_DMUL_I,        INSN_MACRO,                0,                I3        },
1639
{"dmulo",   "d,v,t",        0,    (int) M_DMULO,        INSN_MACRO,                0,                I3        },
1640
{"dmulo",   "d,v,I",        0,    (int) M_DMULO_I,        INSN_MACRO,                0,                I3        },
1641
{"dmulou",  "d,v,t",        0,    (int) M_DMULOU,        INSN_MACRO,                0,                I3        },
1642
{"dmulou",  "d,v,I",        0,    (int) M_DMULOU_I,        INSN_MACRO,                0,                I3        },
1643
{"dmult",   "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,                I3        },
1644
{"dmultu",  "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,                I3        },
1645
{"dneg",    "d,w",        0x0000002e, 0xffe007ff,        WR_d|RD_t,                0,                I3        }, /* dsub 0 */
1646
{"dnegu",   "d,w",        0x0000002f, 0xffe007ff,        WR_d|RD_t,                0,                I3        }, /* dsubu 0*/
1647
{"drem",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,                I3      },
1648
{"drem",    "d,v,t",        3,    (int) M_DREM_3,        INSN_MACRO,                0,                I3        },
1649
{"drem",    "d,v,I",        3,    (int) M_DREM_3I,        INSN_MACRO,                0,                I3        },
1650
{"dremu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,                I3      },
1651
{"dremu",   "d,v,t",        3,    (int) M_DREMU_3,        INSN_MACRO,                0,                I3        },
1652
{"dremu",   "d,v,I",        3,    (int) M_DREMU_3I,        INSN_MACRO,                0,                I3        },
1653
{"dret",    "",                0x7000003e, 0xffffffff,        0,                        0,                N5        },
1654
{"drol",    "d,v,t",        0,    (int) M_DROL,        INSN_MACRO,                0,                I3        },
1655
{"drol",    "d,v,I",        0,    (int) M_DROL_I,        INSN_MACRO,                0,                I3        },
1656
{"dror",    "d,v,t",        0,    (int) M_DROR,        INSN_MACRO,                0,                I3        },
1657
{"dror",    "d,v,I",        0,    (int) M_DROR_I,        INSN_MACRO,                0,                I3        },
1658
{"dror",    "d,w,<",        0x0020003a, 0xffe0003f,        WR_d|RD_t,                0,                N5|I65        },
1659
{"drorv",   "d,t,s",        0x00000056, 0xfc0007ff,        RD_t|RD_s|WR_d,                0,                N5|I65        },
1660
{"dror32",  "d,w,<",        0x0020003e, 0xffe0003f,        WR_d|RD_t,                0,                N5|I65        },
1661
{"drotl",   "d,v,t",        0,    (int) M_DROL,        INSN_MACRO,                0,                I65        },
1662
{"drotl",   "d,v,I",        0,    (int) M_DROL_I,        INSN_MACRO,                0,                I65        },
1663
{"drotr",   "d,v,t",        0,    (int) M_DROR,        INSN_MACRO,                0,                I65        },
1664
{"drotr",   "d,v,I",        0,    (int) M_DROR_I,        INSN_MACRO,                0,                I65        },
1665
{"drotrv",  "d,t,s",        0x00000056, 0xfc0007ff,        RD_t|RD_s|WR_d,                0,                I65        },
1666
{"drotr32", "d,w,<",        0x0020003e, 0xffe0003f,        WR_d|RD_t,                0,                I65        },
1667
{"dsbh",    "d,w",        0x7c0000a4, 0xffe007ff,        WR_d|RD_t,                0,                I65        },
1668
{"dshd",    "d,w",        0x7c000164, 0xffe007ff,        WR_d|RD_t,                0,                I65        },
1669
{"dsllv",   "d,t,s",        0x00000014, 0xfc0007ff,        WR_d|RD_t|RD_s,                0,                I3        },
1670
{"dsll32",  "d,w,<",        0x0000003c, 0xffe0003f, WR_d|RD_t,                0,                I3        },
1671
{"dsll",    "d,w,s",        0x00000014, 0xfc0007ff,        WR_d|RD_t|RD_s,                0,                I3        }, /* dsllv */
1672
{"dsll",    "d,w,>",        0x0000003c, 0xffe0003f, WR_d|RD_t,                0,                I3        }, /* dsll32 */
1673
{"dsll",    "d,w,<",        0x00000038, 0xffe0003f,        WR_d|RD_t,                0,                I3        },
1674
{"dsrav",   "d,t,s",        0x00000017, 0xfc0007ff,        WR_d|RD_t|RD_s,                0,                I3        },
1675
{"dsra32",  "d,w,<",        0x0000003f, 0xffe0003f, WR_d|RD_t,                0,                I3        },
1676
{"dsra",    "d,w,s",        0x00000017, 0xfc0007ff,        WR_d|RD_t|RD_s,                0,                I3        }, /* dsrav */
1677
{"dsra",    "d,w,>",        0x0000003f, 0xffe0003f, WR_d|RD_t,                0,                I3        }, /* dsra32 */
1678
{"dsra",    "d,w,<",        0x0000003b, 0xffe0003f,        WR_d|RD_t,                0,                I3        },
1679
{"dsrlv",   "d,t,s",        0x00000016, 0xfc0007ff,        WR_d|RD_t|RD_s,                0,                I3        },
1680
{"dsrl32",  "d,w,<",        0x0000003e, 0xffe0003f, WR_d|RD_t,                0,                I3        },
1681
{"dsrl",    "d,w,s",        0x00000016, 0xfc0007ff,        WR_d|RD_t|RD_s,                0,                I3        }, /* dsrlv */
1682
{"dsrl",    "d,w,>",        0x0000003e, 0xffe0003f, WR_d|RD_t,                0,                I3        }, /* dsrl32 */
1683
{"dsrl",    "d,w,<",        0x0000003a, 0xffe0003f,        WR_d|RD_t,                0,                I3        },
1684
{"dsub",    "d,v,t",        0x0000002e, 0xfc0007ff,        WR_d|RD_s|RD_t,                0,                I3        },
1685
{"dsub",    "d,v,I",        0,    (int) M_DSUB_I,        INSN_MACRO,                0,                I3        },
1686
{"dsubu",   "d,v,t",        0x0000002f, 0xfc0007ff,        WR_d|RD_s|RD_t,                0,                I3        },
1687
{"dsubu",   "d,v,I",        0,    (int) M_DSUBU_I,        INSN_MACRO,                0,                I3        },
1688
{"dvpe",    "",                0x41600001, 0xffffffff, TRAP,                        0,                MT32        },
1689
{"dvpe",    "t",        0x41600001, 0xffe0ffff, TRAP|WR_t,                0,                MT32        },
1690
{"ei",      "",                0x41606020, 0xffffffff,        WR_t|WR_C0,                0,                I33        },
1691
{"ei",      "t",        0x41606020, 0xffe0ffff,        WR_t|WR_C0,                0,                I33        },
1692
{"emt",     "",                0x41600be1, 0xffffffff, TRAP,                        0,                MT32        },
1693
{"emt",     "t",        0x41600be1, 0xffe0ffff, TRAP|WR_t,                0,                MT32        },
1694
{"eret",    "",         0x42000018, 0xffffffff, 0,                      0,                I3|I32        },
1695
{"evpe",    "",                0x41600021, 0xffffffff, TRAP,                        0,                MT32        },
1696
{"evpe",    "t",        0x41600021, 0xffe0ffff, TRAP|WR_t,                0,                MT32        },
1697
{"ext",     "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s,                    0,                I33        },
1698
{"floor.l.d", "D,S",        0x4620000b, 0xffff003f, WR_D|RD_S|FP_D,                0,                I3|I33        },
1699
{"floor.l.s", "D,S",        0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D,        0,                I3|I33        },
1700
{"floor.w.d", "D,S",        0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D,        0,                I2        },
1701
{"floor.w.s", "D,S",        0x4600000f, 0xffff003f, WR_D|RD_S|FP_S,                0,                I2        },
1702
{"hibernate","",        0x42000023, 0xffffffff,        0,                         0,                V1        },
1703
{"ins",     "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s,                    0,                I33        },
1704
{"jr",      "s",        0x00000008, 0xfc1fffff,        UBD|RD_s,                0,                I1        },
1705
/* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
1706
   the same hazard barrier effect.  */
1707
{"jr.hb",   "s",        0x00000408, 0xfc1fffff,        UBD|RD_s,                0,                I32        },
1708
{"j",       "s",        0x00000008, 0xfc1fffff,        UBD|RD_s,                0,                I1        }, /* jr */
1709
/* SVR4 PIC code requires special handling for j, so it must be a
1710
   macro.  */
1711
{"j",            "a",        0,     (int) M_J_A,        INSN_MACRO,                0,                I1        },
1712
/* This form of j is used by the disassembler and internally by the
1713
   assembler, but will never match user input (because the line above
1714
   will match first).  */
1715
{"j",       "a",        0x08000000, 0xfc000000,        UBD,                        0,                I1        },
1716
{"jalr",    "s",        0x0000f809, 0xfc1fffff,        UBD|RD_s|WR_d,                0,                I1        },
1717
{"jalr",    "d,s",        0x00000009, 0xfc1f07ff,        UBD|RD_s|WR_d,                0,                I1        },
1718
/* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr
1719
   with the same hazard barrier effect.  */
1720
{"jalr.hb", "s",        0x0000fc09, 0xfc1fffff,        UBD|RD_s|WR_d,                0,                I32        },
1721
{"jalr.hb", "d,s",        0x00000409, 0xfc1f07ff,        UBD|RD_s|WR_d,                0,                I32        },
1722
/* SVR4 PIC code requires special handling for jal, so it must be a
1723
   macro.  */
1724
{"jal",     "d,s",        0,     (int) M_JAL_2,        INSN_MACRO,                0,                I1        },
1725
{"jal",     "s",        0,     (int) M_JAL_1,        INSN_MACRO,                0,                I1        },
1726
{"jal",     "a",        0,     (int) M_JAL_A,        INSN_MACRO,                0,                I1        },
1727
/* This form of jal is used by the disassembler and internally by the
1728
   assembler, but will never match user input (because the line above
1729
   will match first).  */
1730
{"jal",     "a",        0x0c000000, 0xfc000000,        UBD|WR_31,                0,                I1        },
1731
{"jalx",    "a",        0x74000000, 0xfc000000, UBD|WR_31,                0,                I16     },
1732
{"la",      "t,A(b)",        0,    (int) M_LA_AB,        INSN_MACRO,                0,                I1        },
1733
{"lb",      "t,o(b)",        0x80000000, 0xfc000000,        LDD|RD_b|WR_t,                0,                I1        },
1734
{"lb",      "t,A(b)",        0,    (int) M_LB_AB,        INSN_MACRO,                0,                I1        },
1735
{"lbu",     "t,o(b)",        0x90000000, 0xfc000000,        LDD|RD_b|WR_t,                0,                I1        },
1736
{"lbu",     "t,A(b)",        0,    (int) M_LBU_AB,        INSN_MACRO,                0,                I1        },
1737
{"lca",     "t,A(b)",        0,    (int) M_LCA_AB,        INSN_MACRO,                0,                I1        },
1738
{"ld",            "t,o(b)",   0xdc000000, 0xfc000000, WR_t|RD_b,                0,                I3        },
1739
{"ld",      "t,o(b)",        0,    (int) M_LD_OB,        INSN_MACRO,                0,                I1        },
1740
{"ld",      "t,A(b)",        0,    (int) M_LD_AB,        INSN_MACRO,                0,                I1        },
1741
{"ldc1",    "T,o(b)",        0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,        0,                I2        },
1742
{"ldc1",    "E,o(b)",        0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,        0,                I2        },
1743
{"ldc1",    "T,A(b)",        0,    (int) M_LDC1_AB,        INSN_MACRO,                0,                I2        },
1744
{"ldc1",    "E,A(b)",        0,    (int) M_LDC1_AB,        INSN_MACRO,                0,                I2        },
1745
{"l.d",     "T,o(b)",        0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,        0,                I2        }, /* ldc1 */
1746
{"l.d",     "T,o(b)",        0,    (int) M_L_DOB,        INSN_MACRO,                0,                I1        },
1747
{"l.d",     "T,A(b)",        0,    (int) M_L_DAB,        INSN_MACRO,                0,                I1        },
1748
{"ldc2",    "E,o(b)",        0xd8000000, 0xfc000000, CLD|RD_b|WR_CC,                0,                I2        },
1749
{"ldc2",    "E,A(b)",        0,    (int) M_LDC2_AB,        INSN_MACRO,                0,                I2        },
1750
{"ldc3",    "E,o(b)",        0xdc000000, 0xfc000000, CLD|RD_b|WR_CC,                0,                I2        },
1751
{"ldc3",    "E,A(b)",        0,    (int) M_LDC3_AB,        INSN_MACRO,                0,                I2        },
1752
{"ldl",            "t,o(b)",        0x68000000, 0xfc000000, LDD|WR_t|RD_b,                0,                I3        },
1753
{"ldl",            "t,A(b)",        0,    (int) M_LDL_AB,        INSN_MACRO,                0,                I3        },
1754
{"ldr",            "t,o(b)",        0x6c000000, 0xfc000000, LDD|WR_t|RD_b,                0,                I3        },
1755
{"ldr",     "t,A(b)",        0,    (int) M_LDR_AB,        INSN_MACRO,                0,                I3        },
1756
{"ldxc1",   "D,t(b)",        0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,                I4|I33        },
1757
{"lh",      "t,o(b)",        0x84000000, 0xfc000000,        LDD|RD_b|WR_t,                0,                I1        },
1758
{"lh",      "t,A(b)",        0,    (int) M_LH_AB,        INSN_MACRO,                0,                I1        },
1759
{"lhu",     "t,o(b)",        0x94000000, 0xfc000000,        LDD|RD_b|WR_t,                0,                I1        },
1760
{"lhu",     "t,A(b)",        0,    (int) M_LHU_AB,        INSN_MACRO,                0,                I1        },
1761
/* li is at the start of the table.  */
1762
{"li.d",    "t,F",        0,    (int) M_LI_D,        INSN_MACRO,                0,                I1        },
1763
{"li.d",    "T,L",        0,    (int) M_LI_DD,        INSN_MACRO,                0,                I1        },
1764
{"li.s",    "t,f",        0,    (int) M_LI_S,        INSN_MACRO,                0,                I1        },
1765
{"li.s",    "T,l",        0,    (int) M_LI_SS,        INSN_MACRO,                0,                I1        },
1766
{"ll",            "t,o(b)",        0xc0000000, 0xfc000000, LDD|RD_b|WR_t,                0,                I2        },
1767
{"ll",            "t,A(b)",        0,    (int) M_LL_AB,        INSN_MACRO,                0,                I2        },
1768
{"lld",            "t,o(b)",        0xd0000000, 0xfc000000, LDD|RD_b|WR_t,                0,                I3        },
1769
{"lld",     "t,A(b)",        0,    (int) M_LLD_AB,        INSN_MACRO,                0,                I3        },
1770
{"lui",     "t,u",        0x3c000000, 0xffe00000,        WR_t,                        0,                I1        },
1771
{"luxc1",   "D,t(b)",        0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,                I5|I33|N55},
1772
{"lw",      "t,o(b)",        0x8c000000, 0xfc000000,        LDD|RD_b|WR_t,                0,                I1        },
1773
{"lw",      "t,A(b)",        0,    (int) M_LW_AB,        INSN_MACRO,                0,                I1        },
1774
{"lwc0",    "E,o(b)",        0xc0000000, 0xfc000000,        CLD|RD_b|WR_CC,                0,                I1        },
1775
{"lwc0",    "E,A(b)",        0,    (int) M_LWC0_AB,        INSN_MACRO,                0,                I1        },
1776
{"lwc1",    "T,o(b)",        0xc4000000, 0xfc000000,        CLD|RD_b|WR_T|FP_S,        0,                I1        },
1777
{"lwc1",    "E,o(b)",        0xc4000000, 0xfc000000,        CLD|RD_b|WR_T|FP_S,        0,                I1        },
1778
{"lwc1",    "T,A(b)",        0,    (int) M_LWC1_AB,        INSN_MACRO,                0,                I1        },
1779
{"lwc1",    "E,A(b)",        0,    (int) M_LWC1_AB,        INSN_MACRO,                0,                I1        },
1780
{"l.s",     "T,o(b)",        0xc4000000, 0xfc000000,        CLD|RD_b|WR_T|FP_S,        0,                I1        }, /* lwc1 */
1781
{"l.s",     "T,A(b)",        0,    (int) M_LWC1_AB,        INSN_MACRO,                0,                I1        },
1782
{"lwc2",    "E,o(b)",        0xc8000000, 0xfc000000,        CLD|RD_b|WR_CC,                0,                I1        },
1783
{"lwc2",    "E,A(b)",        0,    (int) M_LWC2_AB,        INSN_MACRO,                0,                I1        },
1784
{"lwc3",    "E,o(b)",        0xcc000000, 0xfc000000,        CLD|RD_b|WR_CC,                0,                I1        },
1785
{"lwc3",    "E,A(b)",        0,    (int) M_LWC3_AB,        INSN_MACRO,                0,                I1        },
1786
{"lwl",     "t,o(b)",        0x88000000, 0xfc000000,        LDD|RD_b|WR_t,                0,                I1        },
1787
{"lwl",     "t,A(b)",        0,    (int) M_LWL_AB,        INSN_MACRO,                0,                I1        },
1788
{"lcache",  "t,o(b)",        0x88000000, 0xfc000000,        LDD|RD_b|WR_t,                0,                I2        }, /* same */
1789
{"lcache",  "t,A(b)",        0,    (int) M_LWL_AB,        INSN_MACRO,                0,                I2        }, /* as lwl */
1790
{"lwr",     "t,o(b)",        0x98000000, 0xfc000000,        LDD|RD_b|WR_t,                0,                I1        },
1791
{"lwr",     "t,A(b)",        0,    (int) M_LWR_AB,        INSN_MACRO,                0,                I1        },
1792
{"flush",   "t,o(b)",        0x98000000, 0xfc000000,        LDD|RD_b|WR_t,                0,                I2        }, /* same */
1793
{"flush",   "t,A(b)",        0,    (int) M_LWR_AB,        INSN_MACRO,                0,                I2        }, /* as lwr */
1794
{"fork",    "d,s,t",        0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t,        0,                MT32        },
1795
{"lwu",     "t,o(b)",        0x9c000000, 0xfc000000,        LDD|RD_b|WR_t,                0,                I3        },
1796
{"lwu",     "t,A(b)",        0,    (int) M_LWU_AB,        INSN_MACRO,                0,                I3        },
1797
{"lwxc1",   "D,t(b)",        0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,                I4|I33        },
1798
{"lwxs",    "d,t(b)",        0x70000088, 0xfc0007ff,        LDD|RD_b|RD_t|WR_d,        0,                SMT        },
1799
{"macc",    "d,s,t",        0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,                N412    },
1800
{"macc",    "d,s,t",        0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d,        0,                N5      },
1801
{"maccs",   "d,s,t",        0x00000428, 0xfc0007ff,        RD_s|RD_t|WR_HILO|WR_d, 0,                N412    },
1802
{"macchi",  "d,s,t",        0x00000228, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,                N412    },
1803
{"macchi",  "d,s,t",        0x00000358, 0xfc0007ff,        RD_s|RD_t|WR_HILO|WR_d,        0,                N5      },
1804
{"macchis", "d,s,t",        0x00000628, 0xfc0007ff,        RD_s|RD_t|WR_HILO|WR_d, 0,                N412    },
1805
{"macchiu", "d,s,t",        0x00000268, 0xfc0007ff,        RD_s|RD_t|WR_HILO|WR_d, 0,                N412    },
1806
{"macchiu", "d,s,t",        0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d,        0,                N5      },
1807
{"macchius","d,s,t",        0x00000668, 0xfc0007ff,        RD_s|RD_t|WR_HILO|WR_d, 0,                N412    },
1808
{"maccu",   "d,s,t",        0x00000068, 0xfc0007ff,        RD_s|RD_t|WR_HILO|WR_d, 0,                N412    },
1809
{"maccu",   "d,s,t",        0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d,        0,                N5      },
1810
{"maccus",  "d,s,t",        0x00000468, 0xfc0007ff,        RD_s|RD_t|WR_HILO|WR_d, 0,                N412    },
1811
{"mad",     "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,                P3      },
1812
{"madu",    "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,                P3      },
1813
{"madd.d",  "D,R,S,T",        0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,                I4|I33        },
1814
{"madd.s",  "D,R,S,T",        0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,    0,                I4|I33        },
1815
{"madd.ps", "D,R,S,T",        0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,                I5|I33        },
1816
{"madd",    "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,                L1        },
1817
{"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,                I32|N55        },
1818
{"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,                G1        },
1819
{"madd",    "7,s,t",        0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D33        },
1820
{"madd",    "d,s,t",    0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,                G1        },
1821
{"maddp",   "s,t",      0x70000441, 0xfc00ffff,        RD_s|RD_t|MOD_HILO,             0,                SMT        },
1822
{"maddu",   "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,                L1        },
1823
{"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,                I32|N55        },
1824
{"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,                G1        },
1825
{"maddu",   "7,s,t",        0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D33        },
1826
{"maddu",   "d,s,t",    0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,                G1        },
1827
{"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO,        0,                N411    },
1828
{"max.ob",  "X,Y,Q",        0x78000007, 0xfc20003f,        WR_D|RD_S|RD_T|FP_D,        0,                MX|SB1        },
1829
{"max.ob",  "D,S,T",        0x4ac00007, 0xffe0003f,        WR_D|RD_S|RD_T,                0,                N54        },
1830
{"max.ob",  "D,S,T[e]",        0x48000007, 0xfe20003f,        WR_D|RD_S|RD_T,                0,                N54        },
1831
{"max.ob",  "D,S,k",        0x4bc00007, 0xffe0003f,        WR_D|RD_S|RD_T,                0,                N54        },
1832
{"max.qh",  "X,Y,Q",        0x78200007, 0xfc20003f,        WR_D|RD_S|RD_T|FP_D,        0,                MX        },
1833
{"mfpc",    "t,P",        0x4000c801, 0xffe0ffc1,        LCD|WR_t|RD_C0,                0,                M1|N5        },
1834
{"mfps",    "t,P",        0x4000c800, 0xffe0ffc1,        LCD|WR_t|RD_C0,                0,                M1|N5        },
1835
{"mftacx",  "d",        0x41020021, 0xffff07ff, TRAP|WR_d|RD_a,                0,                MT32        },
1836
{"mftacx",  "d,*",        0x41020021, 0xfff307ff, TRAP|WR_d|RD_a,                0,                MT32        },
1837
{"mftc0",   "d,+t",        0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0,        0,                MT32        },
1838
{"mftc0",   "d,+T",        0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0,        0,                MT32        },
1839
{"mftc0",   "d,E,H",        0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0,        0,                MT32        },
1840
{"mftc1",   "d,T",        0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0,                MT32        },
1841
{"mftc1",   "d,E",        0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0,                MT32        },
1842
{"mftc2",   "d,E",        0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,        0,                MT32        },
1843
{"mftdsp",  "d",        0x41100021, 0xffff07ff, TRAP|WR_d,                0,                MT32        },
1844
{"mftgpr",  "d,t",        0x41000020, 0xffe007ff, TRAP|WR_d|RD_t,                0,                MT32        },
1845
{"mfthc1",  "d,T",        0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0,                MT32        },
1846
{"mfthc1",  "d,E",        0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0,                MT32        },
1847
{"mfthc2",  "d,E",        0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,        0,                MT32        },
1848
{"mfthi",   "d",        0x41010021, 0xffff07ff, TRAP|WR_d|RD_a,                0,                MT32        },
1849
{"mfthi",   "d,*",        0x41010021, 0xfff307ff, TRAP|WR_d|RD_a,                0,                MT32        },
1850
{"mftlo",   "d",        0x41000021, 0xffff07ff, TRAP|WR_d|RD_a,                0,                MT32        },
1851
{"mftlo",   "d,*",        0x41000021, 0xfff307ff, TRAP|WR_d|RD_a,                0,                MT32        },
1852
{"mftr",    "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d,                0,                MT32        },
1853
{"mfc0",    "t,G",        0x40000000, 0xffe007ff,        LCD|WR_t|RD_C0,                0,                I1        },
1854
{"mfc0",    "t,+D",     0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,         0,                I32     },
1855
{"mfc0",    "t,G,H",    0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,         0,                I32     },
1856
{"mfc1",    "t,S",        0x44000000, 0xffe007ff,        LCD|WR_t|RD_S|FP_S,        0,                I1        },
1857
{"mfc1",    "t,G",        0x44000000, 0xffe007ff,        LCD|WR_t|RD_S|FP_S,        0,                I1        },
1858
{"mfhc1",   "t,S",        0x44600000, 0xffe007ff,        LCD|WR_t|RD_S|FP_D,        0,                I33        },
1859
{"mfhc1",   "t,G",        0x44600000, 0xffe007ff,        LCD|WR_t|RD_S|FP_D,        0,                I33        },
1860
/* mfc2 is at the bottom of the table.  */
1861
/* mfhc2 is at the bottom of the table.  */
1862
/* mfc3 is at the bottom of the table.  */
1863
{"mfdr",    "t,G",        0x7000003d, 0xffe007ff,        LCD|WR_t|RD_C0,                0,                N5      },
1864
{"mfhi",    "d",        0x00000010, 0xffff07ff,        WR_d|RD_HI,                0,                I1        },
1865
{"mfhi",    "d,9",        0x00000010, 0xff9f07ff, WR_d|RD_HI,                0,                D32        },
1866
{"mflo",    "d",        0x00000012, 0xffff07ff,        WR_d|RD_LO,                0,                I1        },
1867
{"mflo",    "d,9",        0x00000012, 0xff9f07ff, WR_d|RD_LO,                0,                D32        },
1868
{"mflhxu",  "d",        0x00000052, 0xffff07ff,        WR_d|MOD_HILO,                0,                SMT        },
1869
{"min.ob",  "X,Y,Q",        0x78000006, 0xfc20003f,        WR_D|RD_S|RD_T|FP_D,        0,                MX|SB1        },
1870
{"min.ob",  "D,S,T",        0x4ac00006, 0xffe0003f,        WR_D|RD_S|RD_T,                0,                N54        },
1871
{"min.ob",  "D,S,T[e]",        0x48000006, 0xfe20003f,        WR_D|RD_S|RD_T,                0,                N54        },
1872
{"min.ob",  "D,S,k",        0x4bc00006, 0xffe0003f,        WR_D|RD_S|RD_T,                0,                N54        },
1873
{"min.qh",  "X,Y,Q",        0x78200006, 0xfc20003f,        WR_D|RD_S|RD_T|FP_D,        0,                MX        },
1874
{"mov.d",   "D,S",        0x46200006, 0xffff003f,        WR_D|RD_S|FP_D,                0,                I1        },
1875
{"mov.s",   "D,S",        0x46000006, 0xffff003f,        WR_D|RD_S|FP_S,                0,                I1        },
1876
{"mov.ps",  "D,S",        0x46c00006, 0xffff003f,        WR_D|RD_S|FP_D,                0,                I5|I33        },
1877
{"movf",    "d,s,N",    0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0,                I4|I32  },
1878
{"movf.d",  "D,S,N",    0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,                I4|I32        },
1879
{"movf.l",  "D,S,N",        0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,        0,                MX|SB1        },
1880
{"movf.l",  "X,Y,N",        0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,        0,                MX|SB1        },
1881
{"movf.s",  "D,S,N",    0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,                I4|I32        },
1882
{"movf.ps", "D,S,N",        0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,        0,                I5|I33        },
1883
{"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t,         0,                I4|I32        },
1884
{"ffc",     "d,v",        0x0000000b, 0xfc1f07ff,        WR_d|RD_s,                0,                L1        },
1885
{"movn.d",  "D,S,t",    0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,                I4|I32        },
1886
{"movn.l",  "D,S,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,                MX|SB1        },
1887
{"movn.l",  "X,Y,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,                MX|SB1        },
1888
{"movn.s",  "D,S,t",    0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    0,                I4|I32        },
1889
{"movn.ps", "D,S,t",    0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,                I5|I33        },
1890
{"movt",    "d,s,N",    0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0,                I4|I32        },
1891
{"movt.d",  "D,S,N",    0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,                I4|I32        },
1892
{"movt.l",  "D,S,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,                MX|SB1        },
1893
{"movt.l",  "X,Y,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,                MX|SB1        },
1894
{"movt.s",  "D,S,N",    0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,                I4|I32        },
1895
{"movt.ps", "D,S,N",        0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,        0,                I5|I33        },
1896
{"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t,         0,                I4|I32        },
1897
{"ffs",     "d,v",        0x0000000a, 0xfc1f07ff,        WR_d|RD_s,                0,                L1        },
1898
{"movz.d",  "D,S,t",    0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,                I4|I32        },
1899
{"movz.l",  "D,S,t",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,                MX|SB1        },
1900
{"movz.l",  "X,Y,t",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,                MX|SB1        },
1901
{"movz.s",  "D,S,t",    0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    0,                I4|I32        },
1902
{"movz.ps", "D,S,t",    0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,                I5|I33        },
1903
{"msac",    "d,s,t",        0x000001d8, 0xfc0007ff,        RD_s|RD_t|WR_HILO|WR_d,        0,                N5        },
1904
{"msacu",   "d,s,t",        0x000001d9, 0xfc0007ff,        RD_s|RD_t|WR_HILO|WR_d,        0,                N5        },
1905
{"msachi",  "d,s,t",        0x000003d8, 0xfc0007ff,        RD_s|RD_t|WR_HILO|WR_d,        0,                N5        },
1906
{"msachiu", "d,s,t",        0x000003d9, 0xfc0007ff,        RD_s|RD_t|WR_HILO|WR_d,        0,                N5        },
1907
/* move is at the top of the table.  */
1908
{"msgn.qh", "X,Y,Q",        0x78200000, 0xfc20003f,        WR_D|RD_S|RD_T|FP_D,        0,                MX        },
1909
{"msub.d",  "D,R,S,T",        0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,                I4|I33        },
1910
{"msub.s",  "D,R,S,T",        0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,                I4|I33        },
1911
{"msub.ps", "D,R,S,T",        0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,                I5|I33        },
1912
{"msub",    "s,t",      0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,        0,                L1            },
1913
{"msub",    "s,t",      0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,                I32|N55 },
1914
{"msub",    "7,s,t",        0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33        },
1915
{"msubu",   "s,t",      0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,        0,                L1        },
1916
{"msubu",   "s,t",      0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,                I32|N55        },
1917
{"msubu",   "7,s,t",        0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33        },
1918
{"mtpc",    "t,P",        0x4080c801, 0xffe0ffc1,        COD|RD_t|WR_C0,                0,                M1|N5        },
1919
{"mtps",    "t,P",        0x4080c800, 0xffe0ffc1,        COD|RD_t|WR_C0,                0,                M1|N5        },
1920
{"mtc0",    "t,G",        0x40800000, 0xffe007ff,        COD|RD_t|WR_C0|WR_CC,        0,                I1        },
1921
{"mtc0",    "t,+D",     0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,                I32     },
1922
{"mtc0",    "t,G,H",    0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,                I32     },
1923
{"mtc1",    "t,S",        0x44800000, 0xffe007ff,        COD|RD_t|WR_S|FP_S,        0,                I1        },
1924
{"mtc1",    "t,G",        0x44800000, 0xffe007ff,        COD|RD_t|WR_S|FP_S,        0,                I1        },
1925
{"mthc1",   "t,S",        0x44e00000, 0xffe007ff,        COD|RD_t|WR_S|FP_D,        0,                I33        },
1926
{"mthc1",   "t,G",        0x44e00000, 0xffe007ff,        COD|RD_t|WR_S|FP_D,        0,                I33        },
1927
/* mtc2 is at the bottom of the table.  */
1928
/* mthc2 is at the bottom of the table.  */
1929
/* mtc3 is at the bottom of the table.  */
1930
{"mtdr",    "t,G",        0x7080003d, 0xffe007ff,        COD|RD_t|WR_C0,                0,                N5        },
1931
{"mthi",    "s",        0x00000011, 0xfc1fffff,        RD_s|WR_HI,                0,                I1        },
1932
{"mthi",    "s,7",        0x00000011, 0xfc1fe7ff, RD_s|WR_HI,                0,                D32        },
1933
{"mtlo",    "s",        0x00000013, 0xfc1fffff,        RD_s|WR_LO,                0,                I1        },
1934
{"mtlo",    "s,7",        0x00000013, 0xfc1fe7ff, RD_s|WR_LO,                0,                D32        },
1935
{"mtlhx",   "s",        0x00000053, 0xfc1fffff,        RD_s|MOD_HILO,                0,                SMT        },
1936
{"mttc0",   "t,G",        0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0,                MT32        },
1937
{"mttc0",   "t,+D",        0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0,                MT32        },
1938
{"mttc0",   "t,G,H",        0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0,                MT32        },
1939
{"mttc1",   "t,S",        0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0,                MT32        },
1940
{"mttc1",   "t,G",        0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0,                MT32        },
1941
{"mttc2",   "t,g",        0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0,                MT32        },
1942
{"mttacx",  "t",        0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t,                0,                MT32        },
1943
{"mttacx",  "t,&",        0x41801021, 0xffe09fff, TRAP|WR_a|RD_t,                0,                MT32        },
1944
{"mttdsp",  "t",        0x41808021, 0xffe0ffff, TRAP|RD_t,                0,                MT32        },
1945
{"mttgpr",  "t,d",        0x41800020, 0xffe007ff, TRAP|WR_d|RD_t,                0,                MT32        },
1946
{"mtthc1",  "t,S",        0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0,                MT32        },
1947
{"mtthc1",  "t,G",        0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0,                MT32        },
1948
{"mtthc2",  "t,g",        0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0,                MT32        },
1949
{"mtthi",   "t",        0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t,                0,                MT32        },
1950
{"mtthi",   "t,&",        0x41800821, 0xffe09fff, TRAP|WR_a|RD_t,                0,                MT32        },
1951
{"mttlo",   "t",        0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t,                0,                MT32        },
1952
{"mttlo",   "t,&",        0x41800021, 0xffe09fff, TRAP|WR_a|RD_t,                0,                MT32        },
1953
{"mttr",    "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t,                0,                MT32        },
1954
{"mul.d",   "D,V,T",        0x46200002, 0xffe0003f,        WR_D|RD_S|RD_T|FP_D,        0,                I1        },
1955
{"mul.s",   "D,V,T",        0x46000002, 0xffe0003f,        WR_D|RD_S|RD_T|FP_S,        0,                I1        },
1956
{"mul.ob",  "X,Y,Q",        0x78000030, 0xfc20003f,        WR_D|RD_S|RD_T|FP_D,        0,                MX|SB1        },
1957
{"mul.ob",  "D,S,T",        0x4ac00030, 0xffe0003f,        WR_D|RD_S|RD_T,                0,                N54        },
1958
{"mul.ob",  "D,S,T[e]",        0x48000030, 0xfe20003f,        WR_D|RD_S|RD_T,                0,                N54        },
1959
{"mul.ob",  "D,S,k",        0x4bc00030, 0xffe0003f,        WR_D|RD_S|RD_T,                0,                N54        },
1960
{"mul.ps",  "D,V,T",        0x46c00002, 0xffe0003f,        WR_D|RD_S|RD_T|FP_D,        0,                I5|I33        },
1961
{"mul.qh",  "X,Y,Q",        0x78200030, 0xfc20003f,        WR_D|RD_S|RD_T|FP_D,        0,                MX        },
1962
{"mul",     "d,v,t",    0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,                I32|P3|N55},
1963
{"mul",     "d,s,t",        0x00000058, 0xfc0007ff,        RD_s|RD_t|WR_HILO|WR_d,        0,                N54        },
1964
{"mul",     "d,v,t",        0,    (int) M_MUL,        INSN_MACRO,                0,                I1        },
1965
{"mul",     "d,v,I",        0,    (int) M_MUL_I,        INSN_MACRO,                0,                I1        },
1966
{"mula.ob", "Y,Q",        0x78000033, 0xfc2007ff,        RD_S|RD_T|FP_D,                WR_MACC,        MX|SB1        },
1967
{"mula.ob", "S,T",        0x4ac00033, 0xffe007ff,        WR_CC|RD_S|RD_T,        0,                N54        },
1968
{"mula.ob", "S,T[e]",        0x48000033, 0xfe2007ff,        WR_CC|RD_S|RD_T,        0,                N54        },
1969
{"mula.ob", "S,k",        0x4bc00033, 0xffe007ff,        WR_CC|RD_S|RD_T,        0,                N54        },
1970
{"mula.qh", "Y,Q",        0x78200033, 0xfc2007ff,        RD_S|RD_T|FP_D,                WR_MACC,        MX        },
1971
{"mulhi",   "d,s,t",        0x00000258, 0xfc0007ff,        RD_s|RD_t|WR_HILO|WR_d,        0,                N5        },
1972
{"mulhiu",  "d,s,t",        0x00000259, 0xfc0007ff,        RD_s|RD_t|WR_HILO|WR_d,        0,                N5        },
1973
{"mull.ob", "Y,Q",        0x78000433, 0xfc2007ff,        RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1        },
1974
{"mull.ob", "S,T",        0x4ac00433, 0xffe007ff,        WR_CC|RD_S|RD_T,        0,                N54        },
1975
{"mull.ob", "S,T[e]",        0x48000433, 0xfe2007ff,        WR_CC|RD_S|RD_T,        0,                N54        },
1976
{"mull.ob", "S,k",        0x4bc00433, 0xffe007ff,        WR_CC|RD_S|RD_T,        0,                N54        },
1977
{"mull.qh", "Y,Q",        0x78200433, 0xfc2007ff,        RD_S|RD_T|FP_D,                WR_MACC,        MX        },
1978
{"mulo",    "d,v,t",        0,    (int) M_MULO,        INSN_MACRO,                0,                I1        },
1979
{"mulo",    "d,v,I",        0,    (int) M_MULO_I,        INSN_MACRO,                0,                I1        },
1980
{"mulou",   "d,v,t",        0,    (int) M_MULOU,        INSN_MACRO,                0,                I1        },
1981
{"mulou",   "d,v,I",        0,    (int) M_MULOU_I,        INSN_MACRO,                0,                I1        },
1982
{"mulr.ps", "D,S,T",        0x46c0001a, 0xffe0003f,        WR_D|RD_S|RD_T|FP_D,        0,                M3D        },
1983
{"muls",    "d,s,t",        0x000000d8, 0xfc0007ff,        RD_s|RD_t|WR_HILO|WR_d,        0,                N5        },
1984
{"mulsu",   "d,s,t",        0x000000d9, 0xfc0007ff,        RD_s|RD_t|WR_HILO|WR_d,        0,                N5        },
1985
{"mulshi",  "d,s,t",        0x000002d8, 0xfc0007ff,        RD_s|RD_t|WR_HILO|WR_d,        0,                N5        },
1986
{"mulshiu", "d,s,t",        0x000002d9, 0xfc0007ff,        RD_s|RD_t|WR_HILO|WR_d,        0,                N5        },
1987
{"muls.ob", "Y,Q",        0x78000032, 0xfc2007ff,        RD_S|RD_T|FP_D,                WR_MACC,        MX|SB1        },
1988
{"muls.ob", "S,T",        0x4ac00032, 0xffe007ff,        WR_CC|RD_S|RD_T,        0,                N54        },
1989
{"muls.ob", "S,T[e]",        0x48000032, 0xfe2007ff,        WR_CC|RD_S|RD_T,        0,                N54        },
1990
{"muls.ob", "S,k",        0x4bc00032, 0xffe007ff,        WR_CC|RD_S|RD_T,        0,                N54        },
1991
{"muls.qh", "Y,Q",        0x78200032, 0xfc2007ff,        RD_S|RD_T|FP_D,                WR_MACC,        MX        },
1992
{"mulsl.ob", "Y,Q",        0x78000432, 0xfc2007ff,        RD_S|RD_T|FP_D,                WR_MACC,        MX|SB1        },
1993
{"mulsl.ob", "S,T",        0x4ac00432, 0xffe007ff,        WR_CC|RD_S|RD_T,        0,                N54        },
1994
{"mulsl.ob", "S,T[e]",        0x48000432, 0xfe2007ff,        WR_CC|RD_S|RD_T,        0,                N54        },
1995
{"mulsl.ob", "S,k",        0x4bc00432, 0xffe007ff,        WR_CC|RD_S|RD_T,        0,                N54        },
1996
{"mulsl.qh", "Y,Q",        0x78200432, 0xfc2007ff,        RD_S|RD_T|FP_D,                WR_MACC,        MX        },
1997
{"mult",    "s,t",      0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,                I1        },
1998
{"mult",    "7,s,t",        0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D33        },
1999
{"mult",    "d,s,t",    0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,                G1        },
2000
{"multp",   "s,t",        0x00000459, 0xfc00ffff,        RD_s|RD_t|MOD_HILO,        0,                SMT        },
2001
{"multu",   "s,t",      0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,                I1        },
2002
{"multu",   "7,s,t",        0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D33        },
2003
{"multu",   "d,s,t",    0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,                G1        },
2004
{"mulu",    "d,s,t",        0x00000059, 0xfc0007ff,        RD_s|RD_t|WR_HILO|WR_d,        0,                N5        },
2005
{"neg",     "d,w",        0x00000022, 0xffe007ff,        WR_d|RD_t,                0,                I1        }, /* sub 0 */
2006
{"negu",    "d,w",        0x00000023, 0xffe007ff,        WR_d|RD_t,                0,                I1        }, /* subu 0 */
2007
{"neg.d",   "D,V",        0x46200007, 0xffff003f,        WR_D|RD_S|FP_D,                0,                I1        },
2008
{"neg.s",   "D,V",        0x46000007, 0xffff003f,        WR_D|RD_S|FP_S,                0,                I1        },
2009
{"neg.ps",  "D,V",        0x46c00007, 0xffff003f,        WR_D|RD_S|FP_D,                0,                I5|I33        },
2010
{"nmadd.d", "D,R,S,T",        0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,                I4|I33        },
2011
{"nmadd.s", "D,R,S,T",        0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,                I4|I33        },
2012
{"nmadd.ps","D,R,S,T",        0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,                I5|I33        },
2013
{"nmsub.d", "D,R,S,T",        0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,                I4|I33        },
2014
{"nmsub.s", "D,R,S,T",        0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,                I4|I33        },
2015
{"nmsub.ps","D,R,S,T",        0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,                I5|I33        },
2016
/* nop is at the start of the table.  */
2017
{"nor",     "d,v,t",        0x00000027, 0xfc0007ff,        WR_d|RD_s|RD_t,                0,                I1        },
2018
{"nor",     "t,r,I",        0,    (int) M_NOR_I,        INSN_MACRO,                0,                I1        },
2019
{"nor.ob",  "X,Y,Q",        0x7800000f, 0xfc20003f,        WR_D|RD_S|RD_T|FP_D,        0,                MX|SB1        },
2020
{"nor.ob",  "D,S,T",        0x4ac0000f, 0xffe0003f,        WR_D|RD_S|RD_T,                0,                N54        },
2021
{"nor.ob",  "D,S,T[e]",        0x4800000f, 0xfe20003f,        WR_D|RD_S|RD_T,                0,                N54        },
2022
{"nor.ob",  "D,S,k",        0x4bc0000f, 0xffe0003f,        WR_D|RD_S|RD_T,                0,                N54        },
2023
{"nor.qh",  "X,Y,Q",        0x7820000f, 0xfc20003f,        WR_D|RD_S|RD_T|FP_D,        0,                MX        },
2024
{"not",     "d,v",        0x00000027, 0xfc1f07ff,        WR_d|RD_s|RD_t,                0,                I1        },/*nor d,s,0*/
2025
{"or",      "d,v,t",        0x00000025, 0xfc0007ff,        WR_d|RD_s|RD_t,                0,                I1        },
2026
{"or",      "t,r,I",        0,    (int) M_OR_I,        INSN_MACRO,                0,                I1        },
2027
{"or.ob",   "X,Y,Q",        0x7800000e, 0xfc20003f,        WR_D|RD_S|RD_T|FP_D,        0,                MX|SB1        },
2028
{"or.ob",   "D,S,T",        0x4ac0000e, 0xffe0003f,        WR_D|RD_S|RD_T,                0,                N54        },
2029
{"or.ob",   "D,S,T[e]",        0x4800000e, 0xfe20003f,        WR_D|RD_S|RD_T,                0,                N54        },
2030
{"or.ob",   "D,S,k",        0x4bc0000e, 0xffe0003f,        WR_D|RD_S|RD_T,                0,                N54        },
2031
{"or.qh",   "X,Y,Q",        0x7820000e, 0xfc20003f,        WR_D|RD_S|RD_T|FP_D,        0,                MX        },
2032
{"ori",     "t,r,i",        0x34000000, 0xfc000000,        WR_t|RD_s,                0,                I1        },
2033
{"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f,        WR_D|RD_S|RD_T|FP_D,        0,                SB1        },
2034
{"pabsdiffc.ob", "Y,Q",        0x78000035, 0xfc2007ff,        RD_S|RD_T|FP_D,                WR_MACC,        SB1        },
2035
{"pavg.ob", "X,Y,Q",        0x78000008, 0xfc20003f,        WR_D|RD_S|RD_T|FP_D,        0,                SB1        },
2036
{"pickf.ob", "X,Y,Q",        0x78000002, 0xfc20003f,        WR_D|RD_S|RD_T|FP_D,        0,                MX|SB1        },
2037
{"pickf.ob", "D,S,T",        0x4ac00002, 0xffe0003f,        WR_D|RD_S|RD_T,                0,                N54        },
2038
{"pickf.ob", "D,S,T[e]",0x48000002, 0xfe20003f,        WR_D|RD_S|RD_T,                0,                N54        },
2039
{"pickf.ob", "D,S,k",        0x4bc00002, 0xffe0003f,        WR_D|RD_S|RD_T,                0,                N54        },
2040
{"pickf.qh", "X,Y,Q",        0x78200002, 0xfc20003f,        WR_D|RD_S|RD_T|FP_D,        0,                MX        },
2041
{"pickt.ob", "X,Y,Q",        0x78000003, 0xfc20003f,        WR_D|RD_S|RD_T|FP_D,        0,                MX|SB1        },
2042
{"pickt.ob", "D,S,T",        0x4ac00003, 0xffe0003f,        WR_D|RD_S|RD_T,                0,                N54        },
2043
{"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f,        WR_D|RD_S|RD_T,                0,                N54        },
2044
{"pickt.ob", "D,S,k",        0x4bc00003, 0xffe0003f,        WR_D|RD_S|RD_T,                0,                N54        },
2045
{"pickt.qh", "X,Y,Q",        0x78200003, 0xfc20003f,        WR_D|RD_S|RD_T|FP_D,        0,                MX        },
2046
{"pll.ps",  "D,V,T",        0x46c0002c, 0xffe0003f,        WR_D|RD_S|RD_T|FP_D,        0,                I5|I33        },
2047
{"plu.ps",  "D,V,T",        0x46c0002d, 0xffe0003f,        WR_D|RD_S|RD_T|FP_D,        0,                I5|I33        },
2048
  /* pref and prefx are at the start of the table.  */
2049
{"pul.ps",  "D,V,T",        0x46c0002e, 0xffe0003f,        WR_D|RD_S|RD_T|FP_D,        0,                I5|I33        },
2050
{"puu.ps",  "D,V,T",        0x46c0002f, 0xffe0003f,        WR_D|RD_S|RD_T|FP_D,        0,                I5|I33        },
2051
{"pperm",   "s,t",        0x70000481, 0xfc00ffff,        MOD_HILO|RD_s|RD_t,        0,                SMT        },
2052
{"rach.ob", "X",        0x7a00003f, 0xfffff83f,        WR_D|FP_D,                RD_MACC,        MX|SB1        },
2053
{"rach.ob", "D",        0x4a00003f, 0xfffff83f,        WR_D,                        0,                N54        },
2054
{"rach.qh", "X",        0x7a20003f, 0xfffff83f,        WR_D|FP_D,                RD_MACC,        MX        },
2055
{"racl.ob", "X",        0x7800003f, 0xfffff83f,        WR_D|FP_D,                RD_MACC,        MX|SB1        },
2056
{"racl.ob", "D",        0x4800003f, 0xfffff83f,        WR_D,                        0,                N54        },
2057
{"racl.qh", "X",        0x7820003f, 0xfffff83f,        WR_D|FP_D,                RD_MACC,        MX        },
2058
{"racm.ob", "X",        0x7900003f, 0xfffff83f,        WR_D|FP_D,                RD_MACC,        MX|SB1        },
2059
{"racm.ob", "D",        0x4900003f, 0xfffff83f,        WR_D,                        0,                N54        },
2060
{"racm.qh", "X",        0x7920003f, 0xfffff83f,        WR_D|FP_D,                RD_MACC,        MX        },
2061
{"recip.d", "D,S",        0x46200015, 0xffff003f, WR_D|RD_S|FP_D,                0,                I4|I33        },
2062
{"recip.ps","D,S",        0x46c00015, 0xffff003f, WR_D|RD_S|FP_D,                0,                SB1        },
2063
{"recip.s", "D,S",        0x46000015, 0xffff003f, WR_D|RD_S|FP_S,                0,                I4|I33        },
2064
{"recip1.d",  "D,S",        0x4620001d, 0xffff003f,        WR_D|RD_S|FP_D,                0,                M3D        },
2065
{"recip1.ps", "D,S",        0x46c0001d, 0xffff003f,        WR_D|RD_S|FP_S,                0,                M3D        },
2066
{"recip1.s",  "D,S",        0x4600001d, 0xffff003f,        WR_D|RD_S|FP_S,                0,                M3D        },
2067
{"recip2.d",  "D,S,T",        0x4620001c, 0xffe0003f,        WR_D|RD_S|RD_T|FP_D,        0,                M3D        },
2068
{"recip2.ps", "D,S,T",        0x46c0001c, 0xffe0003f,        WR_D|RD_S|RD_T|FP_S,        0,                M3D        },
2069
{"recip2.s",  "D,S,T",        0x4600001c, 0xffe0003f,        WR_D|RD_S|RD_T|FP_S,        0,                M3D        },
2070
{"rem",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,                I1        },
2071
{"rem",     "d,v,t",        0,    (int) M_REM_3,        INSN_MACRO,                0,                I1        },
2072
{"rem",     "d,v,I",        0,    (int) M_REM_3I,        INSN_MACRO,                0,                I1        },
2073
{"remu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,                I1        },
2074
{"remu",    "d,v,t",        0,    (int) M_REMU_3,        INSN_MACRO,                0,                I1        },
2075
{"remu",    "d,v,I",        0,    (int) M_REMU_3I,        INSN_MACRO,                0,                I1        },
2076
{"rdhwr",   "t,K",        0x7c00003b, 0xffe007ff, WR_t,                        0,                I33        },
2077
{"rdpgpr",  "d,w",        0x41400000, 0xffe007ff, WR_d,                        0,                I33        },
2078
{"rfe",     "",                0x42000010, 0xffffffff,        0,                        0,                I1|T3        },
2079
{"rnas.qh", "X,Q",        0x78200025, 0xfc20f83f,        WR_D|RD_T|FP_D,                RD_MACC,        MX        },
2080
{"rnau.ob", "X,Q",        0x78000021, 0xfc20f83f,        WR_D|RD_T|FP_D,                RD_MACC,        MX|SB1        },
2081
{"rnau.qh", "X,Q",        0x78200021, 0xfc20f83f,        WR_D|RD_T|FP_D,                RD_MACC,        MX        },
2082
{"rnes.qh", "X,Q",        0x78200026, 0xfc20f83f,        WR_D|RD_T|FP_D,                RD_MACC,        MX        },
2083
{"rneu.ob", "X,Q",        0x78000022, 0xfc20f83f,        WR_D|RD_T|FP_D,                RD_MACC,        MX|SB1        },
2084
{"rneu.qh", "X,Q",        0x78200022, 0xfc20f83f,        WR_D|RD_T|FP_D,                RD_MACC,        MX        },
2085
{"rol",     "d,v,t",        0,    (int) M_ROL,        INSN_MACRO,                0,                I1        },
2086
{"rol",     "d,v,I",        0,    (int) M_ROL_I,        INSN_MACRO,                0,                I1        },
2087
{"ror",     "d,v,t",        0,    (int) M_ROR,        INSN_MACRO,                0,                I1        },
2088
{"ror",     "d,v,I",        0,    (int) M_ROR_I,        INSN_MACRO,                0,                I1        },
2089
{"ror",            "d,w,<",        0x00200002, 0xffe0003f,        WR_d|RD_t,                0,                N5|I33|SMT },
2090
{"rorv",    "d,t,s",        0x00000046, 0xfc0007ff,        RD_t|RD_s|WR_d,                0,                N5|I33|SMT },
2091
{"rotl",    "d,v,t",        0,    (int) M_ROL,        INSN_MACRO,                0,                I33|SMT        },
2092
{"rotl",    "d,v,I",        0,    (int) M_ROL_I,        INSN_MACRO,                0,                I33|SMT        },
2093
{"rotr",    "d,v,t",        0,    (int) M_ROR,        INSN_MACRO,                0,                I33|SMT        },
2094
{"rotr",    "d,v,I",        0,    (int) M_ROR_I,        INSN_MACRO,                0,                I33|SMT        },
2095
{"rotrv",   "d,t,s",        0x00000046, 0xfc0007ff,        RD_t|RD_s|WR_d,                0,                I33|SMT        },
2096
{"round.l.d", "D,S",        0x46200008, 0xffff003f, WR_D|RD_S|FP_D,                0,                I3|I33        },
2097
{"round.l.s", "D,S",        0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D,        0,                I3|I33        },
2098
{"round.w.d", "D,S",        0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D,        0,                I2        },
2099
{"round.w.s", "D,S",        0x4600000c, 0xffff003f, WR_D|RD_S|FP_S,                0,                I2        },
2100
{"rsqrt.d", "D,S",        0x46200016, 0xffff003f, WR_D|RD_S|FP_D,                0,                I4|I33        },
2101
{"rsqrt.ps","D,S",        0x46c00016, 0xffff003f, WR_D|RD_S|FP_D,                0,                SB1        },
2102
{"rsqrt.s", "D,S",        0x46000016, 0xffff003f, WR_D|RD_S|FP_S,                0,                I4|I33        },
2103
{"rsqrt1.d",  "D,S",        0x4620001e, 0xffff003f,        WR_D|RD_S|FP_D,                0,                M3D        },
2104
{"rsqrt1.ps", "D,S",        0x46c0001e, 0xffff003f,        WR_D|RD_S|FP_S,                0,                M3D        },
2105
{"rsqrt1.s",  "D,S",        0x4600001e, 0xffff003f,        WR_D|RD_S|FP_S,                0,                M3D        },
2106
{"rsqrt2.d",  "D,S,T",        0x4620001f, 0xffe0003f,        WR_D|RD_S|RD_T|FP_D,        0,                M3D        },
2107
{"rsqrt2.ps", "D,S,T",        0x46c0001f, 0xffe0003f,        WR_D|RD_S|RD_T|FP_S,        0,                M3D        },
2108
{"rsqrt2.s",  "D,S,T",        0x4600001f, 0xffe0003f,        WR_D|RD_S|RD_T|FP_S,        0,                M3D        },
2109
{"rzs.qh",  "X,Q",        0x78200024, 0xfc20f83f,        WR_D|RD_T|FP_D,                RD_MACC,        MX        },
2110
{"rzu.ob",  "X,Q",        0x78000020, 0xfc20f83f,        WR_D|RD_T|FP_D,                RD_MACC,        MX|SB1        },
2111
{"rzu.ob",  "D,k",        0x4bc00020, 0xffe0f83f,        WR_D|RD_S|RD_T,                0,                N54        },
2112
{"rzu.qh",  "X,Q",        0x78200020, 0xfc20f83f,        WR_D|RD_T|FP_D,                RD_MACC,        MX        },
2113
{"sb",      "t,o(b)",        0xa0000000, 0xfc000000,        SM|RD_t|RD_b,                0,                I1        },
2114
{"sb",      "t,A(b)",        0,    (int) M_SB_AB,        INSN_MACRO,                0,                I1        },
2115
{"sc",            "t,o(b)",        0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,        0,                I2        },
2116
{"sc",            "t,A(b)",        0,    (int) M_SC_AB,        INSN_MACRO,                0,                I2        },
2117
{"scd",            "t,o(b)",        0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,        0,                I3        },
2118
{"scd",            "t,A(b)",        0,    (int) M_SCD_AB,        INSN_MACRO,                0,                I3        },
2119
{"sd",            "t,o(b)",        0xfc000000, 0xfc000000,        SM|RD_t|RD_b,                0,                I3        },
2120
{"sd",      "t,o(b)",        0,    (int) M_SD_OB,        INSN_MACRO,                0,                I1        },
2121
{"sd",      "t,A(b)",        0,    (int) M_SD_AB,        INSN_MACRO,                0,                I1        },
2122
{"sdbbp",   "",                0x0000000e, 0xffffffff,        TRAP,                   0,                G2        },
2123
{"sdbbp",   "c",        0x0000000e, 0xfc00ffff,        TRAP,                        0,                G2        },
2124
{"sdbbp",   "c,q",        0x0000000e, 0xfc00003f,        TRAP,                        0,                G2        },
2125
{"sdbbp",   "",         0x7000003f, 0xffffffff, TRAP,                   0,                I32     },
2126
{"sdbbp",   "B",        0x7000003f, 0xfc00003f, TRAP,                   0,                I32     },
2127
{"sdc1",    "T,o(b)",        0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,        0,                I2        },
2128
{"sdc1",    "E,o(b)",        0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,        0,                I2        },
2129
{"sdc1",    "T,A(b)",        0,    (int) M_SDC1_AB,        INSN_MACRO,                0,                I2        },
2130
{"sdc1",    "E,A(b)",        0,    (int) M_SDC1_AB,        INSN_MACRO,                0,                I2        },
2131
{"sdc2",    "E,o(b)",        0xf8000000, 0xfc000000, SM|RD_C2|RD_b,                0,                I2        },
2132
{"sdc2",    "E,A(b)",        0,    (int) M_SDC2_AB,        INSN_MACRO,                0,                I2        },
2133
{"sdc3",    "E,o(b)",        0xfc000000, 0xfc000000, SM|RD_C3|RD_b,                0,                I2        },
2134
{"sdc3",    "E,A(b)",        0,    (int) M_SDC3_AB,        INSN_MACRO,                0,                I2        },
2135
{"s.d",     "T,o(b)",        0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,        0,                I2        },
2136
{"s.d",     "T,o(b)",        0,    (int) M_S_DOB,        INSN_MACRO,                0,                I1        },
2137
{"s.d",     "T,A(b)",        0,    (int) M_S_DAB,        INSN_MACRO,                0,                I1        },
2138
{"sdl",     "t,o(b)",        0xb0000000, 0xfc000000,        SM|RD_t|RD_b,                0,                I3        },
2139
{"sdl",     "t,A(b)",        0,    (int) M_SDL_AB,        INSN_MACRO,                0,                I3        },
2140
{"sdr",     "t,o(b)",        0xb4000000, 0xfc000000,        SM|RD_t|RD_b,                0,                I3        },
2141
{"sdr",     "t,A(b)",        0,    (int) M_SDR_AB,        INSN_MACRO,                0,                I3        },
2142
{"sdxc1",   "S,t(b)",   0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D,        0,                I4|I33        },
2143
{"seb",     "d,w",        0x7c000420, 0xffe007ff,        WR_d|RD_t,                0,                I33        },
2144
{"seh",     "d,w",        0x7c000620, 0xffe007ff,        WR_d|RD_t,                0,                I33        },
2145
{"selsl",   "d,v,t",        0x00000005, 0xfc0007ff,        WR_d|RD_s|RD_t,                0,                L1        },
2146
{"selsr",   "d,v,t",        0x00000001, 0xfc0007ff,        WR_d|RD_s|RD_t,                0,                L1        },
2147
{"seq",     "d,v,t",        0,    (int) M_SEQ,        INSN_MACRO,                0,                I1        },
2148
{"seq",     "d,v,I",        0,    (int) M_SEQ_I,        INSN_MACRO,                0,                I1        },
2149
{"sge",     "d,v,t",        0,    (int) M_SGE,        INSN_MACRO,                0,                I1        },
2150
{"sge",     "d,v,I",        0,    (int) M_SGE_I,        INSN_MACRO,                0,                I1        },
2151
{"sgeu",    "d,v,t",        0,    (int) M_SGEU,        INSN_MACRO,                0,                I1        },
2152
{"sgeu",    "d,v,I",        0,    (int) M_SGEU_I,        INSN_MACRO,                0,                I1        },
2153
{"sgt",     "d,v,t",        0,    (int) M_SGT,        INSN_MACRO,                0,                I1        },
2154
{"sgt",     "d,v,I",        0,    (int) M_SGT_I,        INSN_MACRO,                0,                I1        },
2155
{"sgtu",    "d,v,t",        0,    (int) M_SGTU,        INSN_MACRO,                0,                I1        },
2156
{"sgtu",    "d,v,I",        0,    (int) M_SGTU_I,        INSN_MACRO,                0,                I1        },
2157
{"sh",      "t,o(b)",        0xa4000000, 0xfc000000,        SM|RD_t|RD_b,                0,                I1        },
2158
{"sh",      "t,A(b)",        0,    (int) M_SH_AB,        INSN_MACRO,                0,                I1        },
2159
{"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,        0,                MX        },
2160
{"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,        0,                MX|SB1        },
2161
{"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T,         0,                N54        },
2162
{"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,        0,                MX        },
2163
{"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,        0,                MX|SB1        },
2164
{"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T,         0,                N54        },
2165
{"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,        0,                MX        },
2166
{"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,        0,                MX|SB1        },
2167
{"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T,         0,                N54        },
2168
{"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,        0,                MX        },
2169
{"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T,         0,                N54        },
2170
{"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,        0,                MX        },
2171
{"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,        0,                MX        },
2172
{"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,        0,                MX|SB1        },
2173
{"sle",     "d,v,t",        0,    (int) M_SLE,        INSN_MACRO,                0,                I1        },
2174
{"sle",     "d,v,I",        0,    (int) M_SLE_I,        INSN_MACRO,                0,                I1        },
2175
{"sleu",    "d,v,t",        0,    (int) M_SLEU,        INSN_MACRO,                0,                I1        },
2176
{"sleu",    "d,v,I",        0,    (int) M_SLEU_I,        INSN_MACRO,                0,                I1        },
2177
{"sllv",    "d,t,s",        0x00000004, 0xfc0007ff,        WR_d|RD_t|RD_s,                0,                I1        },
2178
{"sll",     "d,w,s",        0x00000004, 0xfc0007ff,        WR_d|RD_t|RD_s,                0,                I1        }, /* sllv */
2179
{"sll",     "d,w,<",        0x00000000, 0xffe0003f,        WR_d|RD_t,                0,                I1        },
2180
{"sll.ob",  "X,Y,Q",        0x78000010, 0xfc20003f,        WR_D|RD_S|RD_T|FP_D,        0,                MX|SB1        },
2181
{"sll.ob",  "D,S,T[e]",        0x48000010, 0xfe20003f,        WR_D|RD_S|RD_T,                0,                N54        },
2182
{"sll.ob",  "D,S,k",        0x4bc00010, 0xffe0003f,        WR_D|RD_S|RD_T,                0,                N54        },
2183
{"sll.qh",  "X,Y,Q",        0x78200010, 0xfc20003f,        WR_D|RD_S|RD_T|FP_D,        0,                MX        },
2184
{"slt",     "d,v,t",        0x0000002a, 0xfc0007ff,        WR_d|RD_s|RD_t,                0,                I1        },
2185
{"slt",     "d,v,I",        0,    (int) M_SLT_I,        INSN_MACRO,                0,                I1        },
2186
{"slti",    "t,r,j",        0x28000000, 0xfc000000,        WR_t|RD_s,                0,                I1        },
2187
{"sltiu",   "t,r,j",        0x2c000000, 0xfc000000,        WR_t|RD_s,                0,                I1        },
2188
{"sltu",    "d,v,t",        0x0000002b, 0xfc0007ff,        WR_d|RD_s|RD_t,                0,                I1        },
2189
{"sltu",    "d,v,I",        0,    (int) M_SLTU_I,        INSN_MACRO,                0,                I1        },
2190
{"sne",     "d,v,t",        0,    (int) M_SNE,        INSN_MACRO,                0,                I1        },
2191
{"sne",     "d,v,I",        0,    (int) M_SNE_I,        INSN_MACRO,                0,                I1        },
2192
{"sqrt.d",  "D,S",        0x46200004, 0xffff003f, WR_D|RD_S|FP_D,                0,                I2        },
2193
{"sqrt.s",  "D,S",        0x46000004, 0xffff003f, WR_D|RD_S|FP_S,                0,                I2        },
2194
{"sqrt.ps", "D,S",        0x46c00004, 0xffff003f, WR_D|RD_S|FP_D,                0,                SB1        },
2195
{"srav",    "d,t,s",        0x00000007, 0xfc0007ff,        WR_d|RD_t|RD_s,                0,                I1        },
2196
{"sra",     "d,w,s",        0x00000007, 0xfc0007ff,        WR_d|RD_t|RD_s,                0,                I1        }, /* srav */
2197
{"sra",     "d,w,<",        0x00000003, 0xffe0003f,        WR_d|RD_t,                0,                I1        },
2198
{"sra.qh",  "X,Y,Q",        0x78200013, 0xfc20003f,        WR_D|RD_S|RD_T|FP_D,        0,                MX        },
2199
{"srlv",    "d,t,s",        0x00000006, 0xfc0007ff,        WR_d|RD_t|RD_s,                0,                I1        },
2200
{"srl",     "d,w,s",        0x00000006, 0xfc0007ff,        WR_d|RD_t|RD_s,                0,                I1        }, /* srlv */
2201
{"srl",     "d,w,<",        0x00000002, 0xffe0003f,        WR_d|RD_t,                0,                I1        },
2202
{"srl.ob",  "X,Y,Q",        0x78000012, 0xfc20003f,        WR_D|RD_S|RD_T|FP_D,        0,                MX|SB1        },
2203
{"srl.ob",  "D,S,T[e]",        0x48000012, 0xfe20003f,        WR_D|RD_S|RD_T,                0,                N54        },
2204
{"srl.ob",  "D,S,k",        0x4bc00012, 0xffe0003f,        WR_D|RD_S|RD_T,                0,                N54        },
2205
{"srl.qh",  "X,Y,Q",        0x78200012, 0xfc20003f,        WR_D|RD_S|RD_T|FP_D,        0,                MX        },
2206
/* ssnop is at the start of the table.  */
2207
{"standby", "",         0x42000021, 0xffffffff,        0,                        0,                V1        },
2208
{"sub",     "d,v,t",        0x00000022, 0xfc0007ff,        WR_d|RD_s|RD_t,                0,                I1        },
2209
{"sub",     "d,v,I",        0,    (int) M_SUB_I,        INSN_MACRO,                0,                I1        },
2210
{"sub.d",   "D,V,T",        0x46200001, 0xffe0003f,        WR_D|RD_S|RD_T|FP_D,        0,                I1        },
2211
{"sub.s",   "D,V,T",        0x46000001, 0xffe0003f,        WR_D|RD_S|RD_T|FP_S,        0,                I1        },
2212
{"sub.ob",  "X,Y,Q",        0x7800000a, 0xfc20003f,        WR_D|RD_S|RD_T|FP_D,        0,                MX|SB1        },
2213
{"sub.ob",  "D,S,T",        0x4ac0000a, 0xffe0003f,        WR_D|RD_S|RD_T,                0,                N54        },
2214
{"sub.ob",  "D,S,T[e]",        0x4800000a, 0xfe20003f,        WR_D|RD_S|RD_T,                0,                N54        },
2215
{"sub.ob",  "D,S,k",        0x4bc0000a, 0xffe0003f,        WR_D|RD_S|RD_T,                0,                N54        },
2216
{"sub.ps",  "D,V,T",        0x46c00001, 0xffe0003f,        WR_D|RD_S|RD_T|FP_D,        0,                I5|I33        },
2217
{"sub.qh",  "X,Y,Q",        0x7820000a, 0xfc20003f,        WR_D|RD_S|RD_T|FP_D,        0,                MX        },
2218
{"suba.ob", "Y,Q",        0x78000036, 0xfc2007ff,        RD_S|RD_T|FP_D,                WR_MACC,        MX|SB1        },
2219
{"suba.qh", "Y,Q",        0x78200036, 0xfc2007ff,        RD_S|RD_T|FP_D,                WR_MACC,        MX        },
2220
{"subl.ob", "Y,Q",        0x78000436, 0xfc2007ff,        RD_S|RD_T|FP_D,                WR_MACC,        MX|SB1        },
2221
{"subl.qh", "Y,Q",        0x78200436, 0xfc2007ff,        RD_S|RD_T|FP_D,                WR_MACC,        MX        },
2222
{"subu",    "d,v,t",        0x00000023, 0xfc0007ff,        WR_d|RD_s|RD_t,                0,                I1        },
2223
{"subu",    "d,v,I",        0,    (int) M_SUBU_I,        INSN_MACRO,                0,                I1        },
2224
{"suspend", "",         0x42000022, 0xffffffff,        0,                        0,                V1        },
2225
{"suxc1",   "S,t(b)",   0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b,        0,                I5|I33|N55},
2226
{"sw",      "t,o(b)",        0xac000000, 0xfc000000,        SM|RD_t|RD_b,                0,                I1        },
2227
{"sw",      "t,A(b)",        0,    (int) M_SW_AB,        INSN_MACRO,                0,                I1        },
2228
{"swc0",    "E,o(b)",        0xe0000000, 0xfc000000,        SM|RD_C0|RD_b,                0,                I1        },
2229
{"swc0",    "E,A(b)",        0,    (int) M_SWC0_AB,        INSN_MACRO,                0,                I1        },
2230
{"swc1",    "T,o(b)",        0xe4000000, 0xfc000000,        SM|RD_T|RD_b|FP_S,        0,                I1        },
2231
{"swc1",    "E,o(b)",        0xe4000000, 0xfc000000,        SM|RD_T|RD_b|FP_S,        0,                I1        },
2232
{"swc1",    "T,A(b)",        0,    (int) M_SWC1_AB,        INSN_MACRO,                0,                I1        },
2233
{"swc1",    "E,A(b)",        0,    (int) M_SWC1_AB,        INSN_MACRO,                0,                I1        },
2234
{"s.s",     "T,o(b)",        0xe4000000, 0xfc000000,        SM|RD_T|RD_b|FP_S,        0,                I1        }, /* swc1 */
2235
{"s.s",     "T,A(b)",        0,    (int) M_SWC1_AB,        INSN_MACRO,                0,                I1        },
2236
{"swc2",    "E,o(b)",        0xe8000000, 0xfc000000,        SM|RD_C2|RD_b,                0,                I1        },
2237
{"swc2",    "E,A(b)",        0,    (int) M_SWC2_AB,        INSN_MACRO,                0,                I1        },
2238
{"swc3",    "E,o(b)",        0xec000000, 0xfc000000,        SM|RD_C3|RD_b,                0,                I1        },
2239
{"swc3",    "E,A(b)",        0,    (int) M_SWC3_AB,        INSN_MACRO,                0,                I1        },
2240
{"swl",     "t,o(b)",        0xa8000000, 0xfc000000,        SM|RD_t|RD_b,                0,                I1        },
2241
{"swl",     "t,A(b)",        0,    (int) M_SWL_AB,        INSN_MACRO,                0,                I1        },
2242
{"scache",  "t,o(b)",        0xa8000000, 0xfc000000,        RD_t|RD_b,                0,                I2        }, /* same */
2243
{"scache",  "t,A(b)",        0,    (int) M_SWL_AB,        INSN_MACRO,                0,                I2        }, /* as swl */
2244
{"swr",     "t,o(b)",        0xb8000000, 0xfc000000,        SM|RD_t|RD_b,                0,                I1        },
2245
{"swr",     "t,A(b)",        0,    (int) M_SWR_AB,        INSN_MACRO,                0,                I1        },
2246
{"invalidate", "t,o(b)",0xb8000000, 0xfc000000,        RD_t|RD_b,                0,                I2        }, /* same */
2247
{"invalidate", "t,A(b)",0,    (int) M_SWR_AB,        INSN_MACRO,                0,                I2        }, /* as swr */
2248
{"swxc1",   "S,t(b)",   0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S,        0,                I4|I33        },
2249
{"sync",    "",                0x0000000f, 0xffffffff,        INSN_SYNC,                0,                I2|G1        },
2250
{"sync.p",  "",                0x0000040f, 0xffffffff,        INSN_SYNC,                0,                I2        },
2251
{"sync.l",  "",                0x0000000f, 0xffffffff,        INSN_SYNC,                0,                I2        },
2252
{"synci",   "o(b)",        0x041f0000, 0xfc1f0000,        SM|RD_b,                0,                I33        },
2253
{"syscall", "",                0x0000000c, 0xffffffff,        TRAP,                        0,                I1        },
2254
{"syscall", "B",        0x0000000c, 0xfc00003f,        TRAP,                        0,                I1        },
2255
{"teqi",    "s,j",        0x040c0000, 0xfc1f0000, RD_s|TRAP,                0,                I2        },
2256
{"teq",            "s,t",        0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP,                0,                I2        },
2257
{"teq",            "s,t,q",        0x00000034, 0xfc00003f, RD_s|RD_t|TRAP,                0,                I2        },
2258
{"teq",     "s,j",        0x040c0000, 0xfc1f0000, RD_s|TRAP,                0,                I2        }, /* teqi */
2259
{"teq",     "s,I",        0,    (int) M_TEQ_I,        INSN_MACRO,                0,                I2        },
2260
{"tgei",    "s,j",        0x04080000, 0xfc1f0000, RD_s|TRAP,                0,                I2        },
2261
{"tge",            "s,t",        0x00000030, 0xfc00ffff,        RD_s|RD_t|TRAP,                0,                I2        },
2262
{"tge",            "s,t,q",        0x00000030, 0xfc00003f,        RD_s|RD_t|TRAP,                0,                I2        },
2263
{"tge",     "s,j",        0x04080000, 0xfc1f0000, RD_s|TRAP,                0,                I2        }, /* tgei */
2264
{"tge",            "s,I",        0,    (int) M_TGE_I,    INSN_MACRO,                0,                I2        },
2265
{"tgeiu",   "s,j",        0x04090000, 0xfc1f0000, RD_s|TRAP,                0,                I2        },
2266
{"tgeu",    "s,t",        0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP,                0,                I2        },
2267
{"tgeu",    "s,t,q",        0x00000031, 0xfc00003f, RD_s|RD_t|TRAP,                0,                I2        },
2268
{"tgeu",    "s,j",        0x04090000, 0xfc1f0000, RD_s|TRAP,                0,                I2        }, /* tgeiu */
2269
{"tgeu",    "s,I",        0,    (int) M_TGEU_I,        INSN_MACRO,                0,                I2        },
2270
{"tlbp",    "",         0x42000008, 0xffffffff, INSN_TLB,               0,                I1           },
2271
{"tlbr",    "",         0x42000001, 0xffffffff, INSN_TLB,               0,                I1           },
2272
{"tlbwi",   "",         0x42000002, 0xffffffff, INSN_TLB,               0,                I1           },
2273
{"tlbwr",   "",         0x42000006, 0xffffffff, INSN_TLB,               0,                I1           },
2274
{"tlti",    "s,j",        0x040a0000, 0xfc1f0000,        RD_s|TRAP,                0,                I2        },
2275
{"tlt",     "s,t",        0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP,                0,                I2        },
2276
{"tlt",     "s,t,q",        0x00000032, 0xfc00003f, RD_s|RD_t|TRAP,                0,                I2        },
2277
{"tlt",     "s,j",        0x040a0000, 0xfc1f0000,        RD_s|TRAP,                0,                I2        }, /* tlti */
2278
{"tlt",     "s,I",        0,    (int) M_TLT_I,        INSN_MACRO,                0,                I2        },
2279
{"tltiu",   "s,j",        0x040b0000, 0xfc1f0000, RD_s|TRAP,                0,                I2        },
2280
{"tltu",    "s,t",        0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP,                0,                I2        },
2281
{"tltu",    "s,t,q",        0x00000033, 0xfc00003f, RD_s|RD_t|TRAP,                0,                I2        },
2282
{"tltu",    "s,j",        0x040b0000, 0xfc1f0000, RD_s|TRAP,                0,                I2        }, /* tltiu */
2283
{"tltu",    "s,I",        0,    (int) M_TLTU_I,        INSN_MACRO,                0,                I2        },
2284
{"tnei",    "s,j",        0x040e0000, 0xfc1f0000, RD_s|TRAP,                0,                I2        },
2285
{"tne",     "s,t",        0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP,                0,                I2        },
2286
{"tne",     "s,t,q",        0x00000036, 0xfc00003f, RD_s|RD_t|TRAP,                0,                I2        },
2287
{"tne",     "s,j",        0x040e0000, 0xfc1f0000, RD_s|TRAP,                0,                I2        }, /* tnei */
2288
{"tne",     "s,I",        0,    (int) M_TNE_I,        INSN_MACRO,                0,                I2        },
2289
{"trunc.l.d", "D,S",        0x46200009, 0xffff003f, WR_D|RD_S|FP_D,                0,                I3|I33        },
2290
{"trunc.l.s", "D,S",        0x46000009, 0xffff003f,        WR_D|RD_S|FP_S|FP_D,        0,                I3|I33        },
2291
{"trunc.w.d", "D,S",        0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,        0,                I2        },
2292
{"trunc.w.d", "D,S,x",        0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,        0,                I2        },
2293
{"trunc.w.d", "D,S,t",        0,    (int) M_TRUNCWD,        INSN_MACRO,                0,                I1        },
2294
{"trunc.w.s", "D,S",        0x4600000d, 0xffff003f,        WR_D|RD_S|FP_S,                0,                I2        },
2295
{"trunc.w.s", "D,S,x",        0x4600000d, 0xffff003f,        WR_D|RD_S|FP_S,                0,                I2        },
2296
{"trunc.w.s", "D,S,t",        0,    (int) M_TRUNCWS,        INSN_MACRO,                0,                I1        },
2297
{"uld",     "t,o(b)",        0,    (int) M_ULD,        INSN_MACRO,                0,                I3        },
2298
{"uld",     "t,A(b)",        0,    (int) M_ULD_A,        INSN_MACRO,                0,                I3        },
2299
{"ulh",     "t,o(b)",        0,    (int) M_ULH,        INSN_MACRO,                0,                I1        },
2300
{"ulh",     "t,A(b)",        0,    (int) M_ULH_A,        INSN_MACRO,                0,                I1        },
2301
{"ulhu",    "t,o(b)",        0,    (int) M_ULHU,        INSN_MACRO,                0,                I1        },
2302
{"ulhu",    "t,A(b)",        0,    (int) M_ULHU_A,        INSN_MACRO,                0,                I1        },
2303
{"ulw",     "t,o(b)",        0,    (int) M_ULW,        INSN_MACRO,                0,                I1        },
2304
{"ulw",     "t,A(b)",        0,    (int) M_ULW_A,        INSN_MACRO,                0,                I1        },
2305
{"usd",     "t,o(b)",        0,    (int) M_USD,        INSN_MACRO,                0,                I3        },
2306
{"usd",     "t,A(b)",        0,    (int) M_USD_A,        INSN_MACRO,                0,                I3        },
2307
{"ush",     "t,o(b)",        0,    (int) M_USH,        INSN_MACRO,                0,                I1        },
2308
{"ush",     "t,A(b)",        0,    (int) M_USH_A,        INSN_MACRO,                0,                I1        },
2309
{"usw",     "t,o(b)",        0,    (int) M_USW,        INSN_MACRO,                0,                I1        },
2310
{"usw",     "t,A(b)",        0,    (int) M_USW_A,        INSN_MACRO,                0,                I1        },
2311
{"wach.ob", "Y",        0x7a00003e, 0xffff07ff,        RD_S|FP_D,                WR_MACC,        MX|SB1        },
2312
{"wach.ob", "S",        0x4a00003e, 0xffff07ff,        RD_S,                        0,                N54        },
2313
{"wach.qh", "Y",        0x7a20003e, 0xffff07ff,        RD_S|FP_D,                WR_MACC,        MX        },
2314
{"wacl.ob", "Y,Z",        0x7800003e, 0xffe007ff,        RD_S|RD_T|FP_D,                WR_MACC,        MX|SB1        },
2315
{"wacl.ob", "S,T",        0x4800003e, 0xffe007ff,        RD_S|RD_T,                0,                N54        },
2316
{"wacl.qh", "Y,Z",        0x7820003e, 0xffe007ff,        RD_S|RD_T|FP_D,                WR_MACC,        MX        },
2317
{"wait",    "",         0x42000020, 0xffffffff, TRAP,                   0,                I3|I32        },
2318
{"wait",    "J",        0x42000020, 0xfe00003f, TRAP,                   0,                I32|N55        },
2319
{"waiti",   "",                0x42000020, 0xffffffff,        TRAP,                        0,                L1        },
2320
{"wrpgpr",  "d,w",        0x41c00000, 0xffe007ff, RD_t,                        0,                I33        },
2321
{"wsbh",    "d,w",        0x7c0000a0, 0xffe007ff,        WR_d|RD_t,                0,                I33        },
2322
{"xor",     "d,v,t",        0x00000026, 0xfc0007ff,        WR_d|RD_s|RD_t,                0,                I1        },
2323
{"xor",     "t,r,I",        0,    (int) M_XOR_I,        INSN_MACRO,                0,                I1        },
2324
{"xor.ob",  "X,Y,Q",        0x7800000d, 0xfc20003f,        WR_D|RD_S|RD_T|FP_D,        0,                MX|SB1        },
2325
{"xor.ob",  "D,S,T",        0x4ac0000d, 0xffe0003f,        WR_D|RD_S|RD_T,                0,                N54        },
2326
{"xor.ob",  "D,S,T[e]",        0x4800000d, 0xfe20003f,        WR_D|RD_S|RD_T,                0,                N54        },
2327
{"xor.ob",  "D,S,k",        0x4bc0000d, 0xffe0003f,        WR_D|RD_S|RD_T,                0,                N54        },
2328
{"xor.qh",  "X,Y,Q",        0x7820000d, 0xfc20003f,        WR_D|RD_S|RD_T|FP_D,        0,                MX        },
2329
{"xori",    "t,r,i",        0x38000000, 0xfc000000,        WR_t|RD_s,                0,                I1        },
2330
{"yield",   "s",        0x7c000009, 0xfc1fffff, TRAP|RD_s,                0,                MT32        },
2331
{"yield",   "d,s",        0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s,                0,                MT32        },
2332

    
2333
/* User Defined Instruction.  */
2334
{"udi0",     "s,t,d,+1",0x70000010, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2335
{"udi0",     "s,t,+2",        0x70000010, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2336
{"udi0",     "s,+3",        0x70000010, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2337
{"udi0",     "+4",        0x70000010, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2338
{"udi1",     "s,t,d,+1",0x70000011, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2339
{"udi1",     "s,t,+2",        0x70000011, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2340
{"udi1",     "s,+3",        0x70000011, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2341
{"udi1",     "+4",        0x70000011, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2342
{"udi2",     "s,t,d,+1",0x70000012, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2343
{"udi2",     "s,t,+2",        0x70000012, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2344
{"udi2",     "s,+3",        0x70000012, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2345
{"udi2",     "+4",        0x70000012, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2346
{"udi3",     "s,t,d,+1",0x70000013, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2347
{"udi3",     "s,t,+2",        0x70000013, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2348
{"udi3",     "s,+3",        0x70000013, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2349
{"udi3",     "+4",        0x70000013, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2350
{"udi4",     "s,t,d,+1",0x70000014, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2351
{"udi4",     "s,t,+2",        0x70000014, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2352
{"udi4",     "s,+3",        0x70000014, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2353
{"udi4",     "+4",        0x70000014, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2354
{"udi5",     "s,t,d,+1",0x70000015, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2355
{"udi5",     "s,t,+2",        0x70000015, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2356
{"udi5",     "s,+3",        0x70000015, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2357
{"udi5",     "+4",        0x70000015, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2358
{"udi6",     "s,t,d,+1",0x70000016, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2359
{"udi6",     "s,t,+2",        0x70000016, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2360
{"udi6",     "s,+3",        0x70000016, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2361
{"udi6",     "+4",        0x70000016, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2362
{"udi7",     "s,t,d,+1",0x70000017, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2363
{"udi7",     "s,t,+2",        0x70000017, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2364
{"udi7",     "s,+3",        0x70000017, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2365
{"udi7",     "+4",        0x70000017, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2366
{"udi8",     "s,t,d,+1",0x70000018, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2367
{"udi8",     "s,t,+2",        0x70000018, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2368
{"udi8",     "s,+3",        0x70000018, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2369
{"udi8",     "+4",        0x70000018, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2370
{"udi9",     "s,t,d,+1",0x70000019, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2371
{"udi9",      "s,t,+2",        0x70000019, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2372
{"udi9",     "s,+3",        0x70000019, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2373
{"udi9",     "+4",        0x70000019, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2374
{"udi10",    "s,t,d,+1",0x7000001a, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2375
{"udi10",    "s,t,+2",        0x7000001a, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2376
{"udi10",    "s,+3",        0x7000001a, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2377
{"udi10",    "+4",        0x7000001a, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2378
{"udi11",    "s,t,d,+1",0x7000001b, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2379
{"udi11",    "s,t,+2",        0x7000001b, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2380
{"udi11",    "s,+3",        0x7000001b, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2381
{"udi11",    "+4",        0x7000001b, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2382
{"udi12",    "s,t,d,+1",0x7000001c, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2383
{"udi12",    "s,t,+2",        0x7000001c, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2384
{"udi12",    "s,+3",        0x7000001c, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2385
{"udi12",    "+4",        0x7000001c, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2386
{"udi13",    "s,t,d,+1",0x7000001d, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2387
{"udi13",    "s,t,+2",        0x7000001d, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2388
{"udi13",    "s,+3",        0x7000001d, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2389
{"udi13",    "+4",        0x7000001d, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2390
{"udi14",    "s,t,d,+1",0x7000001e, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2391
{"udi14",    "s,t,+2",        0x7000001e, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2392
{"udi14",    "s,+3",        0x7000001e, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2393
{"udi14",    "+4",        0x7000001e, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2394
{"udi15",    "s,t,d,+1",0x7000001f, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2395
{"udi15",    "s,t,+2",        0x7000001f, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2396
{"udi15",    "s,+3",        0x7000001f, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2397
{"udi15",    "+4",        0x7000001f, 0xfc00003f,        WR_d|RD_s|RD_t,                0,                I33        },
2398

    
2399
/* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
2400
   instructions so they are here for the latters to take precedence.  */
2401
{"bc2f",    "p",        0x49000000, 0xffff0000,        CBD|RD_CC,                0,                I1        },
2402
{"bc2f",    "N,p",        0x49000000, 0xffe30000,        CBD|RD_CC,                0,                I32        },
2403
{"bc2fl",   "p",        0x49020000, 0xffff0000,        CBL|RD_CC,                0,                I2|T3        },
2404
{"bc2fl",   "N,p",        0x49020000, 0xffe30000,        CBL|RD_CC,                0,                I32        },
2405
{"bc2t",    "p",        0x49010000, 0xffff0000,        CBD|RD_CC,                0,                I1        },
2406
{"bc2t",    "N,p",        0x49010000, 0xffe30000,        CBD|RD_CC,                0,                I32        },
2407
{"bc2tl",   "p",        0x49030000, 0xffff0000,        CBL|RD_CC,                0,                I2|T3        },
2408
{"bc2tl",   "N,p",        0x49030000, 0xffe30000,        CBL|RD_CC,                0,                I32        },
2409
{"cfc2",    "t,G",        0x48400000, 0xffe007ff,        LCD|WR_t|RD_C2,                0,                I1        },
2410
{"ctc2",    "t,G",        0x48c00000, 0xffe007ff,        COD|RD_t|WR_CC,                0,                I1        },
2411
{"dmfc2",   "t,G",        0x48200000, 0xffe007ff,        LCD|WR_t|RD_C2,                0,                I3        },
2412
{"dmfc2",   "t,G,H",        0x48200000, 0xffe007f8,        LCD|WR_t|RD_C2,                0,                I64        },
2413
{"dmtc2",   "t,G",        0x48a00000, 0xffe007ff,        COD|RD_t|WR_C2|WR_CC,        0,                I3        },
2414
{"dmtc2",   "t,G,H",        0x48a00000, 0xffe007f8,        COD|RD_t|WR_C2|WR_CC,        0,                I64        },
2415
{"mfc2",    "t,G",        0x48000000, 0xffe007ff,        LCD|WR_t|RD_C2,                0,                I1        },
2416
{"mfc2",    "t,G,H",        0x48000000, 0xffe007f8,        LCD|WR_t|RD_C2,                0,                I32        },
2417
{"mfhc2",   "t,G",        0x48600000, 0xffe007ff,        LCD|WR_t|RD_C2,                0,                I33        },
2418
{"mfhc2",   "t,G,H",        0x48600000, 0xffe007f8,        LCD|WR_t|RD_C2,                0,                I33        },
2419
{"mfhc2",   "t,i",        0x48600000, 0xffe00000,        LCD|WR_t|RD_C2,                0,                I33        },
2420
{"mtc2",    "t,G",        0x48800000, 0xffe007ff,        COD|RD_t|WR_C2|WR_CC,        0,                I1        },
2421
{"mtc2",    "t,G,H",        0x48800000, 0xffe007f8,        COD|RD_t|WR_C2|WR_CC,        0,                I32        },
2422
{"mthc2",   "t,G",        0x48e00000, 0xffe007ff,        COD|RD_t|WR_C2|WR_CC,        0,                I33        },
2423
{"mthc2",   "t,G,H",        0x48e00000, 0xffe007f8,        COD|RD_t|WR_C2|WR_CC,        0,                I33        },
2424
{"mthc2",   "t,i",        0x48e00000, 0xffe00000,        COD|RD_t|WR_C2|WR_CC,        0,                I33        },
2425

    
2426
/* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X
2427
   instructions, so they are here for the latters to take precedence.  */
2428
{"bc3f",    "p",        0x4d000000, 0xffff0000,        CBD|RD_CC,                0,                I1        },
2429
{"bc3fl",   "p",        0x4d020000, 0xffff0000,        CBL|RD_CC,                0,                I2|T3        },
2430
{"bc3t",    "p",        0x4d010000, 0xffff0000,        CBD|RD_CC,                0,                I1        },
2431
{"bc3tl",   "p",        0x4d030000, 0xffff0000,        CBL|RD_CC,                0,                I2|T3        },
2432
{"cfc3",    "t,G",        0x4c400000, 0xffe007ff,        LCD|WR_t|RD_C3,                0,                I1        },
2433
{"ctc3",    "t,G",        0x4cc00000, 0xffe007ff,        COD|RD_t|WR_CC,                0,                I1        },
2434
{"dmfc3",   "t,G",        0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3,         0,                I3        },
2435
{"dmtc3",   "t,G",        0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,        0,                I3        },
2436
{"mfc3",    "t,G",        0x4c000000, 0xffe007ff,        LCD|WR_t|RD_C3,                0,                I1        },
2437
{"mfc3",    "t,G,H",    0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3,         0,                I32     },
2438
{"mtc3",    "t,G",        0x4c800000, 0xffe007ff,        COD|RD_t|WR_C3|WR_CC,        0,                I1        },
2439
{"mtc3",    "t,G,H",    0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC,   0,                I32     },
2440

    
2441
/* No hazard protection on coprocessor instructions--they shouldn't
2442
   change the state of the processor and if they do it's up to the
2443
   user to put in nops as necessary.  These are at the end so that the
2444
   disassembler recognizes more specific versions first.  */
2445
{"c0",      "C",        0x42000000, 0xfe000000,        0,                        0,                I1        },
2446
{"c1",      "C",        0x46000000, 0xfe000000,        0,                        0,                I1        },
2447
{"c2",      "C",        0x4a000000, 0xfe000000,        0,                        0,                I1        },
2448
{"c3",      "C",        0x4e000000, 0xfe000000,        0,                        0,                I1        },
2449
{"cop0",     "C",        0,    (int) M_COP0,        INSN_MACRO,                0,                I1        },
2450
{"cop1",     "C",        0,    (int) M_COP1,        INSN_MACRO,                0,                I1        },
2451
{"cop2",     "C",        0,    (int) M_COP2,        INSN_MACRO,                0,                I1        },
2452
{"cop3",     "C",        0,    (int) M_COP3,        INSN_MACRO,                0,                I1        },
2453
  /* Conflicts with the 4650's "mul" instruction.  Nobody's using the
2454
     4010 any more, so move this insn out of the way.  If the object
2455
     format gave us more info, we could do this right.  */
2456
{"addciu",  "t,r,j",        0x70000000, 0xfc000000,        WR_t|RD_s,                0,                L1        },
2457
/* MIPS DSP ASE */
2458
{"absq_s.ph", "d,t",        0x7c000252, 0xffe007ff, WR_d|RD_t,                0,                D32        },
2459
{"absq_s.pw", "d,t",        0x7c000456, 0xffe007ff, WR_d|RD_t,                0,                D64        },
2460
{"absq_s.qh", "d,t",        0x7c000256, 0xffe007ff, WR_d|RD_t,                0,                D64        },
2461
{"absq_s.w", "d,t",        0x7c000452, 0xffe007ff, WR_d|RD_t,                0,                D32        },
2462
{"addq.ph", "d,s,t",        0x7c000290, 0xfc0007ff, WR_d|RD_s|RD_t,                0,                D32        },
2463
{"addq.pw", "d,s,t",        0x7c000494, 0xfc0007ff, WR_d|RD_s|RD_t,                0,                D64        },
2464
{"addq.qh", "d,s,t",        0x7c000294, 0xfc0007ff, WR_d|RD_s|RD_t,                0,                D64        },
2465
{"addq_s.ph", "d,s,t",        0x7c000390, 0xfc0007ff, WR_d|RD_s|RD_t,                0,                D32        },
2466
{"addq_s.pw", "d,s,t",        0x7c000594, 0xfc0007ff, WR_d|RD_s|RD_t,                0,                D64        },
2467
{"addq_s.qh", "d,s,t",        0x7c000394, 0xfc0007ff, WR_d|RD_s|RD_t,                0,                D64        },
2468
{"addq_s.w", "d,s,t",        0x7c000590, 0xfc0007ff, WR_d|RD_s|RD_t,                0,                D32        },
2469
{"addsc",   "d,s,t",        0x7c000410, 0xfc0007ff, WR_d|RD_s|RD_t,                0,                D32        },
2470
{"addu.ob", "d,s,t",        0x7c000014, 0xfc0007ff, WR_d|RD_s|RD_t,                0,                D64        },
2471
{"addu.qb", "d,s,t",        0x7c000010, 0xfc0007ff, WR_d|RD_s|RD_t,                0,                D32        },
2472
{"addu_s.ob", "d,s,t",        0x7c000114, 0xfc0007ff, WR_d|RD_s|RD_t,                0,                D64        },
2473
{"addu_s.qb", "d,s,t",        0x7c000110, 0xfc0007ff, WR_d|RD_s|RD_t,                0,                D32        },
2474
{"addwc",   "d,s,t",        0x7c000450, 0xfc0007ff, WR_d|RD_s|RD_t,                0,                D32        },
2475
{"bitrev",  "d,t",        0x7c0006d2, 0xffe007ff, WR_d|RD_t,                0,                D32        },
2476
{"bposge32", "p",        0x041c0000, 0xffff0000, CBD,                        0,                D32        },
2477
{"bposge64", "p",        0x041d0000, 0xffff0000, CBD,                        0,                D64        },
2478
{"cmp.eq.ph", "s,t",        0x7c000211, 0xfc00ffff, RD_s|RD_t,                0,                D32        },
2479
{"cmp.eq.pw", "s,t",        0x7c000415, 0xfc00ffff, RD_s|RD_t,                0,                D64        },
2480
{"cmp.eq.qh", "s,t",        0x7c000215, 0xfc00ffff, RD_s|RD_t,                0,                D64        },
2481
{"cmpgu.eq.ob", "d,s,t", 0x7c000115, 0xfc0007ff, WR_d|RD_s|RD_t,        0,                D64        },
2482
{"cmpgu.eq.qb", "d,s,t", 0x7c000111, 0xfc0007ff, WR_d|RD_s|RD_t,        0,                D32        },
2483
{"cmpgu.le.ob", "d,s,t", 0x7c000195, 0xfc0007ff, WR_d|RD_s|RD_t,        0,                D64        },
2484
{"cmpgu.le.qb", "d,s,t", 0x7c000191, 0xfc0007ff, WR_d|RD_s|RD_t,        0,                D32        },
2485
{"cmpgu.lt.ob", "d,s,t", 0x7c000155, 0xfc0007ff, WR_d|RD_s|RD_t,        0,                D64        },
2486
{"cmpgu.lt.qb", "d,s,t", 0x7c000151, 0xfc0007ff, WR_d|RD_s|RD_t,        0,                D32        },
2487
{"cmp.le.ph", "s,t",        0x7c000291, 0xfc00ffff, RD_s|RD_t,                0,                D32        },
2488
{"cmp.le.pw", "s,t",        0x7c000495, 0xfc00ffff, RD_s|RD_t,                0,                D64        },
2489
{"cmp.le.qh", "s,t",        0x7c000295, 0xfc00ffff, RD_s|RD_t,                0,                D64        },
2490
{"cmp.lt.ph", "s,t",        0x7c000251, 0xfc00ffff, RD_s|RD_t,                0,                D32        },
2491
{"cmp.lt.pw", "s,t",        0x7c000455, 0xfc00ffff, RD_s|RD_t,                0,                D64        },
2492
{"cmp.lt.qh", "s,t",        0x7c000255, 0xfc00ffff, RD_s|RD_t,                0,                D64        },
2493
{"cmpu.eq.ob", "s,t",        0x7c000015, 0xfc00ffff, RD_s|RD_t,                0,                D64        },
2494
{"cmpu.eq.qb", "s,t",        0x7c000011, 0xfc00ffff, RD_s|RD_t,                0,                D32        },
2495
{"cmpu.le.ob", "s,t",        0x7c000095, 0xfc00ffff, RD_s|RD_t,                0,                D64        },
2496
{"cmpu.le.qb", "s,t",        0x7c000091, 0xfc00ffff, RD_s|RD_t,                0,                D32        },
2497
{"cmpu.lt.ob", "s,t",        0x7c000055, 0xfc00ffff, RD_s|RD_t,                0,                D64        },
2498
{"cmpu.lt.qb", "s,t",        0x7c000051, 0xfc00ffff, RD_s|RD_t,                0,                D32        },
2499
{"dextpdp", "t,7,6",        0x7c0002bc, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA,        0,                D64        },
2500
{"dextpdpv", "t,7,s",        0x7c0002fc, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0,                D64        },
2501
{"dextp",   "t,7,6",        0x7c0000bc, 0xfc00e7ff, WR_t|RD_a,                0,                D64        },
2502
{"dextpv",  "t,7,s",        0x7c0000fc, 0xfc00e7ff, WR_t|RD_a|RD_s,                0,                D64        },
2503
{"dextr.l", "t,7,6",        0x7c00043c, 0xfc00e7ff, WR_t|RD_a,                0,                D64        },
2504
{"dextr_r.l", "t,7,6",        0x7c00053c, 0xfc00e7ff, WR_t|RD_a,                0,                D64        },
2505
{"dextr_rs.l", "t,7,6",        0x7c0005bc, 0xfc00e7ff, WR_t|RD_a,                0,                D64        },
2506
{"dextr_rs.w", "t,7,6",        0x7c0001bc, 0xfc00e7ff, WR_t|RD_a,                0,                D64        },
2507
{"dextr_r.w", "t,7,6",        0x7c00013c, 0xfc00e7ff, WR_t|RD_a,                0,                D64        },
2508
{"dextr_s.h", "t,7,6",        0x7c0003bc, 0xfc00e7ff, WR_t|RD_a,                0,                D64        },
2509
{"dextrv.l", "t,7,s",        0x7c00047c, 0xfc00e7ff, WR_t|RD_a|RD_s,                0,                D64        },
2510
{"dextrv_r.l", "t,7,s",        0x7c00057c, 0xfc00e7ff, WR_t|RD_a|RD_s,                0,                D64        },
2511
{"dextrv_rs.l", "t,7,s", 0x7c0005fc, 0xfc00e7ff, WR_t|RD_a|RD_s,        0,                D64        },
2512
{"dextrv_rs.w", "t,7,s", 0x7c0001fc, 0xfc00e7ff, WR_t|RD_a|RD_s,        0,                D64        },
2513
{"dextrv_r.w", "t,7,s",        0x7c00017c, 0xfc00e7ff, WR_t|RD_a|RD_s,                0,                D64        },
2514
{"dextrv_s.h", "t,7,s",        0x7c0003fc, 0xfc00e7ff, WR_t|RD_a|RD_s,                0,                D64        },
2515
{"dextrv.w", "t,7,s",        0x7c00007c, 0xfc00e7ff, WR_t|RD_a|RD_s,                0,                D64        },
2516
{"dextr.w", "t,7,6",        0x7c00003c, 0xfc00e7ff, WR_t|RD_a,                0,                D64        },
2517
{"dinsv",   "t,s",        0x7c00000d, 0xfc00ffff, WR_t|RD_s,                0,                D64        },
2518
{"dmadd",   "7,s,t",        0x7c000674, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,                D64        },
2519
{"dmaddu",  "7,s,t",        0x7c000774, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,                D64        },
2520
{"dmsub",   "7,s,t",        0x7c0006f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,                D64        },
2521
{"dmsubu",  "7,s,t",        0x7c0007f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,                D64        },
2522
{"dmthlip", "s,7",        0x7c0007fc, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA,        0,                D64        },
2523
{"dpaq_sa.l.pw", "7,s,t", 0x7c000334, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,                D64        },
2524
{"dpaq_sa.l.w", "7,s,t", 0x7c000330, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,                D32        },
2525
{"dpaq_s.w.ph", "7,s,t", 0x7c000130, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,                D32        },
2526
{"dpaq_s.w.qh", "7,s,t", 0x7c000134, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,                D64        },
2527
{"dpau.h.obl", "7,s,t",        0x7c0000f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,                D64        },
2528
{"dpau.h.obr", "7,s,t",        0x7c0001f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,                D64        },
2529
{"dpau.h.qbl", "7,s,t",        0x7c0000f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,                D32        },
2530
{"dpau.h.qbr", "7,s,t",        0x7c0001f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,                D32        },
2531
{"dpsq_sa.l.pw", "7,s,t", 0x7c000374, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,                D64        },
2532
{"dpsq_sa.l.w", "7,s,t", 0x7c000370, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,                D32        },
2533
{"dpsq_s.w.ph", "7,s,t", 0x7c000170, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,                D32        },
2534
{"dpsq_s.w.qh", "7,s,t", 0x7c000174, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,                D64        },
2535
{"dpsu.h.obl", "7,s,t",        0x7c0002f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,                D64        },
2536
{"dpsu.h.obr", "7,s,t",        0x7c0003f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,                D64        },
2537
{"dpsu.h.qbl", "7,s,t",        0x7c0002f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,                D32        },
2538
{"dpsu.h.qbr", "7,s,t",        0x7c0003f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,                D32        },
2539
{"dshilo",  "7,:",        0x7c0006bc, 0xfc07e7ff, MOD_a,                        0,                D64        },
2540
{"dshilov", "7,s",        0x7c0006fc, 0xfc1fe7ff, MOD_a|RD_s,                0,                D64        },
2541
{"extpdp",  "t,7,6",        0x7c0002b8, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA,        0,                D32        },
2542
{"extpdpv", "t,7,s",        0x7c0002f8, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0,                D32        },
2543
{"extp"