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/* Print SPARC instructions.
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   Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
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   2000, 2002 Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
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#include <stdlib.h>
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#include "dis-asm.h"
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/* The SPARC opcode table (and other related data) is defined in
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   the opcodes library in sparc-opc.c.  If you change anything here, make
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   sure you fix up that file, and vice versa.  */
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 /* FIXME-someday: perhaps the ,a's and such should be embedded in the
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    instruction's name rather than the args.  This would make gas faster, pinsn
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    slower, but would mess up some macros a bit.  xoxorich. */
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/* List of instruction sets variations.
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   These values are such that each element is either a superset of a
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   preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P
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   returns non-zero.
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   The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
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   Don't change this without updating sparc-opc.c.  */
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enum sparc_opcode_arch_val {
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  SPARC_OPCODE_ARCH_V6 = 0,
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  SPARC_OPCODE_ARCH_V7,
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  SPARC_OPCODE_ARCH_V8,
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  SPARC_OPCODE_ARCH_SPARCLET,
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  SPARC_OPCODE_ARCH_SPARCLITE,
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  /* v9 variants must appear last */
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  SPARC_OPCODE_ARCH_V9,
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  SPARC_OPCODE_ARCH_V9A, /* v9 with ultrasparc additions */
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  SPARC_OPCODE_ARCH_V9B, /* v9 with ultrasparc and cheetah additions */
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  SPARC_OPCODE_ARCH_BAD /* error return from sparc_opcode_lookup_arch */
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};
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/* The highest architecture in the table.  */
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#define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1)
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/* Given an enum sparc_opcode_arch_val, return the bitmask to use in
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   insn encoding/decoding.  */
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#define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch))
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/* Given a valid sparc_opcode_arch_val, return non-zero if it's v9.  */
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#define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9)
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/* Table of cpu variants.  */
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struct sparc_opcode_arch {
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  const char *name;
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  /* Mask of sparc_opcode_arch_val's supported.
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     EG: For v7 this would be
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     (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)).
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     These are short's because sparc_opcode.architecture is.  */
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  short supported;
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};
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extern const struct sparc_opcode_arch sparc_opcode_archs[];
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/* Given architecture name, look up it's sparc_opcode_arch_val value.  */
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extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch
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  PARAMS ((const char *));
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/* Return the bitmask of supported architectures for ARCH.  */
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#define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported)
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/* Non-zero if ARCH1 conflicts with ARCH2.
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   IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa.  */
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#define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \
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(((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
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  != SPARC_OPCODE_SUPPORTED (ARCH1)) \
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 && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
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     != SPARC_OPCODE_SUPPORTED (ARCH2)))
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/* Structure of an opcode table entry.  */
88

    
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struct sparc_opcode {
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  const char *name;
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  unsigned long match;        /* Bits that must be set. */
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  unsigned long lose;        /* Bits that must not be set. */
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  const char *args;
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  /* This was called "delayed" in versions before the flags. */
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  char flags;
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  short architecture;        /* Bitmask of sparc_opcode_arch_val's.  */
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};
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#define        F_DELAYED        1        /* Delayed branch */
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#define        F_ALIAS                2        /* Alias for a "real" instruction */
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#define        F_UNBR                4        /* Unconditional branch */
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#define        F_CONDBR        8        /* Conditional branch */
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#define        F_JSR                16        /* Subroutine call */
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#define F_FLOAT                32        /* Floating point instruction (not a branch) */
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#define F_FBR                64        /* Floating point branch */
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/* FIXME: Add F_ANACHRONISTIC flag for v9.  */
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/*
109

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All sparc opcodes are 32 bits, except for the `set' instruction (really a
111
macro), which is 64 bits. It is handled as a special case.
112

113
The match component is a mask saying which bits must match a particular
114
opcode in order for an instruction to be an instance of that opcode.
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116
The args component is a string containing one character for each operand of the
117
instruction.
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Kinds of operands:
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        #        Number used by optimizer.        It is ignored.
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        1        rs1 register.
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        2        rs2 register.
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        d        rd register.
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        e        frs1 floating point register.
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        v        frs1 floating point register (double/even).
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        V        frs1 floating point register (quad/multiple of 4).
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        f        frs2 floating point register.
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        B        frs2 floating point register (double/even).
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        R        frs2 floating point register (quad/multiple of 4).
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        g        frsd floating point register.
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        H        frsd floating point register (double/even).
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        J        frsd floating point register (quad/multiple of 4).
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        b        crs1 coprocessor register
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        c        crs2 coprocessor register
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        D        crsd coprocessor register
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        m        alternate space register (asr) in rd
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        M        alternate space register (asr) in rs1
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        h        22 high bits.
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        X        5 bit unsigned immediate
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        Y        6 bit unsigned immediate
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        3        SIAM mode (3 bits). (v9b)
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        K        MEMBAR mask (7 bits). (v9)
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        j        10 bit Immediate. (v9)
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        I        11 bit Immediate. (v9)
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        i        13 bit Immediate.
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        n        22 bit immediate.
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        k        2+14 bit PC relative immediate. (v9)
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        G        19 bit PC relative immediate. (v9)
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        l        22 bit PC relative immediate.
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        L        30 bit PC relative immediate.
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        a        Annul.        The annul bit is set.
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        A        Alternate address space. Stored as 8 bits.
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        C        Coprocessor state register.
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        F        floating point state register.
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        p        Processor state register.
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        N        Branch predict clear ",pn" (v9)
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        T        Branch predict set ",pt" (v9)
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        z        %icc. (v9)
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        Z        %xcc. (v9)
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        q        Floating point queue.
161
        r        Single register that is both rs1 and rd.
162
        O        Single register that is both rs2 and rd.
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        Q        Coprocessor queue.
164
        S        Special case.
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        t        Trap base register.
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        w        Window invalid mask register.
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        y        Y register.
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        u        sparclet coprocessor registers in rd position
169
        U        sparclet coprocessor registers in rs1 position
170
        E        %ccr. (v9)
171
        s        %fprs. (v9)
172
        P        %pc.  (v9)
173
        W        %tick.        (v9)
174
        o        %asi. (v9)
175
        6        %fcc0. (v9)
176
        7        %fcc1. (v9)
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        8        %fcc2. (v9)
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        9        %fcc3. (v9)
179
        !        Privileged Register in rd (v9)
180
        ?        Privileged Register in rs1 (v9)
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        *        Prefetch function constant. (v9)
182
        x        OPF field (v9 impdep).
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        0        32/64 bit immediate for set or setx (v9) insns
184
        _        Ancillary state register in rd (v9a)
185
        /        Ancillary state register in rs1 (v9a)
186

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The following chars are unused: (note: ,[] are used as punctuation)
188
[45]
189

190
*/
191

    
192
#define OP2(x)                (((x)&0x7) << 22) /* op2 field of format2 insns */
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#define OP3(x)                (((x)&0x3f) << 19) /* op3 field of format3 insns */
194
#define OP(x)                ((unsigned)((x)&0x3) << 30) /* op field of all insns */
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#define OPF(x)                (((x)&0x1ff) << 5) /* opf field of float insns */
196
#define OPF_LOW5(x)        OPF((x)&0x1f) /* v9 */
197
#define F3F(x, y, z)        (OP(x) | OP3(y) | OPF(z)) /* format3 float insns */
198
#define F3I(x)                (((x)&0x1) << 13) /* immediate field of format 3 insns */
199
#define F2(x, y)        (OP(x) | OP2(y)) /* format 2 insns */
200
#define F3(x, y, z)        (OP(x) | OP3(y) | F3I(z)) /* format3 insns */
201
#define F1(x)                (OP(x))
202
#define DISP30(x)        ((x)&0x3fffffff)
203
#define ASI(x)                (((x)&0xff) << 5) /* asi field of format3 insns */
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#define RS2(x)                ((x)&0x1f) /* rs2 field */
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#define SIMM13(x)        ((x)&0x1fff) /* simm13 field */
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#define RD(x)                (((x)&0x1f) << 25) /* destination register field */
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#define RS1(x)                (((x)&0x1f) << 14) /* rs1 field */
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#define ASI_RS2(x)        (SIMM13(x))
209
#define MEMBAR(x)        ((x)&0x7f)
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#define SLCPOP(x)        (((x)&0x7f) << 6) /* sparclet cpop */
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212
#define ANNUL        (1<<29)
213
#define BPRED        (1<<19)        /* v9 */
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#define        IMMED        F3I(1)
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#define RD_G0        RD(~0)
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#define        RS1_G0        RS1(~0)
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#define        RS2_G0        RS2(~0)
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219
extern const struct sparc_opcode sparc_opcodes[];
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extern const int sparc_num_opcodes;
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222
extern int sparc_encode_asi PARAMS ((const char *));
223
extern const char *sparc_decode_asi PARAMS ((int));
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extern int sparc_encode_membar PARAMS ((const char *));
225
extern const char *sparc_decode_membar PARAMS ((int));
226
extern int sparc_encode_prefetch PARAMS ((const char *));
227
extern const char *sparc_decode_prefetch PARAMS ((int));
228
extern int sparc_encode_sparclet_cpreg PARAMS ((const char *));
229
extern const char *sparc_decode_sparclet_cpreg PARAMS ((int));
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231
/* Some defines to make life easy.  */
232
#define MASK_V6                SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6)
233
#define MASK_V7                SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7)
234
#define MASK_V8                SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)
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#define MASK_SPARCLET        SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET)
236
#define MASK_SPARCLITE        SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
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#define MASK_V9                SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9)
238
#define MASK_V9A        SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)
239
#define MASK_V9B        SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B)
240

    
241
/* Bit masks of architectures supporting the insn.  */
242

    
243
#define v6                (MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \
244
                         | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
245
/* v6 insns not supported on the sparclet */
246
#define v6notlet        (MASK_V6 | MASK_V7 | MASK_V8 \
247
                         | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
248
#define v7                (MASK_V7 | MASK_V8 | MASK_SPARCLET \
249
                         | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
250
/* Although not all insns are implemented in hardware, sparclite is defined
251
   to be a superset of v8.  Unimplemented insns trap and are then theoretically
252
   implemented in software.
253
   It's not clear that the same is true for sparclet, although the docs
254
   suggest it is.  Rather than complicating things, the sparclet assembler
255
   recognizes all v8 insns.  */
256
#define v8                (MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE \
257
                         | MASK_V9 | MASK_V9A | MASK_V9B)
258
#define sparclet        (MASK_SPARCLET)
259
#define sparclite        (MASK_SPARCLITE)
260
#define v9                (MASK_V9 | MASK_V9A | MASK_V9B)
261
#define v9a                (MASK_V9A | MASK_V9B)
262
#define v9b                (MASK_V9B)
263
/* v6 insns not supported by v9 */
264
#define v6notv9                (MASK_V6 | MASK_V7 | MASK_V8 \
265
                         | MASK_SPARCLET | MASK_SPARCLITE)
266
/* v9a instructions which would appear to be aliases to v9's impdep's
267
   otherwise */
268
#define v9notv9a        (MASK_V9)
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270
/* Table of opcode architectures.
271
   The order is defined in opcode/sparc.h.  */
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273
const struct sparc_opcode_arch sparc_opcode_archs[] = {
274
  { "v6", MASK_V6 },
275
  { "v7", MASK_V6 | MASK_V7 },
276
  { "v8", MASK_V6 | MASK_V7 | MASK_V8 },
277
  { "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET },
278
  { "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE },
279
  /* ??? Don't some v8 privileged insns conflict with v9?  */
280
  { "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 },
281
  /* v9 with ultrasparc additions */
282
  { "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A },
283
  /* v9 with cheetah additions */
284
  { "v9b", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B },
285
  { NULL, 0 }
286
};
287

    
288
/* Given NAME, return it's architecture entry.  */
289

    
290
enum sparc_opcode_arch_val
291
sparc_opcode_lookup_arch (name)
292
     const char *name;
293
{
294
  const struct sparc_opcode_arch *p;
295

    
296
  for (p = &sparc_opcode_archs[0]; p->name; ++p)
297
    {
298
      if (strcmp (name, p->name) == 0)
299
        return (enum sparc_opcode_arch_val) (p - &sparc_opcode_archs[0]);
300
    }
301

    
302
  return SPARC_OPCODE_ARCH_BAD;
303
}
304
 
305
/* Branch condition field.  */
306
#define COND(x)                (((x)&0xf)<<25)
307

    
308
/* v9: Move (MOVcc and FMOVcc) condition field.  */
309
#define MCOND(x,i_or_f)        ((((i_or_f)&1)<<18)|(((x)>>11)&(0xf<<14))) /* v9 */
310

    
311
/* v9: Move register (MOVRcc and FMOVRcc) condition field.  */
312
#define RCOND(x)        (((x)&0x7)<<10)        /* v9 */
313

    
314
#define CONDA        (COND(0x8))
315
#define CONDCC        (COND(0xd))
316
#define CONDCS        (COND(0x5))
317
#define CONDE        (COND(0x1))
318
#define CONDG        (COND(0xa))
319
#define CONDGE        (COND(0xb))
320
#define CONDGU        (COND(0xc))
321
#define CONDL        (COND(0x3))
322
#define CONDLE        (COND(0x2))
323
#define CONDLEU        (COND(0x4))
324
#define CONDN        (COND(0x0))
325
#define CONDNE        (COND(0x9))
326
#define CONDNEG        (COND(0x6))
327
#define CONDPOS        (COND(0xe))
328
#define CONDVC        (COND(0xf))
329
#define CONDVS        (COND(0x7))
330

    
331
#define CONDNZ        CONDNE
332
#define CONDZ        CONDE
333
#define CONDGEU        CONDCC
334
#define CONDLU        CONDCS
335

    
336
#define FCONDA                (COND(0x8))
337
#define FCONDE                (COND(0x9))
338
#define FCONDG                (COND(0x6))
339
#define FCONDGE                (COND(0xb))
340
#define FCONDL                (COND(0x4))
341
#define FCONDLE                (COND(0xd))
342
#define FCONDLG                (COND(0x2))
343
#define FCONDN                (COND(0x0))
344
#define FCONDNE                (COND(0x1))
345
#define FCONDO                (COND(0xf))
346
#define FCONDU                (COND(0x7))
347
#define FCONDUE                (COND(0xa))
348
#define FCONDUG                (COND(0x5))
349
#define FCONDUGE        (COND(0xc))
350
#define FCONDUL                (COND(0x3))
351
#define FCONDULE        (COND(0xe))
352

    
353
#define FCONDNZ        FCONDNE
354
#define FCONDZ        FCONDE
355

    
356
#define ICC (0)        /* v9 */
357
#define XCC (1<<12) /* v9 */
358
#define FCC(x)        (((x)&0x3)<<11) /* v9 */
359
#define FBFCC(x)        (((x)&0x3)<<20)        /* v9 */
360
 
361
/* The order of the opcodes in the table is significant:
362

363
        * The assembler requires that all instances of the same mnemonic must
364
        be consecutive.        If they aren't, the assembler will bomb at runtime.
365

366
        * The disassembler should not care about the order of the opcodes.
367

368
*/
369

    
370
/* Entries for commutative arithmetic operations.  */
371
/* ??? More entries can make use of this.  */
372
#define COMMUTEOP(opcode, op3, arch_mask) \
373
{ opcode,        F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0),        "1,2,d", 0, arch_mask }, \
374
{ opcode,        F3(2, op3, 1), F3(~2, ~op3, ~1),                "1,i,d", 0, arch_mask }, \
375
{ opcode,        F3(2, op3, 1), F3(~2, ~op3, ~1),                "i,1,d", 0, arch_mask }
376

    
377
const struct sparc_opcode sparc_opcodes[] = {
378

    
379
{ "ld",        F3(3, 0x00, 0), F3(~3, ~0x00, ~0),                "[1+2],d", 0, v6 },
380
{ "ld",        F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0,        "[1],d", 0, v6 }, /* ld [rs1+%g0],d */
381
{ "ld",        F3(3, 0x00, 1), F3(~3, ~0x00, ~1),                "[1+i],d", 0, v6 },
382
{ "ld",        F3(3, 0x00, 1), F3(~3, ~0x00, ~1),                "[i+1],d", 0, v6 },
383
{ "ld",        F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0,        "[i],d", 0, v6 },
384
{ "ld",        F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0),        "[1],d", 0, v6 }, /* ld [rs1+0],d */
385
{ "ld",        F3(3, 0x20, 0), F3(~3, ~0x20, ~0),                "[1+2],g", 0, v6 },
386
{ "ld",        F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0,        "[1],g", 0, v6 }, /* ld [rs1+%g0],d */
387
{ "ld",        F3(3, 0x20, 1), F3(~3, ~0x20, ~1),                "[1+i],g", 0, v6 },
388
{ "ld",        F3(3, 0x20, 1), F3(~3, ~0x20, ~1),                "[i+1],g", 0, v6 },
389
{ "ld",        F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0,        "[i],g", 0, v6 },
390
{ "ld",        F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0),        "[1],g", 0, v6 }, /* ld [rs1+0],d */
391

    
392
{ "ld",        F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0),        "[1+2],F", 0, v6 },
393
{ "ld",        F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+%g0],d */
394
{ "ld",        F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0),        "[1+i],F", 0, v6 },
395
{ "ld",        F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0),        "[i+1],F", 0, v6 },
396
{ "ld",        F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~0),"[i],F", 0, v6 },
397
{ "ld",        F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+0],d */
398

    
399
{ "ld",        F3(3, 0x30, 0), F3(~3, ~0x30, ~0),                "[1+2],D", 0, v6notv9 },
400
{ "ld",        F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0,        "[1],D", 0, v6notv9 }, /* ld [rs1+%g0],d */
401
{ "ld",        F3(3, 0x30, 1), F3(~3, ~0x30, ~1),                "[1+i],D", 0, v6notv9 },
402
{ "ld",        F3(3, 0x30, 1), F3(~3, ~0x30, ~1),                "[i+1],D", 0, v6notv9 },
403
{ "ld",        F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0,        "[i],D", 0, v6notv9 },
404
{ "ld",        F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0),        "[1],D", 0, v6notv9 }, /* ld [rs1+0],d */
405
{ "ld",        F3(3, 0x31, 0), F3(~3, ~0x31, ~0),                "[1+2],C", 0, v6notv9 },
406
{ "ld",        F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0,        "[1],C", 0, v6notv9 }, /* ld [rs1+%g0],d */
407
{ "ld",        F3(3, 0x31, 1), F3(~3, ~0x31, ~1),                "[1+i],C", 0, v6notv9 },
408
{ "ld",        F3(3, 0x31, 1), F3(~3, ~0x31, ~1),                "[i+1],C", 0, v6notv9 },
409
{ "ld",        F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0,        "[i],C", 0, v6notv9 },
410
{ "ld",        F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0),        "[1],C", 0, v6notv9 }, /* ld [rs1+0],d */
411

    
412
/* The v9 LDUW is the same as the old 'ld' opcode, it is not the same as the
413
   'ld' pseudo-op in v9.  */
414
{ "lduw",        F3(3, 0x00, 0), F3(~3, ~0x00, ~0),                "[1+2],d", F_ALIAS, v9 },
415
{ "lduw",        F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0,        "[1],d", F_ALIAS, v9 }, /* ld [rs1+%g0],d */
416
{ "lduw",        F3(3, 0x00, 1), F3(~3, ~0x00, ~1),                "[1+i],d", F_ALIAS, v9 },
417
{ "lduw",        F3(3, 0x00, 1), F3(~3, ~0x00, ~1),                "[i+1],d", F_ALIAS, v9 },
418
{ "lduw",        F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0,        "[i],d", F_ALIAS, v9 },
419
{ "lduw",        F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0),        "[1],d", F_ALIAS, v9 }, /* ld [rs1+0],d */
420

    
421
{ "ldd",        F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0),        "[1+2],d", 0, v6 },
422
{ "ldd",        F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0),        "[1],d", 0, v6 }, /* ldd [rs1+%g0],d */
423
{ "ldd",        F3(3, 0x03, 1), F3(~3, ~0x03, ~1),                "[1+i],d", 0, v6 },
424
{ "ldd",        F3(3, 0x03, 1), F3(~3, ~0x03, ~1),                "[i+1],d", 0, v6 },
425
{ "ldd",        F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0,        "[i],d", 0, v6 },
426
{ "ldd",        F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0),        "[1],d", 0, v6 }, /* ldd [rs1+0],d */
427
{ "ldd",        F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0),        "[1+2],H", 0, v6 },
428
{ "ldd",        F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0),        "[1],H", 0, v6 }, /* ldd [rs1+%g0],d */
429
{ "ldd",        F3(3, 0x23, 1), F3(~3, ~0x23, ~1),                "[1+i],H", 0, v6 },
430
{ "ldd",        F3(3, 0x23, 1), F3(~3, ~0x23, ~1),                "[i+1],H", 0, v6 },
431
{ "ldd",        F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0,        "[i],H", 0, v6 },
432
{ "ldd",        F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0),        "[1],H", 0, v6 }, /* ldd [rs1+0],d */
433

    
434
{ "ldd",        F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0),        "[1+2],D", 0, v6notv9 },
435
{ "ldd",        F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0),        "[1],D", 0, v6notv9 }, /* ldd [rs1+%g0],d */
436
{ "ldd",        F3(3, 0x33, 1), F3(~3, ~0x33, ~1),                "[1+i],D", 0, v6notv9 },
437
{ "ldd",        F3(3, 0x33, 1), F3(~3, ~0x33, ~1),                "[i+1],D", 0, v6notv9 },
438
{ "ldd",        F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0,        "[i],D", 0, v6notv9 },
439
{ "ldd",        F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0),        "[1],D", 0, v6notv9 }, /* ldd [rs1+0],d */
440

    
441
{ "ldq",        F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0),        "[1+2],J", 0, v9 },
442
{ "ldq",        F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI_RS2(~0),        "[1],J", 0, v9 }, /* ldd [rs1+%g0],d */
443
{ "ldq",        F3(3, 0x22, 1), F3(~3, ~0x22, ~1),                "[1+i],J", 0, v9 },
444
{ "ldq",        F3(3, 0x22, 1), F3(~3, ~0x22, ~1),                "[i+1],J", 0, v9 },
445
{ "ldq",        F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|RS1_G0,        "[i],J", 0, v9 },
446
{ "ldq",        F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|SIMM13(~0),        "[1],J", 0, v9 }, /* ldd [rs1+0],d */
447

    
448
{ "ldsb",        F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0),        "[1+2],d", 0, v6 },
449
{ "ldsb",        F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0),        "[1],d", 0, v6 }, /* ldsb [rs1+%g0],d */
450
{ "ldsb",        F3(3, 0x09, 1), F3(~3, ~0x09, ~1),                "[1+i],d", 0, v6 },
451
{ "ldsb",        F3(3, 0x09, 1), F3(~3, ~0x09, ~1),                "[i+1],d", 0, v6 },
452
{ "ldsb",        F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0,        "[i],d", 0, v6 },
453
{ "ldsb",        F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0),        "[1],d", 0, v6 }, /* ldsb [rs1+0],d */
454

    
455
{ "ldsh",        F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0),        "[1],d", 0, v6 }, /* ldsh [rs1+%g0],d */
456
{ "ldsh",        F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0),        "[1+2],d", 0, v6 },
457
{ "ldsh",        F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1),                "[1+i],d", 0, v6 },
458
{ "ldsh",        F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1),                "[i+1],d", 0, v6 },
459
{ "ldsh",        F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0,        "[i],d", 0, v6 },
460
{ "ldsh",        F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0),        "[1],d", 0, v6 }, /* ldsh [rs1+0],d */
461

    
462
{ "ldstub",        F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0),        "[1+2],d", 0, v6 },
463
{ "ldstub",        F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0),        "[1],d", 0, v6 }, /* ldstub [rs1+%g0],d */
464
{ "ldstub",        F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1),                "[1+i],d", 0, v6 },
465
{ "ldstub",        F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1),                "[i+1],d", 0, v6 },
466
{ "ldstub",        F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0,        "[i],d", 0, v6 },
467
{ "ldstub",        F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0),        "[1],d", 0, v6 }, /* ldstub [rs1+0],d */
468

    
469
{ "ldsw",        F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0),        "[1+2],d", 0, v9 },
470
{ "ldsw",        F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0),        "[1],d", 0, v9 }, /* ldsw [rs1+%g0],d */
471
{ "ldsw",        F3(3, 0x08, 1), F3(~3, ~0x08, ~1),                "[1+i],d", 0, v9 },
472
{ "ldsw",        F3(3, 0x08, 1), F3(~3, ~0x08, ~1),                "[i+1],d", 0, v9 },
473
{ "ldsw",        F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0,        "[i],d", 0, v9 },
474
{ "ldsw",        F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0),        "[1],d", 0, v9 }, /* ldsw [rs1+0],d */
475

    
476
{ "ldub",        F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0),        "[1+2],d", 0, v6 },
477
{ "ldub",        F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0),        "[1],d", 0, v6 }, /* ldub [rs1+%g0],d */
478
{ "ldub",        F3(3, 0x01, 1), F3(~3, ~0x01, ~1),                "[1+i],d", 0, v6 },
479
{ "ldub",        F3(3, 0x01, 1), F3(~3, ~0x01, ~1),                "[i+1],d", 0, v6 },
480
{ "ldub",        F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0,        "[i],d", 0, v6 },
481
{ "ldub",        F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0),        "[1],d", 0, v6 }, /* ldub [rs1+0],d */
482

    
483
{ "lduh",        F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0),        "[1+2],d", 0, v6 },
484
{ "lduh",        F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0),        "[1],d", 0, v6 }, /* lduh [rs1+%g0],d */
485
{ "lduh",        F3(3, 0x02, 1), F3(~3, ~0x02, ~1),                "[1+i],d", 0, v6 },
486
{ "lduh",        F3(3, 0x02, 1), F3(~3, ~0x02, ~1),                "[i+1],d", 0, v6 },
487
{ "lduh",        F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0,        "[i],d", 0, v6 },
488
{ "lduh",        F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0),        "[1],d", 0, v6 }, /* lduh [rs1+0],d */
489

    
490
{ "ldx",        F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0),        "[1+2],d", 0, v9 },
491
{ "ldx",        F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0),        "[1],d", 0, v9 }, /* ldx [rs1+%g0],d */
492
{ "ldx",        F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1),                "[1+i],d", 0, v9 },
493
{ "ldx",        F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1),                "[i+1],d", 0, v9 },
494
{ "ldx",        F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0,        "[i],d", 0, v9 },
495
{ "ldx",        F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0),        "[1],d", 0, v9 }, /* ldx [rs1+0],d */
496

    
497
{ "ldx",        F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1),        "[1+2],F", 0, v9 },
498
{ "ldx",        F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0|RD(~1),        "[1],F", 0, v9 }, /* ld [rs1+%g0],d */
499
{ "ldx",        F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1),        "[1+i],F", 0, v9 },
500
{ "ldx",        F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1),        "[i+1],F", 0, v9 },
501
{ "ldx",        F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~1),        "[i],F", 0, v9 },
502
{ "ldx",        F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, v9 }, /* ld [rs1+0],d */
503

    
504
{ "lda",        F3(3, 0x10, 0), F3(~3, ~0x10, ~0),                "[1+2]A,d", 0, v6 },
505
{ "lda",        F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0,        "[1]A,d", 0, v6 }, /* lda [rs1+%g0],d */
506
{ "lda",        F3(3, 0x10, 1), F3(~3, ~0x10, ~1),                "[1+i]o,d", 0, v9 },
507
{ "lda",        F3(3, 0x10, 1), F3(~3, ~0x10, ~1),                "[i+1]o,d", 0, v9 },
508
{ "lda",        F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0,        "[i]o,d", 0, v9 },
509
{ "lda",        F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0),        "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
510
{ "lda",        F3(3, 0x30, 0), F3(~3, ~0x30, ~0),                "[1+2]A,g", 0, v9 },
511
{ "lda",        F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0,        "[1]A,g", 0, v9 }, /* lda [rs1+%g0],d */
512
{ "lda",        F3(3, 0x30, 1), F3(~3, ~0x30, ~1),                "[1+i]o,g", 0, v9 },
513
{ "lda",        F3(3, 0x30, 1), F3(~3, ~0x30, ~1),                "[i+1]o,g", 0, v9 },
514
{ "lda",        F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0,        "[i]o,g", 0, v9 },
515
{ "lda",        F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0),        "[1]o,g", 0, v9 }, /* ld [rs1+0],d */
516

    
517
{ "ldda",        F3(3, 0x13, 0), F3(~3, ~0x13, ~0),                "[1+2]A,d", 0, v6 },
518
{ "ldda",        F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0,        "[1]A,d", 0, v6 }, /* ldda [rs1+%g0],d */
519
{ "ldda",        F3(3, 0x13, 1), F3(~3, ~0x13, ~1),                "[1+i]o,d", 0, v9 },
520
{ "ldda",        F3(3, 0x13, 1), F3(~3, ~0x13, ~1),                "[i+1]o,d", 0, v9 },
521
{ "ldda",        F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0,        "[i]o,d", 0, v9 },
522
{ "ldda",        F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0),        "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
523

    
524
{ "ldda",        F3(3, 0x33, 0), F3(~3, ~0x33, ~0),                "[1+2]A,H", 0, v9 },
525
{ "ldda",        F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|RS2_G0,        "[1]A,H", 0, v9 }, /* ldda [rs1+%g0],d */
526
{ "ldda",        F3(3, 0x33, 1), F3(~3, ~0x33, ~1),                "[1+i]o,H", 0, v9 },
527
{ "ldda",        F3(3, 0x33, 1), F3(~3, ~0x33, ~1),                "[i+1]o,H", 0, v9 },
528
{ "ldda",        F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0,        "[i]o,H", 0, v9 },
529
{ "ldda",        F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0),        "[1]o,H", 0, v9 }, /* ld [rs1+0],d */
530

    
531
{ "ldqa",        F3(3, 0x32, 0), F3(~3, ~0x32, ~0),                "[1+2]A,J", 0, v9 },
532
{ "ldqa",        F3(3, 0x32, 0), F3(~3, ~0x32, ~0)|RS2_G0,        "[1]A,J", 0, v9 }, /* ldd [rs1+%g0],d */
533
{ "ldqa",        F3(3, 0x32, 1), F3(~3, ~0x32, ~1),                "[1+i]o,J", 0, v9 },
534
{ "ldqa",        F3(3, 0x32, 1), F3(~3, ~0x32, ~1),                "[i+1]o,J", 0, v9 },
535
{ "ldqa",        F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|RS1_G0,        "[i]o,J", 0, v9 },
536
{ "ldqa",        F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|SIMM13(~0),        "[1]o,J", 0, v9 }, /* ldd [rs1+0],d */
537

    
538
{ "ldsba",        F3(3, 0x19, 0), F3(~3, ~0x19, ~0),                "[1+2]A,d", 0, v6 },
539
{ "ldsba",        F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0,        "[1]A,d", 0, v6 }, /* ldsba [rs1+%g0],d */
540
{ "ldsba",        F3(3, 0x19, 1), F3(~3, ~0x19, ~1),                "[1+i]o,d", 0, v9 },
541
{ "ldsba",        F3(3, 0x19, 1), F3(~3, ~0x19, ~1),                "[i+1]o,d", 0, v9 },
542
{ "ldsba",        F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|RS1_G0,        "[i]o,d", 0, v9 },
543
{ "ldsba",        F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|SIMM13(~0),        "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
544

    
545
{ "ldsha",        F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0),                "[1+2]A,d", 0, v6 },
546
{ "ldsha",        F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0,        "[1]A,d", 0, v6 }, /* ldsha [rs1+%g0],d */
547
{ "ldsha",        F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1),                "[1+i]o,d", 0, v9 },
548
{ "ldsha",        F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1),                "[i+1]o,d", 0, v9 },
549
{ "ldsha",        F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|RS1_G0,        "[i]o,d", 0, v9 },
550
{ "ldsha",        F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|SIMM13(~0),        "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
551

    
552
{ "ldstuba",        F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0),                "[1+2]A,d", 0, v6 },
553
{ "ldstuba",        F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0,        "[1]A,d", 0, v6 }, /* ldstuba [rs1+%g0],d */
554
{ "ldstuba",        F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1),                "[1+i]o,d", 0, v9 },
555
{ "ldstuba",        F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1),                "[i+1]o,d", 0, v9 },
556
{ "ldstuba",        F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|RS1_G0,        "[i]o,d", 0, v9 },
557
{ "ldstuba",        F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|SIMM13(~0),        "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
558

    
559
{ "ldswa",        F3(3, 0x18, 0), F3(~3, ~0x18, ~0),                "[1+2]A,d", 0, v9 },
560
{ "ldswa",        F3(3, 0x18, 0), F3(~3, ~0x18, ~0)|RS2_G0,        "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */
561
{ "ldswa",        F3(3, 0x18, 1), F3(~3, ~0x18, ~1),                "[1+i]o,d", 0, v9 },
562
{ "ldswa",        F3(3, 0x18, 1), F3(~3, ~0x18, ~1),                "[i+1]o,d", 0, v9 },
563
{ "ldswa",        F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|RS1_G0,        "[i]o,d", 0, v9 },
564
{ "ldswa",        F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|SIMM13(~0),        "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
565

    
566
{ "lduba",        F3(3, 0x11, 0), F3(~3, ~0x11, ~0),                "[1+2]A,d", 0, v6 },
567
{ "lduba",        F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0,        "[1]A,d", 0, v6 }, /* lduba [rs1+%g0],d */
568
{ "lduba",        F3(3, 0x11, 1), F3(~3, ~0x11, ~1),                "[1+i]o,d", 0, v9 },
569
{ "lduba",        F3(3, 0x11, 1), F3(~3, ~0x11, ~1),                "[i+1]o,d", 0, v9 },
570
{ "lduba",        F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|RS1_G0,        "[i]o,d", 0, v9 },
571
{ "lduba",        F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|SIMM13(~0),        "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
572

    
573
{ "lduha",        F3(3, 0x12, 0), F3(~3, ~0x12, ~0),                "[1+2]A,d", 0, v6 },
574
{ "lduha",        F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0,        "[1]A,d", 0, v6 }, /* lduha [rs1+%g0],d */
575
{ "lduha",        F3(3, 0x12, 1), F3(~3, ~0x12, ~1),                "[1+i]o,d", 0, v9 },
576
{ "lduha",        F3(3, 0x12, 1), F3(~3, ~0x12, ~1),                "[i+1]o,d", 0, v9 },
577
{ "lduha",        F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|RS1_G0,        "[i]o,d", 0, v9 },
578
{ "lduha",        F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|SIMM13(~0),        "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
579

    
580
{ "lduwa",        F3(3, 0x10, 0), F3(~3, ~0x10, ~0),                "[1+2]A,d", F_ALIAS, v9 }, /* lduwa === lda */
581
{ "lduwa",        F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0,        "[1]A,d", F_ALIAS, v9 }, /* lda [rs1+%g0],d */
582
{ "lduwa",        F3(3, 0x10, 1), F3(~3, ~0x10, ~1),                "[1+i]o,d", F_ALIAS, v9 },
583
{ "lduwa",        F3(3, 0x10, 1), F3(~3, ~0x10, ~1),                "[i+1]o,d", F_ALIAS, v9 },
584
{ "lduwa",        F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0,        "[i]o,d", F_ALIAS, v9 },
585
{ "lduwa",        F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0),        "[1]o,d", F_ALIAS, v9 }, /* ld [rs1+0],d */
586

    
587
{ "ldxa",        F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0),                "[1+2]A,d", 0, v9 },
588
{ "ldxa",        F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0)|RS2_G0,        "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */
589
{ "ldxa",        F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1),                "[1+i]o,d", 0, v9 },
590
{ "ldxa",        F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1),                "[i+1]o,d", 0, v9 },
591
{ "ldxa",        F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|RS1_G0,        "[i]o,d", 0, v9 },
592
{ "ldxa",        F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|SIMM13(~0),        "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
593

    
594
{ "st",        F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),                "d,[1+2]", 0, v6 },
595
{ "st",        F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),                "d,[1]", 0, v6 }, /* st d,[rs1+%g0] */
596
{ "st",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1),                        "d,[1+i]", 0, v6 },
597
{ "st",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1),                        "d,[i+1]", 0, v6 },
598
{ "st",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,                "d,[i]", 0, v6 },
599
{ "st",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),                "d,[1]", 0, v6 }, /* st d,[rs1+0] */
600
{ "st",        F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0),                "g,[1+2]", 0, v6 },
601
{ "st",        F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0),                "g,[1]", 0, v6 }, /* st d[rs1+%g0] */
602
{ "st",        F3(3, 0x24, 1), F3(~3, ~0x24, ~1),                        "g,[1+i]", 0, v6 },
603
{ "st",        F3(3, 0x24, 1), F3(~3, ~0x24, ~1),                        "g,[i+1]", 0, v6 },
604
{ "st",        F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0,                "g,[i]", 0, v6 },
605
{ "st",        F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0),                "g,[1]", 0, v6 }, /* st d,[rs1+0] */
606

    
607
{ "st",        F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0),                "D,[1+2]", 0, v6notv9 },
608
{ "st",        F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0),                "D,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */
609
{ "st",        F3(3, 0x34, 1), F3(~3, ~0x34, ~1),                        "D,[1+i]", 0, v6notv9 },
610
{ "st",        F3(3, 0x34, 1), F3(~3, ~0x34, ~1),                        "D,[i+1]", 0, v6notv9 },
611
{ "st",        F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0,                "D,[i]", 0, v6notv9 },
612
{ "st",        F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0),                "D,[1]", 0, v6notv9 }, /* st d,[rs1+0] */
613
{ "st",        F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0),                "C,[1+2]", 0, v6notv9 },
614
{ "st",        F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0),                "C,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */
615
{ "st",        F3(3, 0x35, 1), F3(~3, ~0x35, ~1),                        "C,[1+i]", 0, v6notv9 },
616
{ "st",        F3(3, 0x35, 1), F3(~3, ~0x35, ~1),                        "C,[i+1]", 0, v6notv9 },
617
{ "st",        F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0,                "C,[i]", 0, v6notv9 },
618
{ "st",        F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0),                "C,[1]", 0, v6notv9 }, /* st d,[rs1+0] */
619

    
620
{ "st",        F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0),        "F,[1+2]", 0, v6 },
621
{ "st",        F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0),        "F,[1]", 0, v6 }, /* st d,[rs1+%g0] */
622
{ "st",        F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0,                "F,[1+i]", 0, v6 },
623
{ "st",        F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0,                "F,[i+1]", 0, v6 },
624
{ "st",        F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0,                "F,[i]", 0, v6 },
625
{ "st",        F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|SIMM13(~0),        "F,[1]", 0, v6 }, /* st d,[rs1+0] */
626

    
627
{ "stw",        F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),        "d,[1+2]", F_ALIAS, v9 },
628
{ "stw",        F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),        "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */
629
{ "stw",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1),                "d,[1+i]", F_ALIAS, v9 },
630
{ "stw",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1),                "d,[i+1]", F_ALIAS, v9 },
631
{ "stw",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,        "d,[i]", F_ALIAS, v9 },
632
{ "stw",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),        "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */
633
{ "stsw",        F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),        "d,[1+2]", F_ALIAS, v9 },
634
{ "stsw",        F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),        "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */
635
{ "stsw",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1),                "d,[1+i]", F_ALIAS, v9 },
636
{ "stsw",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1),                "d,[i+1]", F_ALIAS, v9 },
637
{ "stsw",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,        "d,[i]", F_ALIAS, v9 },
638
{ "stsw",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),        "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */
639
{ "stuw",        F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),        "d,[1+2]", F_ALIAS, v9 },
640
{ "stuw",        F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),        "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */
641
{ "stuw",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1),                "d,[1+i]", F_ALIAS, v9 },
642
{ "stuw",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1),                "d,[i+1]", F_ALIAS, v9 },
643
{ "stuw",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,        "d,[i]", F_ALIAS, v9 },
644
{ "stuw",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),        "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */
645

    
646
{ "spill",        F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),        "d,[1+2]", F_ALIAS, v6 },
647
{ "spill",        F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),        "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+%g0] */
648
{ "spill",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1),                "d,[1+i]", F_ALIAS, v6 },
649
{ "spill",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1),                "d,[i+1]", F_ALIAS, v6 },
650
{ "spill",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,        "d,[i]", F_ALIAS, v6 },
651
{ "spill",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),        "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+0] */
652

    
653
{ "sta",        F3(3, 0x14, 0), F3(~3, ~0x14, ~0),                "d,[1+2]A", 0, v6 },
654
{ "sta",        F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0),        "d,[1]A", 0, v6 }, /* sta d,[rs1+%g0] */
655
{ "sta",        F3(3, 0x14, 1), F3(~3, ~0x14, ~1),                "d,[1+i]o", 0, v9 },
656
{ "sta",        F3(3, 0x14, 1), F3(~3, ~0x14, ~1),                "d,[i+1]o", 0, v9 },
657
{ "sta",        F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0,        "d,[i]o", 0, v9 },
658
{ "sta",        F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0),        "d,[1]o", 0, v9 }, /* st d,[rs1+0] */
659

    
660
{ "sta",        F3(3, 0x34, 0), F3(~3, ~0x34, ~0),                "g,[1+2]A", 0, v9 },
661
{ "sta",        F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|RS2(~0),        "g,[1]A", 0, v9 }, /* sta d,[rs1+%g0] */
662
{ "sta",        F3(3, 0x34, 1), F3(~3, ~0x34, ~1),                "g,[1+i]o", 0, v9 },
663
{ "sta",        F3(3, 0x34, 1), F3(~3, ~0x34, ~1),                "g,[i+1]o", 0, v9 },
664
{ "sta",        F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0,        "g,[i]o", 0, v9 },
665
{ "sta",        F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0),        "g,[1]o", 0, v9 }, /* st d,[rs1+0] */
666

    
667
{ "stwa",        F3(3, 0x14, 0), F3(~3, ~0x14, ~0),                "d,[1+2]A", F_ALIAS, v9 },
668
{ "stwa",        F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0),        "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */
669
{ "stwa",        F3(3, 0x14, 1), F3(~3, ~0x14, ~1),                "d,[1+i]o", F_ALIAS, v9 },
670
{ "stwa",        F3(3, 0x14, 1), F3(~3, ~0x14, ~1),                "d,[i+1]o", F_ALIAS, v9 },
671
{ "stwa",        F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0,        "d,[i]o", F_ALIAS, v9 },
672
{ "stwa",        F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0),        "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */
673
{ "stswa",        F3(3, 0x14, 0), F3(~3, ~0x14, ~0),                "d,[1+2]A", F_ALIAS, v9 },
674
{ "stswa",        F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0),        "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */
675
{ "stswa",        F3(3, 0x14, 1), F3(~3, ~0x14, ~1),                "d,[1+i]o", F_ALIAS, v9 },
676
{ "stswa",        F3(3, 0x14, 1), F3(~3, ~0x14, ~1),                "d,[i+1]o", F_ALIAS, v9 },
677
{ "stswa",        F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0,        "d,[i]o", F_ALIAS, v9 },
678
{ "stswa",        F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0),        "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */
679
{ "stuwa",        F3(3, 0x14, 0), F3(~3, ~0x14, ~0),                "d,[1+2]A", F_ALIAS, v9 },
680
{ "stuwa",        F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0),        "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */
681
{ "stuwa",        F3(3, 0x14, 1), F3(~3, ~0x14, ~1),                "d,[1+i]o", F_ALIAS, v9 },
682
{ "stuwa",        F3(3, 0x14, 1), F3(~3, ~0x14, ~1),                "d,[i+1]o", F_ALIAS, v9 },
683
{ "stuwa",        F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0,        "d,[i]o", F_ALIAS, v9 },
684
{ "stuwa",        F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0),        "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */
685

    
686
{ "stb",        F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0),        "d,[1+2]", 0, v6 },
687
{ "stb",        F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0),        "d,[1]", 0, v6 }, /* stb d,[rs1+%g0] */
688
{ "stb",        F3(3, 0x05, 1), F3(~3, ~0x05, ~1),                "d,[1+i]", 0, v6 },
689
{ "stb",        F3(3, 0x05, 1), F3(~3, ~0x05, ~1),                "d,[i+1]", 0, v6 },
690
{ "stb",        F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0,        "d,[i]", 0, v6 },
691
{ "stb",        F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0),        "d,[1]", 0, v6 }, /* stb d,[rs1+0] */
692

    
693
{ "stsb",        F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0),        "d,[1+2]", F_ALIAS, v6 },
694
{ "stsb",        F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0),        "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */
695
{ "stsb",        F3(3, 0x05, 1), F3(~3, ~0x05, ~1),                "d,[1+i]", F_ALIAS, v6 },
696
{ "stsb",        F3(3, 0x05, 1), F3(~3, ~0x05, ~1),                "d,[i+1]", F_ALIAS, v6 },
697
{ "stsb",        F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0,        "d,[i]", F_ALIAS, v6 },
698
{ "stsb",        F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0),        "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */
699
{ "stub",        F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0),        "d,[1+2]", F_ALIAS, v6 },
700
{ "stub",        F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0),        "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */
701
{ "stub",        F3(3, 0x05, 1), F3(~3, ~0x05, ~1),                "d,[1+i]", F_ALIAS, v6 },
702
{ "stub",        F3(3, 0x05, 1), F3(~3, ~0x05, ~1),                "d,[i+1]", F_ALIAS, v6 },
703
{ "stub",        F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0,        "d,[i]", F_ALIAS, v6 },
704
{ "stub",        F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0),        "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */
705

    
706
{ "stba",        F3(3, 0x15, 0), F3(~3, ~0x15, ~0),                "d,[1+2]A", 0, v6 },
707
{ "stba",        F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0),        "d,[1]A", 0, v6 }, /* stba d,[rs1+%g0] */
708
{ "stba",        F3(3, 0x15, 1), F3(~3, ~0x15, ~1),                "d,[1+i]o", 0, v9 },
709
{ "stba",        F3(3, 0x15, 1), F3(~3, ~0x15, ~1),                "d,[i+1]o", 0, v9 },
710
{ "stba",        F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0,        "d,[i]o", 0, v9 },
711
{ "stba",        F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0),        "d,[1]o", 0, v9 }, /* stb d,[rs1+0] */
712

    
713
{ "stsba",        F3(3, 0x15, 0), F3(~3, ~0x15, ~0),                "d,[1+2]A", F_ALIAS, v6 },
714
{ "stsba",        F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0),        "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */
715
{ "stsba",        F3(3, 0x15, 1), F3(~3, ~0x15, ~1),                "d,[1+i]o", F_ALIAS, v9 },
716
{ "stsba",        F3(3, 0x15, 1), F3(~3, ~0x15, ~1),                "d,[i+1]o", F_ALIAS, v9 },
717
{ "stsba",        F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0,        "d,[i]o", F_ALIAS, v9 },
718
{ "stsba",        F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0),        "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */
719
{ "stuba",        F3(3, 0x15, 0), F3(~3, ~0x15, ~0),                "d,[1+2]A", F_ALIAS, v6 },
720
{ "stuba",        F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0),        "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */
721
{ "stuba",        F3(3, 0x15, 1), F3(~3, ~0x15, ~1),                "d,[1+i]o", F_ALIAS, v9 },
722
{ "stuba",        F3(3, 0x15, 1), F3(~3, ~0x15, ~1),                "d,[i+1]o", F_ALIAS, v9 },
723
{ "stuba",        F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0,        "d,[i]o", F_ALIAS, v9 },
724
{ "stuba",        F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0),        "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */
725

    
726
{ "std",        F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0),        "d,[1+2]", 0, v6 },
727
{ "std",        F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0),        "d,[1]", 0, v6 }, /* std d,[rs1+%g0] */
728
{ "std",        F3(3, 0x07, 1), F3(~3, ~0x07, ~1),                "d,[1+i]", 0, v6 },
729
{ "std",        F3(3, 0x07, 1), F3(~3, ~0x07, ~1),                "d,[i+1]", 0, v6 },
730
{ "std",        F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0,        "d,[i]", 0, v6 },
731
{ "std",        F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0),        "d,[1]", 0, v6 }, /* std d,[rs1+0] */
732

    
733
{ "std",        F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0),        "q,[1+2]", 0, v6notv9 },
734
{ "std",        F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0),        "q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */
735
{ "std",        F3(3, 0x26, 1), F3(~3, ~0x26, ~1),                "q,[1+i]", 0, v6notv9 },
736
{ "std",        F3(3, 0x26, 1), F3(~3, ~0x26, ~1),                "q,[i+1]", 0, v6notv9 },
737
{ "std",        F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0,        "q,[i]", 0, v6notv9 },
738
{ "std",        F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0),        "q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */
739
{ "std",        F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0),        "H,[1+2]", 0, v6 },
740
{ "std",        F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0),        "H,[1]", 0, v6 }, /* std d,[rs1+%g0] */
741
{ "std",        F3(3, 0x27, 1), F3(~3, ~0x27, ~1),                "H,[1+i]", 0, v6 },
742
{ "std",        F3(3, 0x27, 1), F3(~3, ~0x27, ~1),                "H,[i+1]", 0, v6 },
743
{ "std",        F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0,        "H,[i]", 0, v6 },
744
{ "std",        F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0),        "H,[1]", 0, v6 }, /* std d,[rs1+0] */
745

    
746
{ "std",        F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0),        "Q,[1+2]", 0, v6notv9 },
747
{ "std",        F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0),        "Q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */
748
{ "std",        F3(3, 0x36, 1), F3(~3, ~0x36, ~1),                "Q,[1+i]", 0, v6notv9 },
749
{ "std",        F3(3, 0x36, 1), F3(~3, ~0x36, ~1),                "Q,[i+1]", 0, v6notv9 },
750
{ "std",        F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0,        "Q,[i]", 0, v6notv9 },
751
{ "std",        F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0),        "Q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */
752
{ "std",        F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0),        "D,[1+2]", 0, v6notv9 },
753
{ "std",        F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0),        "D,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */
754
{ "std",        F3(3, 0x37, 1), F3(~3, ~0x37, ~1),                "D,[1+i]", 0, v6notv9 },
755
{ "std",        F3(3, 0x37, 1), F3(~3, ~0x37, ~1),                "D,[i+1]", 0, v6notv9 },
756
{ "std",        F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0,        "D,[i]", 0, v6notv9 },
757
{ "std",        F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0),        "D,[1]", 0, v6notv9 }, /* std d,[rs1+0] */
758

    
759
{ "spilld",        F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0),        "d,[1+2]", F_ALIAS, v6 },
760
{ "spilld",        F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0),        "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+%g0] */
761
{ "spilld",        F3(3, 0x07, 1), F3(~3, ~0x07, ~1),                "d,[1+i]", F_ALIAS, v6 },
762
{ "spilld",        F3(3, 0x07, 1), F3(~3, ~0x07, ~1),                "d,[i+1]", F_ALIAS, v6 },
763
{ "spilld",        F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0,        "d,[i]", F_ALIAS, v6 },
764
{ "spilld",        F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0),        "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+0] */
765

    
766
{ "stda",        F3(3, 0x17, 0), F3(~3, ~0x17, ~0),                "d,[1+2]A", 0, v6 },
767
{ "stda",        F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0),        "d,[1]A", 0, v6 }, /* stda d,[rs1+%g0] */
768
{ "stda",        F3(3, 0x17, 1), F3(~3, ~0x17, ~1),                "d,[1+i]o", 0, v9 },
769
{ "stda",        F3(3, 0x17, 1), F3(~3, ~0x17, ~1),                "d,[i+1]o", 0, v9 },
770
{ "stda",        F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0,        "d,[i]o", 0, v9 },
771
{ "stda",        F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0),        "d,[1]o", 0, v9 }, /* std d,[rs1+0] */
772
{ "stda",        F3(3, 0x37, 0), F3(~3, ~0x37, ~0),                "H,[1+2]A", 0, v9 },
773
{ "stda",        F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|RS2(~0),        "H,[1]A", 0, v9 }, /* stda d,[rs1+%g0] */
774
{ "stda",        F3(3, 0x37, 1), F3(~3, ~0x37, ~1),                "H,[1+i]o", 0, v9 },
775
{ "stda",        F3(3, 0x37, 1), F3(~3, ~0x37, ~1),                "H,[i+1]o", 0, v9 },
776
{ "stda",        F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0,        "H,[i]o", 0, v9 },
777
{ "stda",        F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0),        "H,[1]o", 0, v9 }, /* std d,[rs1+0] */
778

    
779
{ "sth",        F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0),        "d,[1+2]", 0, v6 },
780
{ "sth",        F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0),        "d,[1]", 0, v6 }, /* sth d,[rs1+%g0] */
781
{ "sth",        F3(3, 0x06, 1), F3(~3, ~0x06, ~1),                "d,[1+i]", 0, v6 },
782
{ "sth",        F3(3, 0x06, 1), F3(~3, ~0x06, ~1),                "d,[i+1]", 0, v6 },
783
{ "sth",        F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0,        "d,[i]", 0, v6 },
784
{ "sth",        F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0),        "d,[1]", 0, v6 }, /* sth d,[rs1+0] */
785

    
786
{ "stsh",        F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0),        "d,[1+2]", F_ALIAS, v6 },
787
{ "stsh",        F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0),        "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */
788
{ "stsh",        F3(3, 0x06, 1), F3(~3, ~0x06, ~1),                "d,[1+i]", F_ALIAS, v6 },
789
{ "stsh",        F3(3, 0x06, 1), F3(~3, ~0x06, ~1),                "d,[i+1]", F_ALIAS, v6 },
790
{ "stsh",        F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0,        "d,[i]", F_ALIAS, v6 },
791
{ "stsh",        F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0),        "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */
792
{ "stuh",        F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0),        "d,[1+2]", F_ALIAS, v6 },
793
{ "stuh",        F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0),        "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */
794
{ "stuh",        F3(3, 0x06, 1), F3(~3, ~0x06, ~1),                "d,[1+i]", F_ALIAS, v6 },
795
{ "stuh",        F3(3, 0x06, 1), F3(~3, ~0x06, ~1),                "d,[i+1]", F_ALIAS, v6 },
796
{ "stuh",        F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0,        "d,[i]", F_ALIAS, v6 },
797
{ "stuh",        F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0),        "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */
798

    
799
{ "stha",        F3(3, 0x16, 0), F3(~3, ~0x16, ~0),                "d,[1+2]A", 0, v6 },
800
{ "stha",        F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0),        "d,[1]A", 0, v6 }, /* stha ,[rs1+%g0] */
801
{ "stha",        F3(3, 0x16, 1), F3(~3, ~0x16, ~1),                "d,[1+i]o", 0, v9 },
802
{ "stha",        F3(3, 0x16, 1), F3(~3, ~0x16, ~1),                "d,[i+1]o", 0, v9 },
803
{ "stha",        F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0,        "d,[i]o", 0, v9 },
804
{ "stha",        F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0),        "d,[1]o", 0, v9 }, /* sth d,[rs1+0] */
805

    
806
{ "stsha",        F3(3, 0x16, 0), F3(~3, ~0x16, ~0),                "d,[1+2]A", F_ALIAS, v6 },
807
{ "stsha",        F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0),        "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */
808
{ "stsha",        F3(3, 0x16, 1), F3(~3, ~0x16, ~1),                "d,[1+i]o", F_ALIAS, v9 },
809
{ "stsha",        F3(3, 0x16, 1), F3(~3, ~0x16, ~1),                "d,[i+1]o", F_ALIAS, v9 },
810
{ "stsha",        F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0,        "d,[i]o", F_ALIAS, v9 },
811
{ "stsha",        F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0),        "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */
812
{ "stuha",        F3(3, 0x16, 0), F3(~3, ~0x16, ~0),                "d,[1+2]A", F_ALIAS, v6 },
813
{ "stuha",        F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0),        "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */
814
{ "stuha",        F3(3, 0x16, 1), F3(~3, ~0x16, ~1),                "d,[1+i]o", F_ALIAS, v9 },
815
{ "stuha",        F3(3, 0x16, 1), F3(~3, ~0x16, ~1),                "d,[i+1]o", F_ALIAS, v9 },
816
{ "stuha",        F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0,        "d,[i]o", F_ALIAS, v9 },
817
{ "stuha",        F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0),        "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */
818

    
819
{ "stx",        F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0),        "d,[1+2]", 0, v9 },
820
{ "stx",        F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0),        "d,[1]", 0, v9 }, /* stx d,[rs1+%g0] */
821
{ "stx",        F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1),                "d,[1+i]", 0, v9 },
822
{ "stx",        F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1),                "d,[i+1]", 0, v9 },
823
{ "stx",        F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RS1_G0,        "d,[i]", 0, v9 },
824
{ "stx",        F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0),        "d,[1]", 0, v9 }, /* stx d,[rs1+0] */
825

    
826
{ "stx",        F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1),        "F,[1+2]", 0, v9 },
827
{ "stx",        F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI_RS2(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+%g0] */
828
{ "stx",        F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1),                "F,[1+i]", 0, v9 },
829
{ "stx",        F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1),                "F,[i+1]", 0, v9 },
830
{ "stx",        F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RS1_G0|RD(~1),        "F,[i]", 0, v9 },
831
{ "stx",        F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|SIMM13(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+0] */
832

    
833
{ "stxa",        F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0),                "d,[1+2]A", 0, v9 },
834
{ "stxa",        F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0),        "d,[1]A", 0, v9 }, /* stxa d,[rs1+%g0] */
835
{ "stxa",        F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1),                "d,[1+i]o", 0, v9 },
836
{ "stxa",        F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1),                "d,[i+1]o", 0, v9 },
837
{ "stxa",        F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|RS1_G0,        "d,[i]o", 0, v9 },
838
{ "stxa",        F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|SIMM13(~0),        "d,[1]o", 0, v9 }, /* stx d,[rs1+0] */
839

    
840
{ "stq",        F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0),        "J,[1+2]", 0, v9 },
841
{ "stq",        F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0),        "J,[1]", 0, v9 }, /* stq [rs1+%g0] */
842
{ "stq",        F3(3, 0x26, 1), F3(~3, ~0x26, ~1),                "J,[1+i]", 0, v9 },
843
{ "stq",        F3(3, 0x26, 1), F3(~3, ~0x26, ~1),                "J,[i+1]", 0, v9 },
844
{ "stq",        F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0,        "J,[i]", 0, v9 },
845
{ "stq",        F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0),        "J,[1]", 0, v9 }, /* stq [rs1+0] */
846

    
847
{ "stqa",        F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0),        "J,[1+2]A", 0, v9 },
848
{ "stqa",        F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0),        "J,[1]A", 0, v9 }, /* stqa [rs1+%g0] */
849
{ "stqa",        F3(3, 0x36, 1), F3(~3, ~0x36, ~1),                "J,[1+i]o", 0, v9 },
850
{ "stqa",        F3(3, 0x36, 1), F3(~3, ~0x36, ~1),                "J,[i+1]o", 0, v9 },
851
{ "stqa",        F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0,        "J,[i]o", 0, v9 },
852
{ "stqa",        F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0),        "J,[1]o", 0, v9 }, /* stqa [rs1+0] */
853

    
854
{ "swap",        F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0),        "[1+2],d", 0, v7 },
855
{ "swap",        F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0),        "[1],d", 0, v7 }, /* swap [rs1+%g0],d */
856
{ "swap",        F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1),                "[1+i],d", 0, v7 },
857
{ "swap",        F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1),                "[i+1],d", 0, v7 },
858
{ "swap",        F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0,        "[i],d", 0, v7 },
859
{ "swap",        F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0),        "[1],d", 0, v7 }, /* swap [rs1+0],d */
860

    
861
{ "swapa",        F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0),                "[1+2]A,d", 0, v7 },
862
{ "swapa",        F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0),        "[1]A,d", 0, v7 }, /* swapa [rs1+%g0],d */
863
{ "swapa",        F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1),                "[1+i]o,d", 0, v9 },
864
{ "swapa",        F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1),                "[i+1]o,d", 0, v9 },
865
{ "swapa",        F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|RS1_G0,        "[i]o,d", 0, v9 },
866
{ "swapa",        F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|SIMM13(~0),        "[1]o,d", 0, v9 }, /* swap [rs1+0],d */
867

    
868
{ "restore",        F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0),                        "1,2,d", 0, v6 },
869
{ "restore",        F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0|RS1_G0|ASI_RS2(~0),        "", 0, v6 }, /* restore %g0,%g0,%g0 */
870
{ "restore",        F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1),                                "1,i,d", 0, v6 },
871
{ "restore",        F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0),        "", 0, v6 }, /* restore %g0,0,%g0 */
872

    
873
{ "rett",        F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0),        "1+2", F_UNBR|F_DELAYED, v6 }, /* rett rs1+rs2 */
874
{ "rett",        F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0),        "1", F_UNBR|F_DELAYED, v6 },        /* rett rs1,%g0 */
875
{ "rett",        F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0,                "1+i", F_UNBR|F_DELAYED, v6 }, /* rett rs1+X */
876
{ "rett",        F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0,                "i+1", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */
877
{ "rett",        F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0,                "i", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */
878
{ "rett",        F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0,                "i", F_UNBR|F_DELAYED, v6 },        /* rett X */
879
{ "rett",        F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0),        "1", F_UNBR|F_DELAYED, v6 },        /* rett rs1+0 */
880

    
881
{ "save",        F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0),        "1,2,d", 0, v6 },
882
{ "save",        F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1),                "1,i,d", 0, v6 },
883
{ "save",        0x81e00000,        ~0x81e00000,                        "", F_ALIAS, v6 },
884

    
885
{ "ret",  F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8),               "", F_UNBR|F_DELAYED, v6 }, /* jmpl %i7+8,%g0 */
886
{ "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %o7+8,%g0 */
887

    
888
{ "jmpl",        F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0),        "1+2,d", F_JSR|F_DELAYED, v6 },
889
{ "jmpl",        F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0),        "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,d */
890
{ "jmpl",        F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0),        "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,d */
891
{ "jmpl",        F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0,        "i,d", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,d */
892
{ "jmpl",        F3(2, 0x38, 1), F3(~2, ~0x38, ~1),                "1+i,d", F_JSR|F_DELAYED, v6 },
893
{ "jmpl",        F3(2, 0x38, 1), F3(~2, ~0x38, ~1),                "i+1,d", F_JSR|F_DELAYED, v6 },
894

    
895
{ "done",        F3(2, 0x3e, 0)|RD(0), F3(~2, ~0x3e, ~0)|RD(~0)|RS1_G0|SIMM13(~0),        "", 0, v9 },
896
{ "retry",        F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0|SIMM13(~0),        "", 0, v9 },
897
{ "saved",        F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0|SIMM13(~0),        "", 0, v9 },
898
{ "restored",        F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|SIMM13(~0),        "", 0, v9 },
899
{ "sir",        F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0,                "i", 0, v9 },
900

    
901
{ "flush",        F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0),        "1+2", 0, v8 },
902
{ "flush",        F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0),        "1", 0, v8 }, /* flush rs1+%g0 */
903
{ "flush",        F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0),        "1", 0, v8 }, /* flush rs1+0 */
904
{ "flush",        F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0,        "i", 0, v8 }, /* flush %g0+i */
905
{ "flush",        F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),                "1+i", 0, v8 },
906
{ "flush",        F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),                "i+1", 0, v8 },
907

    
908
/* IFLUSH was renamed to FLUSH in v8.  */
909
{ "iflush",        F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0),        "1+2", F_ALIAS, v6 },
910
{ "iflush",        F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0),        "1", F_ALIAS, v6 }, /* flush rs1+%g0 */
911
{ "iflush",        F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0),        "1", F_ALIAS, v6 }, /* flush rs1+0 */
912
{ "iflush",        F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0,        "i", F_ALIAS, v6 },
913
{ "iflush",        F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),                "1+i", F_ALIAS, v6 },
914
{ "iflush",        F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),                "i+1", F_ALIAS, v6 },
915

    
916
{ "return",        F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI(~0),        "1+2", 0, v9 },
917
{ "return",        F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI_RS2(~0),        "1", 0, v9 }, /* return rs1+%g0 */
918
{ "return",        F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|SIMM13(~0),        "1", 0, v9 }, /* return rs1+0 */
919
{ "return",        F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RS1_G0,        "i", 0, v9 }, /* return %g0+i */
920
{ "return",        F3(2, 0x39, 1), F3(~2, ~0x39, ~1),                "1+i", 0, v9 },
921
{ "return",        F3(2, 0x39, 1), F3(~2, ~0x39, ~1),                "i+1", 0, v9 },
922

    
923
{ "flushw",        F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RD_G0|RS1_G0|ASI_RS2(~0),        "", 0, v9 },
924

    
925
{ "membar",        F3(2, 0x28, 1)|RS1(0xf), F3(~2, ~0x28, ~1)|RD_G0|RS1(~0xf)|SIMM13(~127), "K", 0, v9 },
926
{ "stbar",        F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0|RS1(~0xf)|SIMM13(~0), "", 0, v8 },
927

    
928
{ "prefetch",        F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0),                "[1+2],*", 0, v9 },
929
{ "prefetch",        F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RS2_G0,        "[1],*", 0, v9 }, /* prefetch [rs1+%g0],prefetch_fcn */
930
{ "prefetch",        F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1),                "[1+i],*", 0, v9 },
931
{ "prefetch",        F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1),                "[i+1],*", 0, v9 },
932
{ "prefetch",        F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RS1_G0,        "[i],*", 0, v9 },
933
{ "prefetch",        F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|SIMM13(~0),        "[1],*", 0, v9 }, /* prefetch [rs1+0],prefetch_fcn */
934
{ "prefetcha",        F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0),                "[1+2]A,*", 0, v9 },
935
{ "prefetcha",        F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0)|RS2_G0,        "[1]A,*", 0, v9 }, /* prefetcha [rs1+%g0],prefetch_fcn */
936
{ "prefetcha",        F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1),                "[1+i]o,*", 0, v9 },
937
{ "prefetcha",        F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1),                "[i+1]o,*", 0, v9 },
938
{ "prefetcha",        F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|RS1_G0,        "[i]o,*", 0, v9 },
939
{ "prefetcha",        F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|SIMM13(~0),        "[1]o,*", 0, v9 }, /* prefetcha [rs1+0],d */
940

    
941
{ "sll",        F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|(0x7f<<5),        "1,2,d", 0, v6 },
942
{ "sll",        F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12)|(0x7f<<5),        "1,X,d", 0, v6 },
943
{ "sra",        F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|(0x7f<<5),        "1,2,d", 0, v6 },
944
{ "sra",        F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12)|(0x7f<<5),        "1,X,d", 0, v6 },
945
{ "srl",        F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|(0x7f<<5),        "1,2,d", 0, v6 },
946
{ "srl",        F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12)|(0x7f<<5),        "1,X,d", 0, v6 },
947

    
948
{ "sllx",        F3(2, 0x25, 0)|(1<<12), F3(~2, ~0x25, ~0)|(0x7f<<5),        "1,2,d", 0, v9 },
949
{ "sllx",        F3(2, 0x25, 1)|(1<<12), F3(~2, ~0x25, ~1)|(0x3f<<6),        "1,Y,d", 0, v9 },
950
{ "srax",        F3(2, 0x27, 0)|(1<<12), F3(~2, ~0x27, ~0)|(0x7f<<5),        "1,2,d", 0, v9 },
951
{ "srax",        F3(2, 0x27, 1)|(1<<12), F3(~2, ~0x27, ~1)|(0x3f<<6),        "1,Y,d", 0, v9 },
952
{ "srlx",        F3(2, 0x26, 0)|(1<<12), F3(~2, ~0x26, ~0)|(0x7f<<5),        "1,2,d", 0, v9 },
953
{ "srlx",        F3(2, 0x26, 1)|(1<<12), F3(~2, ~0x26, ~1)|(0x3f<<6),        "1,Y,d", 0, v9 },
954

    
955
{ "mulscc",        F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0),        "1,2,d", 0, v6 },
956
{ "mulscc",        F3(2, 0x24, 1), F3(~2, ~0x24, ~1),                "1,i,d", 0, v6 },
957

    
958
{ "divscc",        F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0),        "1,2,d", 0, sparclite },
959
{ "divscc",        F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1),                "1,i,d", 0, sparclite },
960

    
961
{ "scan",        F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0),        "1,2,d", 0, sparclet|sparclite },
962
{ "scan",        F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1),                "1,i,d", 0, sparclet|sparclite },
963

    
964
{ "popc",        F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS1_G0|ASI(~0),"2,d", 0, v9 },
965
{ "popc",        F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS1_G0,        "i,d", 0, v9 },
966

    
967
{ "clr",        F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0|RS1_G0|ASI_RS2(~0),        "d", F_ALIAS, v6 }, /* or %g0,%g0,d */
968
{ "clr",        F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0|SIMM13(~0),                "d", F_ALIAS, v6 }, /* or %g0,0,d        */
969
{ "clr",        F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI(~0),                "[1+2]", F_ALIAS, v6 },
970
{ "clr",        F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI_RS2(~0),                "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+%g0] */
971
{ "clr",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0,                        "[1+i]", F_ALIAS, v6 },
972
{ "clr",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0,                        "[i+1]", F_ALIAS, v6 },
973
{ "clr",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0,                        "[i]", F_ALIAS, v6 },
974
{ "clr",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|SIMM13(~0),                "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+0] */
975

    
976
{ "clrb",        F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0),        "[1+2]", F_ALIAS, v6 },
977
{ "clrb",        F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI_RS2(~0),        "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+%g0] */
978
{ "clrb",        F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0,                "[1+i]", F_ALIAS, v6 },
979
{ "clrb",        F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0,                "[i+1]", F_ALIAS, v6 },
980
{ "clrb",        F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0,                "[i]", F_ALIAS, v6 },
981
{ "clrb",        F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|SIMM13(~0),        "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+0] */
982

    
983
{ "clrh",        F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0),        "[1+2]", F_ALIAS, v6 },
984
{ "clrh",        F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI_RS2(~0),        "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+%g0] */
985
{ "clrh",        F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0,                "[1+i]", F_ALIAS, v6 },
986
{ "clrh",        F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0,                "[i+1]", F_ALIAS, v6 },
987
{ "clrh",        F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0,                "[i]", F_ALIAS, v6 },
988
{ "clrh",        F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|SIMM13(~0),        "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+0] */
989

    
990
{ "clrx",        F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI(~0),        "[1+2]", F_ALIAS, v9 },
991
{ "clrx",        F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI_RS2(~0),        "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+%g0] */
992
{ "clrx",        F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0,                "[1+i]", F_ALIAS, v9 },
993
{ "clrx",        F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0,                "[i+1]", F_ALIAS, v9 },
994
{ "clrx",        F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|RS1_G0,                "[i]", F_ALIAS, v9 },
995
{ "clrx",        F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|SIMM13(~0),        "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+0] */
996

    
997
{ "orcc",        F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0),        "1,2,d", 0, v6 },
998
{ "orcc",        F3(2, 0x12, 1), F3(~2, ~0x12, ~1),                "1,i,d", 0, v6 },
999
{ "orcc",        F3(2, 0x12, 1), F3(~2, ~0x12, ~1),                "i,1,d", 0, v6 },
1000

    
1001
/* This is not a commutative instruction.  */
1002
{ "orncc",        F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0),        "1,2,d", 0, v6 },
1003
{ "orncc",        F3(2, 0x16, 1), F3(~2, ~0x16, ~1),                "1,i,d", 0, v6 },
1004

    
1005
/* This is not a commutative instruction.  */
1006
{ "orn",        F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0),        "1,2,d", 0, v6 },
1007
{ "orn",        F3(2, 0x06, 1), F3(~2, ~0x06, ~1),                "1,i,d", 0, v6 },
1008

    
1009
{ "tst",        F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|ASI_RS2(~0),        "1", 0, v6 }, /* orcc rs1, %g0, %g0 */
1010
{ "tst",        F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0),        "2", 0, v6 }, /* orcc %g0, rs2, %g0 */
1011
{ "tst",        F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0),        "1", 0, v6 }, /* orcc rs1, 0, %g0 */
1012

    
1013
{ "wr",        F3(2, 0x30, 0),                F3(~2, ~0x30, ~0)|ASI(~0),                "1,2,m", 0, v8 }, /* wr r,r,%asrX */
1014
{ "wr",        F3(2, 0x30, 1),                F3(~2, ~0x30, ~1),                        "1,i,m", 0, v8 }, /* wr r,i,%asrX */
1015
{ "wr",        F3(2, 0x30, 0),                F3(~2, ~0x30, ~0)|ASI_RS2(~0),                "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */
1016
{ "wr",        F3(2, 0x30, 0),                F3(~2, ~0x30, ~0)|RD_G0|ASI(~0),        "1,2,y", 0, v6 }, /* wr r,r,%y */
1017
{ "wr",        F3(2, 0x30, 1),                F3(~2, ~0x30, ~1)|RD_G0,                "1,i,y", 0, v6 }, /* wr r,i,%y */
1018
{ "wr",        F3(2, 0x30, 0),                F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0),        "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */
1019
{ "wr",        F3(2, 0x31, 0),                F3(~2, ~0x31, ~0)|RD_G0|ASI(~0),        "1,2,p", 0, v6notv9 }, /* wr r,r,%psr */
1020
{ "wr",        F3(2, 0x31, 1),                F3(~2, ~0x31, ~1)|RD_G0,                "1,i,p", 0, v6notv9 }, /* wr r,i,%psr */
1021
{ "wr",        F3(2, 0x31, 0),                F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0),        "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */
1022
{ "wr",        F3(2, 0x32, 0),                F3(~2, ~0x32, ~0)|RD_G0|ASI(~0),        "1,2,w", 0, v6notv9 }, /* wr r,r,%wim */
1023
{ "wr",        F3(2, 0x32, 1),                F3(~2, ~0x32, ~1)|RD_G0,                "1,i,w", 0, v6notv9 }, /* wr r,i,%wim */
1024
{ "wr",        F3(2, 0x32, 0),                F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0),        "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */
1025
{ "wr",        F3(2, 0x33, 0),                F3(~2, ~0x33, ~0)|RD_G0|ASI(~0),        "1,2,t", 0, v6notv9 }, /* wr r,r,%tbr */
1026
{ "wr",        F3(2, 0x33, 1),                F3(~2, ~0x33, ~1)|RD_G0,                "1,i,t", 0, v6notv9 }, /* wr r,i,%tbr */
1027
{ "wr",        F3(2, 0x33, 0),                F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0),        "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */
1028

    
1029
{ "wr", F3(2, 0x30, 0)|RD(2),        F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0),        "1,2,E", 0, v9 }, /* wr r,r,%ccr */
1030
{ "wr", F3(2, 0x30, 1)|RD(2),        F3(~2, ~0x30, ~1)|RD(~2),                "1,i,E", 0, v9 }, /* wr r,i,%ccr */
1031
{ "wr", F3(2, 0x30, 0)|RD(3),        F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0),        "1,2,o", 0, v9 }, /* wr r,r,%asi */
1032
{ "wr", F3(2, 0x30, 1)|RD(3),        F3(~2, ~0x30, ~1)|RD(~3),                "1,i,o", 0, v9 }, /* wr r,i,%asi */
1033
{ "wr", F3(2, 0x30, 0)|RD(6),        F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0),        "1,2,s", 0, v9 }, /* wr r,r,%fprs */
1034
{ "wr", F3(2, 0x30, 1)|RD(6),        F3(~2, ~0x30, ~1)|RD(~6),                "1,i,s", 0, v9 }, /* wr r,i,%fprs */
1035

    
1036
{ "wr", F3(2, 0x30, 0)|RD(16),        F3(~2, ~0x30, ~0)|RD(~16)|ASI(~0),        "1,2,_", 0, v9a }, /* wr r,r,%pcr */
1037
{ "wr", F3(2, 0x30, 1)|RD(16),        F3(~2, ~0x30, ~1)|RD(~16),                "1,i,_", 0, v9a }, /* wr r,i,%pcr */
1038
{ "wr", F3(2, 0x30, 0)|RD(17),        F3(~2, ~0x30, ~0)|RD(~17)|ASI(~0),        "1,2,_", 0, v9a }, /* wr r,r,%pic */
1039
{ "wr", F3(2, 0x30, 1)|RD(17),        F3(~2, ~0x30, ~1)|RD(~17),                "1,i,_", 0, v9a }, /* wr r,i,%pic */
1040
{ "wr", F3(2, 0x30, 0)|RD(18),        F3(~2, ~0x30, ~0)|RD(~18)|ASI(~0),        "1,2,_", 0, v9a }, /* wr r,r,%dcr */
1041
{ "wr", F3(2, 0x30, 1)|RD(18),        F3(~2, ~0x30, ~1)|RD(~18),                "1,i,_", 0, v9a }, /* wr r,i,%dcr */
1042
{ "wr", F3(2, 0x30, 0)|RD(19),        F3(~2, ~0x30, ~0)|RD(~19)|ASI(~0),        "1,2,_", 0, v9a }, /* wr r,r,%gsr */
1043
{ "wr", F3(2, 0x30, 1)|RD(19),        F3(~2, ~0x30, ~1)|RD(~19),                "1,i,_", 0, v9a }, /* wr r,i,%gsr */
1044
{ "wr", F3(2, 0x30, 0)|RD(20),        F3(~2, ~0x30, ~0)|RD(~20)|ASI(~0),        "1,2,_", 0, v9a }, /* wr r,r,%set_softint */
1045
{ "wr", F3(2, 0x30, 1)|RD(20),        F3(~2, ~0x30, ~1)|RD(~20),                "1,i,_", 0, v9a }, /* wr r,i,%set_softint */
1046
{ "wr", F3(2, 0x30, 0)|RD(21),        F3(~2, ~0x30, ~0)|RD(~21)|ASI(~0),        "1,2,_", 0, v9a }, /* wr r,r,%clear_softint */
1047
{ "wr", F3(2, 0x30, 1)|RD(21),        F3(~2, ~0x30, ~1)|RD(~21),                "1,i,_", 0, v9a }, /* wr r,i,%clear_softint */
1048
{ "wr", F3(2, 0x30, 0)|RD(22),        F3(~2, ~0x30, ~0)|RD(~22)|ASI(~0),        "1,2,_", 0, v9a }, /* wr r,r,%softint */
1049
{ "wr", F3(2, 0x30, 1)|RD(22),        F3(~2, ~0x30, ~1)|RD(~22),                "1,i,_", 0, v9a }, /* wr r,i,%softint */
1050
{ "wr", F3(2, 0x30, 0)|RD(23),        F3(~2, ~0x30, ~0)|RD(~23)|ASI(~0),        "1,2,_", 0, v9a }, /* wr r,r,%tick_cmpr */
1051
{ "wr", F3(2, 0x30, 1)|RD(23),        F3(~2, ~0x30, ~1)|RD(~23),                "1,i,_", 0, v9a }, /* wr r,i,%tick_cmpr */
1052
{ "wr", F3(2, 0x30, 0)|RD(24),        F3(~2, ~0x30, ~0)|RD(~24)|ASI(~0),        "1,2,_", 0, v9b }, /* wr r,r,%sys_tick */
1053
{ "wr", F3(2, 0x30, 1)|RD(24),        F3(~2, ~0x30, ~1)|RD(~24),                "1,i,_", 0, v9b }, /* wr r,i,%sys_tick */
1054
{ "wr", F3(2, 0x30, 0)|RD(25),        F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0),        "1,2,_", 0, v9b }, /* wr r,r,%sys_tick_cmpr */
1055
{ "wr", F3(2, 0x30, 1)|RD(25),        F3(~2, ~0x30, ~1)|RD(~25),                "1,i,_", 0, v9b }, /* wr r,i,%sys_tick_cmpr */
1056

    
1057
{ "rd",        F3(2, 0x28, 0),                        F3(~2, ~0x28, ~0)|SIMM13(~0),                "M,d", 0, v8 }, /* rd %asrX,r */
1058
{ "rd",        F3(2, 0x28, 0),                        F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0),        "y,d", 0, v6 }, /* rd %y,r */
1059
{ "rd",        F3(2, 0x29, 0),                        F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0),        "p,d", 0, v6notv9 }, /* rd %psr,r */
1060
{ "rd",        F3(2, 0x2a, 0),                        F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0),        "w,d", 0, v6notv9 }, /* rd %wim,r */
1061
{ "rd",        F3(2, 0x2b, 0),                        F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0),        "t,d", 0, v6notv9 }, /* rd %tbr,r */
1062

    
1063
{ "rd",        F3(2, 0x28, 0)|RS1(2),                F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0),        "E,d", 0, v9 }, /* rd %ccr,r */
1064
{ "rd",        F3(2, 0x28, 0)|RS1(3),                F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0),        "o,d", 0, v9 }, /* rd %asi,r */
1065
{ "rd",        F3(2, 0x28, 0)|RS1(4),                F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0),        "W,d", 0, v9 }, /* rd %tick,r */
1066
{ "rd",        F3(2, 0x28, 0)|RS1(5),                F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0),        "P,d", 0, v9 }, /* rd %pc,r */
1067
{ "rd",        F3(2, 0x28, 0)|RS1(6),                F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0),        "s,d", 0, v9 }, /* rd %fprs,r */
1068

    
1069
{ "rd",        F3(2, 0x28, 0)|RS1(16),                F3(~2, ~0x28, ~0)|RS1(~16)|SIMM13(~0),        "/,d", 0, v9a }, /* rd %pcr,r */
1070
{ "rd",        F3(2, 0x28, 0)|RS1(17),                F3(~2, ~0x28, ~0)|RS1(~17)|SIMM13(~0),        "/,d", 0, v9a }, /* rd %pic,r */
1071
{ "rd",        F3(2, 0x28, 0)|RS1(18),                F3(~2, ~0x28, ~0)|RS1(~18)|SIMM13(~0),        "/,d", 0, v9a }, /* rd %dcr,r */
1072
{ "rd",        F3(2, 0x28, 0)|RS1(19),                F3(~2, ~0x28, ~0)|RS1(~19)|SIMM13(~0),        "/,d", 0, v9a }, /* rd %gsr,r */
1073
{ "rd",        F3(2, 0x28, 0)|RS1(22),                F3(~2, ~0x28, ~0)|RS1(~22)|SIMM13(~0),        "/,d", 0, v9a }, /* rd %softint,r */
1074
{ "rd",        F3(2, 0x28, 0)|RS1(23),                F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0),        "/,d", 0, v9a }, /* rd %tick_cmpr,r */
1075
{ "rd",        F3(2, 0x28, 0)|RS1(24),                F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0),        "/,d", 0, v9b }, /* rd %sys_tick,r */
1076
{ "rd",        F3(2, 0x28, 0)|RS1(25),                F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0),        "/,d", 0, v9b }, /* rd %sys_tick_cmpr,r */
1077

    
1078
{ "rdpr",        F3(2, 0x2a, 0),                F3(~2, ~0x2a, ~0)|SIMM13(~0),        "?,d", 0, v9 },   /* rdpr %priv,r */
1079
{ "wrpr",        F3(2, 0x32, 0),                F3(~2, ~0x32, ~0),                "1,2,!", 0, v9 }, /* wrpr r1,r2,%priv */
1080
{ "wrpr",        F3(2, 0x32, 0),                F3(~2, ~0x32, ~0)|SIMM13(~0),        "1,!", 0, v9 },   /* wrpr r1,%priv */
1081
{ "wrpr",        F3(2, 0x32, 1),                F3(~2, ~0x32, ~1),                "1,i,!", 0, v9 }, /* wrpr r1,i,%priv */
1082
{ "wrpr",        F3(2, 0x32, 1),                F3(~2, ~0x32, ~1),                "i,1,!", F_ALIAS, v9 }, /* wrpr i,r1,%priv */
1083
{ "wrpr",        F3(2, 0x32, 1),                F3(~2, ~0x32, ~1)|RS1(~0),        "i,!", 0, v9 },   /* wrpr i,%priv */
1084

    
1085
/* ??? This group seems wrong.  A three operand move?  */
1086
{ "mov",        F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0),                "1,2,m", F_ALIAS, v8 }, /* wr r,r,%asrX */
1087
{ "mov",        F3(2, 0x30, 1), F3(~2, ~0x30, ~1),                        "1,i,m", F_ALIAS, v8 }, /* wr r,i,%asrX */
1088
{ "mov",        F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0),        "1,2,y", F_ALIAS, v6 }, /* wr r,r,%y */
1089
{ "mov",        F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0,                "1,i,y", F_ALIAS, v6 }, /* wr r,i,%y */
1090
{ "mov",        F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0),        "1,2,p", F_ALIAS, v6notv9 }, /* wr r,r,%psr */
1091
{ "mov",        F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0,                "1,i,p", F_ALIAS, v6notv9 }, /* wr r,i,%psr */
1092
{ "mov",        F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0),        "1,2,w", F_ALIAS, v6notv9 }, /* wr r,r,%wim */
1093
{ "mov",        F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0,                "1,i,w", F_ALIAS, v6notv9 }, /* wr r,i,%wim */
1094
{ "mov",        F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0),        "1,2,t", F_ALIAS, v6notv9 }, /* wr r,r,%tbr */
1095
{ "mov",        F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0,                "1,i,t", F_ALIAS, v6notv9 }, /* wr r,i,%tbr */
1096

    
1097
{ "mov",        F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0),                "M,d", F_ALIAS, v8 }, /* rd %asr1,r */
1098
{ "mov",        F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0),        "y,d", F_ALIAS, v6 }, /* rd %y,r */
1099
{ "mov",        F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0),        "p,d", F_ALIAS, v6notv9 }, /* rd %psr,r */
1100
{ "mov",        F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0),        "w,d", F_ALIAS, v6notv9 }, /* rd %wim,r */
1101
{ "mov",        F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0),        "t,d", F_ALIAS, v6notv9 }, /* rd %tbr,r */
1102

    
1103
{ "mov",        F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0),                "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */
1104
{ "mov",        F3(2, 0x30, 1), F3(~2, ~0x30, ~1),                        "i,m", F_ALIAS, v8 }, /* wr %g0,i,%asrX */
1105
{ "mov",        F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0),                "1,m", F_ALIAS, v8 }, /* wr rs1,0,%asrX */
1106
{ "mov",        F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0),        "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */
1107
{ "mov",        F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0,                "i,y", F_ALIAS, v6 }, /* wr %g0,i,%y */
1108
{ "mov",        F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|SIMM13(~0),        "1,y", F_ALIAS, v6 }, /* wr rs1,0,%y */
1109
{ "mov",        F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0),        "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */
1110
{ "mov",        F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0,                "i,p", F_ALIAS, v6notv9 }, /* wr %g0,i,%psr */
1111
{ "mov",        F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|SIMM13(~0),        "1,p", F_ALIAS, v6notv9 }, /* wr rs1,0,%psr */
1112
{ "mov",        F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0),        "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */
1113
{ "mov",        F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0,                "i,w", F_ALIAS, v6notv9 }, /* wr %g0,i,%wim */
1114
{ "mov",        F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|SIMM13(~0),        "1,w", F_ALIAS, v6notv9 }, /* wr rs1,0,%wim */
1115
{ "mov",        F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0),        "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */
1116
{ "mov",        F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0,                "i,t", F_ALIAS, v6notv9 }, /* wr %g0,i,%tbr */
1117
{ "mov",        F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|SIMM13(~0),        "1,t", F_ALIAS, v6notv9 }, /* wr rs1,0,%tbr */
1118

    
1119
{ "mov",        F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0),        "2,d", 0, v6 }, /* or %g0,rs2,d */
1120
{ "mov",        F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0,                "i,d", 0, v6 }, /* or %g0,i,d        */
1121
{ "mov",        F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0),                "1,d", 0, v6 }, /* or rs1,%g0,d   */
1122
{ "mov",        F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0),                "1,d", 0, v6 }, /* or rs1,0,d */
1123

    
1124
{ "or",        F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0),        "1,2,d", 0, v6 },
1125
{ "or",        F3(2, 0x02, 1), F3(~2, ~0x02, ~1),                "1,i,d", 0, v6 },
1126
{ "or",        F3(2, 0x02, 1), F3(~2, ~0x02, ~1),                "i,1,d", 0, v6 },
1127

    
1128
{ "bset",        F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0),        "2,r", F_ALIAS, v6 },        /* or rd,rs2,rd */
1129
{ "bset",        F3(2, 0x02, 1), F3(~2, ~0x02, ~1),                "i,r", F_ALIAS, v6 },        /* or rd,i,rd */
1130

    
1131
/* This is not a commutative instruction.  */
1132
{ "andn",        F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0),        "1,2,d", 0, v6 },
1133
{ "andn",        F3(2, 0x05, 1), F3(~2, ~0x05, ~1),                "1,i,d", 0, v6 },
1134

    
1135
/* This is not a commutative instruction.  */
1136
{ "andncc",        F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0),        "1,2,d", 0, v6 },
1137
{ "andncc",        F3(2, 0x15, 1), F3(~2, ~0x15, ~1),                "1,i,d", 0, v6 },
1138

    
1139
{ "bclr",        F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0),        "2,r", F_ALIAS, v6 },        /* andn rd,rs2,rd */
1140
{ "bclr",        F3(2, 0x05, 1), F3(~2, ~0x05, ~1),                "i,r", F_ALIAS, v6 },        /* andn rd,i,rd */
1141

    
1142
{ "cmp",        F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0|ASI(~0),        "1,2", 0, v6 },        /* subcc rs1,rs2,%g0 */
1143
{ "cmp",        F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0,                "1,i", 0, v6 },        /* subcc rs1,i,%g0 */
1144

    
1145
{ "sub",        F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0),        "1,2,d", 0, v6 },
1146
{ "sub",        F3(2, 0x04, 1), F3(~2, ~0x04, ~1),                "1,i,d", 0, v6 },
1147

    
1148
{ "subcc",        F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0),        "1,2,d", 0, v6 },
1149
{ "subcc",        F3(2, 0x14, 1), F3(~2, ~0x14, ~1),                "1,i,d", 0, v6 },
1150

    
1151
{ "subx",        F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0),        "1,2,d", 0, v6notv9 },
1152
{ "subx",        F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1),                "1,i,d", 0, v6notv9 },
1153
{ "subc",        F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0),        "1,2,d", 0, v9 },
1154
{ "subc",        F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1),                "1,i,d", 0, v9 },
1155

    
1156
{ "subxcc",        F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0),        "1,2,d", 0, v6notv9 },
1157
{ "subxcc",        F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1),                "1,i,d", 0, v6notv9 },
1158
{ "subccc",        F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0),        "1,2,d", 0, v9 },
1159
{ "subccc",        F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1),                "1,i,d", 0, v9 },
1160

    
1161
{ "and",        F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0),        "1,2,d", 0, v6 },
1162
{ "and",        F3(2, 0x01, 1), F3(~2, ~0x01, ~1),                "1,i,d", 0, v6 },
1163
{ "and",        F3(2, 0x01, 1), F3(~2, ~0x01, ~1),                "i,1,d", 0, v6 },
1164

    
1165
{ "andcc",        F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0),        "1,2,d", 0, v6 },
1166
{ "andcc",        F3(2, 0x11, 1), F3(~2, ~0x11, ~1),                "1,i,d", 0, v6 },
1167
{ "andcc",        F3(2, 0x11, 1), F3(~2, ~0x11, ~1),                "i,1,d", 0, v6 },
1168

    
1169
{ "dec",        F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 },        /* sub rd,1,rd */
1170
{ "dec",        F3(2, 0x04, 1),                    F3(~2, ~0x04, ~1),                       "i,r", F_ALIAS, v8 },        /* sub rd,imm,rd */
1171
{ "deccc",        F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 },        /* subcc rd,1,rd */
1172
{ "deccc",        F3(2, 0x14, 1),                    F3(~2, ~0x14, ~1),                       "i,r", F_ALIAS, v8 },        /* subcc rd,imm,rd */
1173
{ "inc",        F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 },        /* add rd,1,rd */
1174
{ "inc",        F3(2, 0x00, 1),                    F3(~2, ~0x00, ~1),                       "i,r", F_ALIAS, v8 },        /* add rd,imm,rd */
1175
{ "inccc",        F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 },        /* addcc rd,1,rd */
1176
{ "inccc",        F3(2, 0x10, 1),                    F3(~2, ~0x10, ~1),                       "i,r", F_ALIAS, v8 },        /* addcc rd,imm,rd */
1177

    
1178
{ "btst",        F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0|ASI(~0), "1,2", F_ALIAS, v6 },        /* andcc rs1,rs2,%g0 */
1179
{ "btst",        F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0, "i,1", F_ALIAS, v6 },        /* andcc rs1,i,%g0 */
1180

    
1181
{ "neg",        F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "2,d", F_ALIAS, v6 }, /* sub %g0,rs2,rd */
1182
{ "neg",        F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "O", F_ALIAS, v6 }, /* sub %g0,rd,rd */
1183

    
1184
{ "add",        F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0),        "1,2,d", 0, v6 },
1185
{ "add",        F3(2, 0x00, 1), F3(~2, ~0x00, ~1),                "1,i,d", 0, v6 },
1186
{ "add",        F3(2, 0x00, 1), F3(~2, ~0x00, ~1),                "i,1,d", 0, v6 },
1187
{ "addcc",        F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0),        "1,2,d", 0, v6 },
1188
{ "addcc",        F3(2, 0x10, 1), F3(~2, ~0x10, ~1),                "1,i,d", 0, v6 },
1189
{ "addcc",        F3(2, 0x10, 1), F3(~2, ~0x10, ~1),                "i,1,d", 0, v6 },
1190

    
1191
{ "addx",        F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0),        "1,2,d", 0, v6notv9 },
1192
{ "addx",        F3(2, 0x08, 1), F3(~2, ~0x08, ~1),                "1,i,d", 0, v6notv9 },
1193
{ "addx",        F3(2, 0x08, 1), F3(~2, ~0x08, ~1),                "i,1,d", 0, v6notv9 },
1194
{ "addc",        F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0),        "1,2,d", 0, v9 },
1195
{ "addc",        F3(2, 0x08, 1), F3(~2, ~0x08, ~1),                "1,i,d", 0, v9 },
1196
{ "addc",        F3(2, 0x08, 1), F3(~2, ~0x08, ~1),                "i,1,d", 0, v9 },
1197

    
1198
{ "addxcc",        F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0),        "1,2,d", 0, v6notv9 },
1199
{ "addxcc",        F3(2, 0x18, 1), F3(~2, ~0x18, ~1),                "1,i,d", 0, v6notv9 },
1200
{ "addxcc",        F3(2, 0x18, 1), F3(~2, ~0x18, ~1),                "i,1,d", 0, v6notv9 },
1201
{ "addccc",        F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0),        "1,2,d", 0, v9 },
1202
{ "addccc",        F3(2, 0x18, 1), F3(~2, ~0x18, ~1),                "1,i,d", 0, v9 },
1203
{ "addccc",        F3(2, 0x18, 1), F3(~2, ~0x18, ~1),                "i,1,d", 0, v9 },
1204

    
1205
{ "smul",        F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0),        "1,2,d", 0, v8 },
1206
{ "smul",        F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1),                "1,i,d", 0, v8 },
1207
{ "smul",        F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1),                "i,1,d", 0, v8 },
1208
{ "smulcc",        F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0),        "1,2,d", 0, v8 },
1209
{ "smulcc",        F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1),                "1,i,d", 0, v8 },
1210
{ "smulcc",        F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1),                "i,1,d", 0, v8 },
1211
{ "umul",        F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0),        "1,2,d", 0, v8 },
1212
{ "umul",        F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1),                "1,i,d", 0, v8 },
1213
{ "umul",        F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1),                "i,1,d", 0, v8 },
1214
{ "umulcc",        F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0),        "1,2,d", 0, v8 },
1215
{ "umulcc",        F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1),                "1,i,d", 0, v8 },
1216
{ "umulcc",        F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1),                "i,1,d", 0, v8 },
1217
{ "sdiv",        F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0),        "1,2,d", 0, v8 },
1218
{ "sdiv",        F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1),                "1,i,d", 0, v8 },
1219
{ "sdiv",        F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1),                "i,1,d", 0, v8 },
1220
{ "sdivcc",        F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0),        "1,2,d", 0, v8 },
1221
{ "sdivcc",        F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1),                "1,i,d", 0, v8 },
1222
{ "sdivcc",        F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1),                "i,1,d", 0, v8 },
1223
{ "udiv",        F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0),        "1,2,d", 0, v8 },
1224
{ "udiv",        F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1),                "1,i,d", 0, v8 },
1225
{ "udiv",        F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1),                "i,1,d", 0, v8 },
1226
{ "udivcc",        F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0),        "1,2,d", 0, v8 },
1227
{ "udivcc",        F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1),                "1,i,d", 0, v8 },
1228
{ "udivcc",        F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1),                "i,1,d", 0, v8 },
1229

    
1230
{ "mulx",        F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0),        "1,2,d", 0, v9 },
1231
{ "mulx",        F3(2, 0x09, 1), F3(~2, ~0x09, ~1),                "1,i,d", 0, v9 },
1232
{ "sdivx",        F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0),        "1,2,d", 0, v9 },
1233
{ "sdivx",        F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1),                "1,i,d", 0, v9 },
1234
{ "udivx",        F3(2, 0x0d, 0), F3(~2, ~0x0d, ~0)|ASI(~0),        "1,2,d", 0, v9 },
1235
{ "udivx",        F3(2, 0x0d, 1), F3(~2, ~0x0d, ~1),                "1,i,d", 0, v9 },
1236

    
1237
{ "call",        F1(0x1), F1(~0x1), "L", F_JSR|F_DELAYED, v6 },
1238
{ "call",        F1(0x1), F1(~0x1), "L,#", F_JSR|F_DELAYED, v6 },
1239

    
1240
{ "call",        F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0),        "1+2", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%o7 */
1241
{ "call",        F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0),        "1+2,#", F_JSR|F_DELAYED, v6 },
1242
{ "call",        F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0),        "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%o7 */
1243
{ "call",        F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0),        "1,#", F_JSR|F_DELAYED, v6 },
1244
{ "call",        F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),                "1+i", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+i,%o7 */
1245
{ "call",        F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),                "1+i,#", F_JSR|F_DELAYED, v6 },
1246
{ "call",        F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),                "i+1", F_JSR|F_DELAYED, v6 }, /* jmpl i+rs1,%o7 */
1247
{ "call",        F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),                "i+1,#", F_JSR|F_DELAYED, v6 },
1248
{ "call",        F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0,        "i", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,%o7 */
1249
{ "call",        F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0,        "i,#", F_JSR|F_DELAYED, v6 },
1250
{ "call",        F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0),        "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,%o7 */
1251
{ "call",        F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0),        "1,#", F_JSR|F_DELAYED, v6 },
1252

    
1253

    
1254
/* Conditional instructions.
1255

1256
   Because this part of the table was such a mess earlier, I have
1257
   macrofied it so that all the branches and traps are generated from
1258
   a single-line description of each condition value.  John Gilmore. */
1259

    
1260
/* Define branches -- one annulled, one without, etc. */
1261
#define br(opcode, mask, lose, flags) \
1262
 { opcode, (mask)|ANNUL, (lose),       ",a l",   (flags), v6 }, \
1263
 { opcode, (mask)      , (lose)|ANNUL, "l",     (flags), v6 }
1264

    
1265
#define brx(opcode, mask, lose, flags) /* v9 */ \
1266
 { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), "Z,G",      (flags), v9 }, \
1267
 { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), ",T Z,G",   (flags), v9 }, \
1268
 { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a Z,G",   (flags), v9 }, \
1269
 { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a,T Z,G", (flags), v9 }, \
1270
 { opcode, (mask)|(2<<20), ANNUL|BPRED|(lose), ",N Z,G",   (flags), v9 }, \
1271
 { opcode, (mask)|(2<<20)|ANNUL, BPRED|(lose), ",a,N Z,G", (flags), v9 }, \
1272
 { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), "z,G",      (flags), v9 }, \
1273
 { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), ",T z,G",   (flags), v9 }, \
1274
 { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a z,G",   (flags), v9 }, \
1275
 { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a,T z,G", (flags), v9 }, \
1276
 { opcode, (mask), ANNUL|BPRED|(lose)|(2<<20), ",N z,G",   (flags), v9 }, \
1277
 { opcode, (mask)|ANNUL, BPRED|(lose)|(2<<20), ",a,N z,G", (flags), v9 }
1278

    
1279
/* Define four traps: reg+reg, reg + immediate, immediate alone, reg alone. */
1280
#define tr(opcode, mask, lose, flags) \
1281
 { opcode, (mask)|(2<<11)|IMMED, (lose)|RS1_G0,        "Z,i",   (flags), v9 }, /* %g0 + imm */ \
1282
 { opcode, (mask)|(2<<11)|IMMED, (lose),        "Z,1+i", (flags), v9 }, /* rs1 + imm */ \
1283
 { opcode, (mask)|(2<<11), IMMED|(lose),        "Z,1+2", (flags), v9 }, /* rs1 + rs2 */ \
1284
 { opcode, (mask)|(2<<11), IMMED|(lose)|RS2_G0,        "Z,1",   (flags), v9 }, /* rs1 + %g0 */ \
1285
 { opcode, (mask)|IMMED, (lose)|RS1_G0,        "z,i",   (flags)|F_ALIAS, v9 }, /* %g0 + imm */ \
1286
 { opcode, (mask)|IMMED, (lose),        "z,1+i", (flags)|F_ALIAS, v9 }, /* rs1 + imm */ \
1287
 { opcode, (mask), IMMED|(lose),        "z,1+2", (flags)|F_ALIAS, v9 }, /* rs1 + rs2 */ \
1288
 { opcode, (mask), IMMED|(lose)|RS2_G0,        "z,1",   (flags)|F_ALIAS, v9 }, /* rs1 + %g0 */ \
1289
 { opcode, (mask)|IMMED, (lose)|RS1_G0,                "i",     (flags), v6 }, /* %g0 + imm */ \
1290
 { opcode, (mask)|IMMED, (lose),                "1+i",   (flags), v6 }, /* rs1 + imm */ \
1291
 { opcode, (mask), IMMED|(lose),                "1+2",   (flags), v6 }, /* rs1 + rs2 */ \
1292
 { opcode, (mask), IMMED|(lose)|RS2_G0,                "1",     (flags), v6 } /* rs1 + %g0 */
1293

    
1294
/* v9: We must put `brx' before `br', to ensure that we never match something
1295
   v9: against an expression unless it is an expression.  Otherwise, we end
1296
   v9: up with undefined symbol tables entries, because they get added, but
1297
   v9: are not deleted if the pattern fails to match.  */
1298

    
1299
/* Define both branches and traps based on condition mask */
1300
#define cond(bop, top, mask, flags) \
1301
  brx(bop, F2(0, 1)|(mask), F2(~0, ~1)|((~mask)&COND(~0)), F_DELAYED|(flags)), /* v9 */ \
1302
  br(bop,  F2(0, 2)|(mask), F2(~0, ~2)|((~mask)&COND(~0)), F_DELAYED|(flags)), \
1303
  tr(top,  F3(2, 0x3a, 0)|(mask), F3(~2, ~0x3a, 0)|((~mask)&COND(~0)), ((flags) & ~(F_UNBR|F_CONDBR)))
1304

    
1305
/* Define all the conditions, all the branches, all the traps.  */
1306

    
1307
/* Standard branch, trap mnemonics */
1308
cond ("b",        "ta",   CONDA, F_UNBR),
1309
/* Alternative form (just for assembly, not for disassembly) */
1310
cond ("ba",        "t",    CONDA, F_UNBR|F_ALIAS),
1311

    
1312
cond ("bcc",        "tcc",  CONDCC, F_CONDBR),
1313
cond ("bcs",        "tcs",  CONDCS, F_CONDBR),
1314
cond ("be",        "te",   CONDE, F_CONDBR),
1315
cond ("beq",        "teq",  CONDE, F_CONDBR|F_ALIAS),
1316
cond ("bg",        "tg",   CONDG, F_CONDBR),
1317
cond ("bgt",        "tgt",  CONDG, F_CONDBR|F_ALIAS),
1318
cond ("bge",        "tge",  CONDGE, F_CONDBR),
1319
cond ("bgeu",        "tgeu", CONDGEU, F_CONDBR|F_ALIAS), /* for cc */
1320
cond ("bgu",        "tgu",  CONDGU, F_CONDBR),
1321
cond ("bl",        "tl",   CONDL, F_CONDBR),
1322
cond ("blt",        "tlt",  CONDL, F_CONDBR|F_ALIAS),
1323
cond ("ble",        "tle",  CONDLE, F_CONDBR),
1324
cond ("bleu",        "tleu", CONDLEU, F_CONDBR),
1325
cond ("blu",        "tlu",  CONDLU, F_CONDBR|F_ALIAS), /* for cs */
1326
cond ("bn",        "tn",   CONDN, F_CONDBR),
1327
cond ("bne",        "tne",  CONDNE, F_CONDBR),
1328
cond ("bneg",        "tneg", CONDNEG, F_CONDBR),
1329
cond ("bnz",        "tnz",  CONDNZ, F_CONDBR|F_ALIAS), /* for ne */
1330
cond ("bpos",        "tpos", CONDPOS, F_CONDBR),
1331
cond ("bvc",        "tvc",  CONDVC, F_CONDBR),
1332
cond ("bvs",        "tvs",  CONDVS, F_CONDBR),
1333
cond ("bz",        "tz",   CONDZ, F_CONDBR|F_ALIAS), /* for e */
1334

    
1335
#undef cond
1336
#undef br
1337
#undef brr /* v9 */
1338
#undef tr
1339

    
1340
#define brr(opcode, mask, lose, flags) /* v9 */ \
1341
 { opcode, (mask)|BPRED, ANNUL|(lose), "1,k",      F_DELAYED|(flags), v9 }, \
1342
 { opcode, (mask)|BPRED, ANNUL|(lose), ",T 1,k",   F_DELAYED|(flags), v9 }, \
1343
 { opcode, (mask)|BPRED|ANNUL, (lose), ",a 1,k",   F_DELAYED|(flags), v9 }, \
1344
 { opcode, (mask)|BPRED|ANNUL, (lose), ",a,T 1,k", F_DELAYED|(flags), v9 }, \
1345
 { opcode, (mask), ANNUL|BPRED|(lose), ",N 1,k",   F_DELAYED|(flags), v9 }, \
1346
 { opcode, (mask)|ANNUL, BPRED|(lose), ",a,N 1,k", F_DELAYED|(flags), v9 }
1347

    
1348
#define condr(bop, mask, flags) /* v9 */ \
1349
  brr(bop, F2(0, 3)|COND(mask), F2(~0, ~3)|COND(~(mask)), (flags)) /* v9 */
1350

    
1351
/* v9 */ condr("brnz", 0x5, F_CONDBR),
1352
/* v9 */ condr("brz", 0x1, F_CONDBR),
1353
/* v9 */ condr("brgez", 0x7, F_CONDBR),
1354
/* v9 */ condr("brlz", 0x3, F_CONDBR),
1355
/* v9 */ condr("brlez", 0x2, F_CONDBR),
1356
/* v9 */ condr("brgz", 0x6, F_CONDBR),
1357

    
1358
#undef condr /* v9 */
1359
#undef brr /* v9 */
1360

    
1361
#define movr(opcode, mask, flags) /* v9 */ \
1362
 { opcode, F3(2, 0x2f, 0)|RCOND(mask), F3(~2, ~0x2f, ~0)|RCOND(~(mask)), "1,2,d", (flags), v9 }, \
1363
 { opcode, F3(2, 0x2f, 1)|RCOND(mask), F3(~2, ~0x2f, ~1)|RCOND(~(mask)), "1,j,d", (flags), v9 }
1364

    
1365
#define fmrrs(opcode, mask, lose, flags) /* v9 */ \
1366
 { opcode, (mask), (lose), "1,f,g", (flags) | F_FLOAT, v9 }
1367
#define fmrrd(opcode, mask, lose, flags) /* v9 */ \
1368
 { opcode, (mask), (lose), "1,B,H", (flags) | F_FLOAT, v9 }
1369
#define fmrrq(opcode, mask, lose, flags) /* v9 */ \
1370
 { opcode, (mask), (lose), "1,R,J", (flags) | F_FLOAT, v9 }
1371

    
1372
#define fmovrs(mop, mask, flags) /* v9 */ \
1373
  fmrrs(mop, F3(2, 0x35, 0)|OPF_LOW5(5)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~5)|RCOND(~(mask)), (flags)) /* v9 */
1374
#define fmovrd(mop, mask, flags) /* v9 */ \
1375
  fmrrd(mop, F3(2, 0x35, 0)|OPF_LOW5(6)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~6)|RCOND(~(mask)), (flags)) /* v9 */
1376
#define fmovrq(mop, mask, flags) /* v9 */ \
1377
  fmrrq(mop, F3(2, 0x35, 0)|OPF_LOW5(7)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~7)|RCOND(~(mask)), (flags)) /* v9 */
1378

    
1379
/* v9 */ movr("movrne", 0x5, 0),
1380
/* v9 */ movr("movre", 0x1, 0),
1381
/* v9 */ movr("movrgez", 0x7, 0),
1382
/* v9 */ movr("movrlz", 0x3, 0),
1383
/* v9 */ movr("movrlez", 0x2, 0),
1384
/* v9 */ movr("movrgz", 0x6, 0),
1385
/* v9 */ movr("movrnz", 0x5, F_ALIAS),
1386
/* v9 */ movr("movrz", 0x1, F_ALIAS),
1387

    
1388
/* v9 */ fmovrs("fmovrsne", 0x5, 0),
1389
/* v9 */ fmovrs("fmovrse", 0x1, 0),
1390
/* v9 */ fmovrs("fmovrsgez", 0x7, 0),
1391
/* v9 */ fmovrs("fmovrslz", 0x3, 0),
1392
/* v9 */ fmovrs("fmovrslez", 0x2, 0),
1393
/* v9 */ fmovrs("fmovrsgz", 0x6, 0),
1394
/* v9 */ fmovrs("fmovrsnz", 0x5, F_ALIAS),
1395
/* v9 */ fmovrs("fmovrsz", 0x1, F_ALIAS),
1396

    
1397
/* v9 */ fmovrd("fmovrdne", 0x5, 0),
1398
/* v9 */ fmovrd("fmovrde", 0x1, 0),
1399
/* v9 */ fmovrd("fmovrdgez", 0x7, 0),
1400
/* v9 */ fmovrd("fmovrdlz", 0x3, 0),
1401
/* v9 */ fmovrd("fmovrdlez", 0x2, 0),
1402
/* v9 */ fmovrd("fmovrdgz", 0x6, 0),
1403
/* v9 */ fmovrd("fmovrdnz", 0x5, F_ALIAS),
1404
/* v9 */ fmovrd("fmovrdz", 0x1, F_ALIAS),
1405

    
1406
/* v9 */ fmovrq("fmovrqne", 0x5, 0),
1407
/* v9 */ fmovrq("fmovrqe", 0x1, 0),
1408
/* v9 */ fmovrq("fmovrqgez", 0x7, 0),
1409
/* v9 */ fmovrq("fmovrqlz", 0x3, 0),
1410
/* v9 */ fmovrq("fmovrqlez", 0x2, 0),
1411
/* v9 */ fmovrq("fmovrqgz", 0x6, 0),
1412
/* v9 */ fmovrq("fmovrqnz", 0x5, F_ALIAS),
1413
/* v9 */ fmovrq("fmovrqz", 0x1, F_ALIAS),
1414

    
1415
#undef movr /* v9 */
1416
#undef fmovr /* v9 */
1417
#undef fmrr /* v9 */
1418

    
1419
#define movicc(opcode, cond, flags) /* v9 */ \
1420
  { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|XCC|(1<<11), "z,2,d", flags, v9 }, \
1421
  { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|XCC|(1<<11), "z,I,d", flags, v9 }, \
1422
  { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|(1<<11),     "Z,2,d", flags, v9 }, \
1423
  { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|(1<<11),     "Z,I,d", flags, v9 }
1424

    
1425
#define movfcc(opcode, fcond, flags) /* v9 */ \
1426
  { opcode, F3(2, 0x2c, 0)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~0), "6,2,d", flags, v9 }, \
1427
  { opcode, F3(2, 0x2c, 1)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~1), "6,I,d", flags, v9 }, \
1428
  { opcode, F3(2, 0x2c, 0)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~0), "7,2,d", flags, v9 }, \
1429
  { opcode, F3(2, 0x2c, 1)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~1), "7,I,d", flags, v9 }, \
1430
  { opcode, F3(2, 0x2c, 0)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~0), "8,2,d", flags, v9 }, \
1431
  { opcode, F3(2, 0x2c, 1)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~1), "8,I,d", flags, v9 }, \
1432
  { opcode, F3(2, 0x2c, 0)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~0), "9,2,d", flags, v9 }, \
1433
  { opcode, F3(2, 0x2c, 1)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~1), "9,I,d", flags, v9 }
1434

    
1435
#define movcc(opcode, cond, fcond, flags) /* v9 */ \
1436
  movfcc (opcode, fcond, flags), /* v9 */ \
1437
  movicc (opcode, cond, flags) /* v9 */
1438

    
1439
/* v9 */ movcc  ("mova",        CONDA, FCONDA, 0),
1440
/* v9 */ movicc ("movcc",        CONDCC, 0),
1441
/* v9 */ movicc ("movgeu",        CONDGEU, F_ALIAS),
1442
/* v9 */ movicc ("movcs",        CONDCS, 0),
1443
/* v9 */ movicc ("movlu",        CONDLU, F_ALIAS),
1444
/* v9 */ movcc  ("move",        CONDE, FCONDE, 0),
1445
/* v9 */ movcc  ("movg",        CONDG, FCONDG, 0),
1446
/* v9 */ movcc  ("movge",        CONDGE, FCONDGE, 0),
1447
/* v9 */ movicc ("movgu",        CONDGU, 0),
1448
/* v9 */ movcc  ("movl",        CONDL, FCONDL, 0),
1449
/* v9 */ movcc  ("movle",        CONDLE, FCONDLE, 0),
1450
/* v9 */ movicc ("movleu",        CONDLEU, 0),
1451
/* v9 */ movfcc ("movlg",        FCONDLG, 0),
1452
/* v9 */ movcc  ("movn",        CONDN, FCONDN, 0),
1453
/* v9 */ movcc  ("movne",        CONDNE, FCONDNE, 0),
1454
/* v9 */ movicc ("movneg",        CONDNEG, 0),
1455
/* v9 */ movcc  ("movnz",        CONDNZ, FCONDNZ, F_ALIAS),
1456
/* v9 */ movfcc ("movo",        FCONDO, 0),
1457
/* v9 */ movicc ("movpos",        CONDPOS, 0),
1458
/* v9 */ movfcc ("movu",        FCONDU, 0),
1459
/* v9 */ movfcc ("movue",        FCONDUE, 0),
1460
/* v9 */ movfcc ("movug",        FCONDUG, 0),
1461
/* v9 */ movfcc ("movuge",        FCONDUGE, 0),
1462
/* v9 */ movfcc ("movul",        FCONDUL, 0),
1463
/* v9 */ movfcc ("movule",        FCONDULE, 0),
1464
/* v9 */ movicc ("movvc",        CONDVC, 0),
1465
/* v9 */ movicc ("movvs",        CONDVS, 0),
1466
/* v9 */ movcc  ("movz",        CONDZ, FCONDZ, F_ALIAS),
1467

    
1468
#undef movicc /* v9 */
1469
#undef movfcc /* v9 */
1470
#undef movcc /* v9 */
1471

    
1472
#define FM_SF 1                /* v9 - values for fpsize */
1473
#define FM_DF 2                /* v9 */
1474
#define FM_QF 3                /* v9 */
1475

    
1476
#define fmovicc(opcode, fpsize, cond, flags) /* v9 */ \
1477
{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0),  F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0),  "z,f,g", flags, v9 }, \
1478
{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0),  F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0),  "Z,f,g", flags, v9 }
1479

    
1480
#define fmovfcc(opcode, fpsize, fcond, flags) /* v9 */ \
1481
{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6,f,g", flags, v9 }, \
1482
{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7,f,g", flags, v9 }, \
1483
{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8,f,g", flags, v9 }, \
1484
{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9,f,g", flags, v9 }
1485

    
1486
/* FIXME: use fmovicc/fmovfcc? */ /* v9 */
1487
#define fmovcc(opcode, fpsize, cond, fcond, flags) /* v9 */ \
1488
{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0),  F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0),  "z,f,g", flags | F_FLOAT, v9 }, \
1489
{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6,f,g", flags | F_FLOAT, v9 }, \
1490
{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0),  F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0),  "Z,f,g", flags | F_FLOAT, v9 }, \
1491
{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7,f,g", flags | F_FLOAT, v9 }, \
1492
{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8,f,g", flags | F_FLOAT, v9 }, \
1493
{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9,f,g", flags | F_FLOAT, v9 }
1494

    
1495
/* v9 */ fmovcc  ("fmovda",        FM_DF, CONDA, FCONDA, 0),
1496
/* v9 */ fmovcc  ("fmovqa",        FM_QF, CONDA, FCONDA, 0),
1497
/* v9 */ fmovcc  ("fmovsa",        FM_SF, CONDA, FCONDA, 0),
1498
/* v9 */ fmovicc ("fmovdcc",        FM_DF, CONDCC, 0),
1499
/* v9 */ fmovicc ("fmovqcc",        FM_QF, CONDCC, 0),
1500
/* v9 */ fmovicc ("fmovscc",        FM_SF, CONDCC, 0),
1501
/* v9 */ fmovicc ("fmovdcs",        FM_DF, CONDCS, 0),
1502
/* v9 */ fmovicc ("fmovqcs",        FM_QF, CONDCS, 0),
1503
/* v9 */ fmovicc ("fmovscs",        FM_SF, CONDCS, 0),
1504
/* v9 */ fmovcc  ("fmovde",        FM_DF, CONDE, FCONDE, 0),
1505
/* v9 */ fmovcc  ("fmovqe",        FM_QF, CONDE, FCONDE, 0),
1506
/* v9 */ fmovcc  ("fmovse",        FM_SF, CONDE, FCONDE, 0),
1507
/* v9 */ fmovcc  ("fmovdg",        FM_DF, CONDG, FCONDG, 0),
1508
/* v9 */ fmovcc  ("fmovqg",        FM_QF, CONDG, FCONDG, 0),
1509
/* v9 */ fmovcc  ("fmovsg",        FM_SF, CONDG, FCONDG, 0),
1510
/* v9 */ fmovcc  ("fmovdge",        FM_DF, CONDGE, FCONDGE, 0),
1511
/* v9 */ fmovcc  ("fmovqge",        FM_QF, CONDGE, FCONDGE, 0),
1512
/* v9 */ fmovcc  ("fmovsge",        FM_SF, CONDGE, FCONDGE, 0),
1513
/* v9 */ fmovicc ("fmovdgeu",        FM_DF, CONDGEU, F_ALIAS),
1514
/* v9 */ fmovicc ("fmovqgeu",        FM_QF, CONDGEU, F_ALIAS),
1515
/* v9 */ fmovicc ("fmovsgeu",        FM_SF, CONDGEU, F_ALIAS),
1516
/* v9 */ fmovicc ("fmovdgu",        FM_DF, CONDGU, 0),
1517
/* v9 */ fmovicc ("fmovqgu",        FM_QF, CONDGU, 0),
1518
/* v9 */ fmovicc ("fmovsgu",        FM_SF, CONDGU, 0),
1519
/* v9 */ fmovcc  ("fmovdl",        FM_DF, CONDL, FCONDL, 0),
1520
/* v9 */ fmovcc  ("fmovql",        FM_QF, CONDL, FCONDL, 0),
1521
/* v9 */ fmovcc  ("fmovsl",        FM_SF, CONDL, FCONDL, 0),
1522
/* v9 */ fmovcc  ("fmovdle",        FM_DF, CONDLE, FCONDLE, 0),
1523
/* v9 */ fmovcc  ("fmovqle",        FM_QF, CONDLE, FCONDLE, 0),
1524
/* v9 */ fmovcc  ("fmovsle",        FM_SF, CONDLE, FCONDLE, 0),
1525
/* v9 */ fmovicc ("fmovdleu",        FM_DF, CONDLEU, 0),
1526
/* v9 */ fmovicc ("fmovqleu",        FM_QF, CONDLEU, 0),
1527
/* v9 */ fmovicc ("fmovsleu",        FM_SF, CONDLEU, 0),
1528
/* v9 */ fmovfcc ("fmovdlg",        FM_DF, FCONDLG, 0),
1529
/* v9 */ fmovfcc ("fmovqlg",        FM_QF, FCONDLG, 0),
1530
/* v9 */ fmovfcc ("fmovslg",        FM_SF, FCONDLG, 0),
1531
/* v9 */ fmovicc ("fmovdlu",        FM_DF, CONDLU, F_ALIAS),
1532
/* v9 */ fmovicc ("fmovqlu",        FM_QF, CONDLU, F_ALIAS),
1533
/* v9 */ fmovicc ("fmovslu",        FM_SF, CONDLU, F_ALIAS),
1534
/* v9 */ fmovcc  ("fmovdn",        FM_DF, CONDN, FCONDN, 0),
1535
/* v9 */ fmovcc  ("fmovqn",        FM_QF, CONDN, FCONDN, 0),
1536
/* v9 */ fmovcc  ("fmovsn",        FM_SF, CONDN, FCONDN, 0),
1537
/* v9 */ fmovcc  ("fmovdne",        FM_DF, CONDNE, FCONDNE, 0),
1538
/* v9 */ fmovcc  ("fmovqne",        FM_QF, CONDNE, FCONDNE, 0),
1539
/* v9 */ fmovcc  ("fmovsne",        FM_SF, CONDNE, FCONDNE, 0),
1540
/* v9 */ fmovicc ("fmovdneg",        FM_DF, CONDNEG, 0),
1541
/* v9 */ fmovicc ("fmovqneg",        FM_QF, CONDNEG, 0),
1542
/* v9 */ fmovicc ("fmovsneg",        FM_SF, CONDNEG, 0),
1543
/* v9 */ fmovcc  ("fmovdnz",        FM_DF, CONDNZ, FCONDNZ, F_ALIAS),
1544
/* v9 */ fmovcc  ("fmovqnz",        FM_QF, CONDNZ, FCONDNZ, F_ALIAS),
1545
/* v9 */ fmovcc  ("fmovsnz",        FM_SF, CONDNZ, FCONDNZ, F_ALIAS),
1546
/* v9 */ fmovfcc ("fmovdo",        FM_DF, FCONDO, 0),
1547
/* v9 */ fmovfcc ("fmovqo",        FM_QF, FCONDO, 0),
1548
/* v9 */ fmovfcc ("fmovso",        FM_SF, FCONDO, 0),
1549
/* v9 */ fmovicc ("fmovdpos",        FM_DF, CONDPOS, 0),
1550
/* v9 */ fmovicc ("fmovqpos",        FM_QF, CONDPOS, 0),
1551
/* v9 */ fmovicc ("fmovspos",        FM_SF, CONDPOS, 0),
1552
/* v9 */ fmovfcc ("fmovdu",        FM_DF, FCONDU, 0),
1553
/* v9 */ fmovfcc ("fmovqu",        FM_QF, FCONDU, 0),
1554
/* v9 */ fmovfcc ("fmovsu",        FM_SF, FCONDU, 0),
1555
/* v9 */ fmovfcc ("fmovdue",        FM_DF, FCONDUE, 0),
1556
/* v9 */ fmovfcc ("fmovque",        FM_QF, FCONDUE, 0),
1557
/* v9 */ fmovfcc ("fmovsue",        FM_SF, FCONDUE, 0),
1558
/* v9 */ fmovfcc ("fmovdug",        FM_DF, FCONDUG, 0),
1559
/* v9 */ fmovfcc ("fmovqug",        FM_QF, FCONDUG, 0),
1560
/* v9 */ fmovfcc ("fmovsug",        FM_SF, FCONDUG, 0),
1561
/* v9 */ fmovfcc ("fmovduge",        FM_DF, FCONDUGE, 0),
1562
/* v9 */ fmovfcc ("fmovquge",        FM_QF, FCONDUGE, 0),
1563
/* v9 */ fmovfcc ("fmovsuge",        FM_SF, FCONDUGE, 0),
1564
/* v9 */ fmovfcc ("fmovdul",        FM_DF, FCONDUL, 0),
1565
/* v9 */ fmovfcc ("fmovqul",        FM_QF, FCONDUL, 0),
1566
/* v9 */ fmovfcc ("fmovsul",        FM_SF, FCONDUL, 0),
1567
/* v9 */ fmovfcc ("fmovdule",        FM_DF, FCONDULE, 0),
1568
/* v9 */ fmovfcc ("fmovqule",        FM_QF, FCONDULE, 0),
1569
/* v9 */ fmovfcc ("fmovsule",        FM_SF, FCONDULE, 0),
1570
/* v9 */ fmovicc ("fmovdvc",        FM_DF, CONDVC, 0),
1571
/* v9 */ fmovicc ("fmovqvc",        FM_QF, CONDVC, 0),
1572
/* v9 */ fmovicc ("fmovsvc",        FM_SF, CONDVC, 0),
1573
/* v9 */ fmovicc ("fmovdvs",        FM_DF, CONDVS, 0),
1574
/* v9 */ fmovicc ("fmovqvs",        FM_QF, CONDVS, 0),
1575
/* v9 */ fmovicc ("fmovsvs",        FM_SF, CONDVS, 0),
1576
/* v9 */ fmovcc  ("fmovdz",        FM_DF, CONDZ, FCONDZ, F_ALIAS),
1577
/* v9 */ fmovcc  ("fmovqz",        FM_QF, CONDZ, FCONDZ, F_ALIAS),
1578
/* v9 */ fmovcc  ("fmovsz",        FM_SF, CONDZ, FCONDZ, F_ALIAS),
1579

    
1580
#undef fmovicc /* v9 */
1581
#undef fmovfcc /* v9 */
1582
#undef fmovcc /* v9 */
1583
#undef FM_DF /* v9 */
1584
#undef FM_QF /* v9 */
1585
#undef FM_SF /* v9 */
1586

    
1587
/* Coprocessor branches.  */
1588
#define CBR(opcode, mask, lose, flags, arch) \
1589
 { opcode, (mask), ANNUL|(lose), "l",    flags|F_DELAYED, arch }, \
1590
 { opcode, (mask)|ANNUL, (lose), ",a l", flags|F_DELAYED, arch }
1591

    
1592
/* Floating point branches.  */
1593
#define FBR(opcode, mask, lose, flags) \
1594
 { opcode, (mask), ANNUL|(lose), "l",    flags|F_DELAYED|F_FBR, v6 }, \
1595
 { opcode, (mask)|ANNUL, (lose), ",a l", flags|F_DELAYED|F_FBR, v6 }
1596

    
1597
/* V9 extended floating point branches.  */
1598
#define FBRX(opcode, mask, lose, flags) /* v9 */ \
1599
 { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), "6,G",      flags|F_DELAYED|F_FBR, v9 }, \
1600
 { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), ",T 6,G",   flags|F_DELAYED|F_FBR, v9 }, \
1601
 { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a 6,G",   flags|F_DELAYED|F_FBR, v9 }, \
1602
 { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a,T 6,G", flags|F_DELAYED|F_FBR, v9 }, \
1603
 { opcode, FBFCC(0)|(mask), ANNUL|BPRED|FBFCC(~0)|(lose), ",N 6,G",   flags|F_DELAYED|F_FBR, v9 }, \
1604
 { opcode, FBFCC(0)|(mask)|ANNUL, BPRED|FBFCC(~0)|(lose), ",a,N 6,G", flags|F_DELAYED|F_FBR, v9 }, \
1605
 { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), "7,G",      flags|F_DELAYED|F_FBR, v9 }, \
1606
 { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), ",T 7,G",   flags|F_DELAYED|F_FBR, v9 }, \
1607
 { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a 7,G",   flags|F_DELAYED|F_FBR, v9 }, \
1608
 { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a,T 7,G", flags|F_DELAYED|F_FBR, v9 }, \
1609
 { opcode, FBFCC(1)|(mask), ANNUL|BPRED|FBFCC(~1)|(lose), ",N 7,G",   flags|F_DELAYED|F_FBR, v9 }, \
1610
 { opcode, FBFCC(1)|(mask)|ANNUL, BPRED|FBFCC(~1)|(lose), ",a,N 7,G", flags|F_DELAYED|F_FBR, v9 }, \
1611
 { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), "8,G",      flags|F_DELAYED|F_FBR, v9 }, \
1612
 { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), ",T 8,G",   flags|F_DELAYED|F_FBR, v9 }, \
1613
 { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a 8,G",   flags|F_DELAYED|F_FBR, v9 }, \
1614
 { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a,T 8,G", flags|F_DELAYED|F_FBR, v9 }, \
1615
 { opcode, FBFCC(2)|(mask), ANNUL|BPRED|FBFCC(~2)|(lose), ",N 8,G",   flags|F_DELAYED|F_FBR, v9 }, \
1616
 { opcode, FBFCC(2)|(mask)|ANNUL, BPRED|FBFCC(~2)|(lose), ",a,N 8,G", flags|F_DELAYED|F_FBR, v9 }, \
1617
 { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), "9,G",      flags|F_DELAYED|F_FBR, v9 }, \
1618
 { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), ",T 9,G",   flags|F_DELAYED|F_FBR, v9 }, \
1619
 { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a 9,G",   flags|F_DELAYED|F_FBR, v9 }, \
1620
 { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a,T 9,G", flags|F_DELAYED|F_FBR, v9 }, \
1621
 { opcode, FBFCC(3)|(mask), ANNUL|BPRED|FBFCC(~3)|(lose), ",N 9,G",   flags|F_DELAYED|F_FBR, v9 }, \
1622
 { opcode, FBFCC(3)|(mask)|ANNUL, BPRED|FBFCC(~3)|(lose), ",a,N 9,G", flags|F_DELAYED|F_FBR, v9 }
1623

    
1624
/* v9: We must put `FBRX' before `FBR', to ensure that we never match
1625
   v9: something against an expression unless it is an expression.  Otherwise,
1626
   v9: we end up with undefined symbol tables entries, because they get added,
1627
   v9: but are not deleted if the pattern fails to match.  */
1628

    
1629
#define CONDFC(fop, cop, mask, flags) \
1630
  FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
1631
  FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
1632
  CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6notlet)
1633

    
1634
#define CONDFCL(fop, cop, mask, flags) \
1635
  FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
1636
  FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
1637
  CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6)
1638

    
1639
#define CONDF(fop, mask, flags) \
1640
  FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
1641
  FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags)
1642

    
1643
CONDFC  ("fb",    "cb",    0x8, F_UNBR),
1644
CONDFCL ("fba",          "cba",   0x8, F_UNBR|F_ALIAS),
1645
CONDFC  ("fbe",          "cb0",   0x9, F_CONDBR),
1646
CONDF   ("fbz",            0x9, F_CONDBR|F_ALIAS),
1647
CONDFC  ("fbg",          "cb2",   0x6, F_CONDBR),
1648
CONDFC  ("fbge",  "cb02",  0xb, F_CONDBR),
1649
CONDFC  ("fbl",          "cb1",   0x4, F_CONDBR),
1650
CONDFC  ("fble",  "cb01",  0xd, F_CONDBR),
1651
CONDFC  ("fblg",  "cb12",  0x2, F_CONDBR),
1652
CONDFCL ("fbn",          "cbn",   0x0, F_UNBR),
1653
CONDFC  ("fbne",  "cb123", 0x1, F_CONDBR),
1654
CONDF   ("fbnz",           0x1, F_CONDBR|F_ALIAS),
1655
CONDFC  ("fbo",          "cb012", 0xf, F_CONDBR),
1656
CONDFC  ("fbu",          "cb3",   0x7, F_CONDBR),
1657
CONDFC  ("fbue",  "cb03",  0xa, F_CONDBR),
1658
CONDFC  ("fbug",  "cb23",  0x5, F_CONDBR),
1659
CONDFC  ("fbuge", "cb023", 0xc, F_CONDBR),
1660
CONDFC  ("fbul",  "cb13",  0x3, F_CONDBR),
1661
CONDFC  ("fbule", "cb013", 0xe, F_CONDBR),
1662

    
1663
#undef CONDFC
1664
#undef CONDFCL
1665
#undef CONDF
1666
#undef CBR
1667
#undef FBR
1668
#undef FBRX        /* v9 */
1669

    
1670
{ "jmp",        F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0),        "1+2", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%g0 */
1671
{ "jmp",        F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI_RS2(~0),        "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%g0 */
1672
{ "jmp",        F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0,                "1+i", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+i,%g0 */
1673
{ "jmp",        F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0,                "i+1", F_UNBR|F_DELAYED, v6 }, /* jmpl i+rs1,%g0 */
1674
{ "jmp",        F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|RS1_G0,                "i", F_UNBR|F_DELAYED, v6 }, /* jmpl %g0+i,%g0 */
1675
{ "jmp",        F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|SIMM13(~0),        "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+0,%g0 */
1676

    
1677
{ "nop",        F2(0, 4), 0xfeffffff, "", 0, v6 }, /* sethi 0, %g0 */
1678

    
1679
{ "set",        F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v6 },
1680
{ "setuw",        F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 },
1681
{ "setsw",        F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 },
1682
{ "setx",        F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,1,d", F_ALIAS, v9 },
1683

    
1684
{ "sethi",        F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, v6 },
1685

    
1686
{ "taddcc",        F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0),        "1,2,d", 0, v6 },
1687
{ "taddcc",        F3(2, 0x20, 1), F3(~2, ~0x20, ~1),                "1,i,d", 0, v6 },
1688
{ "taddcc",        F3(2, 0x20, 1), F3(~2, ~0x20, ~1),                "i,1,d", 0, v6 },
1689
{ "taddcctv",        F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0),        "1,2,d", 0, v6 },
1690
{ "taddcctv",        F3(2, 0x22, 1), F3(~2, ~0x22, ~1),                "1,i,d", 0, v6 },
1691
{ "taddcctv",        F3(2, 0x22, 1), F3(~2, ~0x22, ~1),                "i,1,d", 0, v6 },
1692

    
1693
{ "tsubcc",        F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0),        "1,2,d", 0, v6 },
1694
{ "tsubcc",        F3(2, 0x21, 1), F3(~2, ~0x21, ~1),                "1,i,d", 0, v6 },
1695
{ "tsubcctv",        F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0),        "1,2,d", 0, v6 },
1696
{ "tsubcctv",        F3(2, 0x23, 1), F3(~2, ~0x23, ~1),                "1,i,d", 0, v6 },
1697

    
1698
{ "unimp",        F2(0x0, 0x0), 0xffc00000, "n", 0, v6notv9 },
1699
{ "illtrap",        F2(0, 0), F2(~0, ~0)|RD_G0, "n", 0, v9 },
1700

    
1701
/* This *is* a commutative instruction.  */
1702
{ "xnor",        F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0),        "1,2,d", 0, v6 },
1703
{ "xnor",        F3(2, 0x07, 1), F3(~2, ~0x07, ~1),                "1,i,d", 0, v6 },
1704
{ "xnor",        F3(2, 0x07, 1), F3(~2, ~0x07, ~1),                "i,1,d", 0, v6 },
1705
/* This *is* a commutative instruction.  */
1706
{ "xnorcc",        F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0),        "1,2,d", 0, v6 },
1707
{ "xnorcc",        F3(2, 0x17, 1), F3(~2, ~0x17, ~1),                "1,i,d", 0, v6 },
1708
{ "xnorcc",        F3(2, 0x17, 1), F3(~2, ~0x17, ~1),                "i,1,d", 0, v6 },
1709
{ "xor",        F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0),        "1,2,d", 0, v6 },
1710
{ "xor",        F3(2, 0x03, 1), F3(~2, ~0x03, ~1),                "1,i,d", 0, v6 },
1711
{ "xor",        F3(2, 0x03, 1), F3(~2, ~0x03, ~1),                "i,1,d", 0, v6 },
1712
{ "xorcc",        F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0),        "1,2,d", 0, v6 },
1713
{ "xorcc",        F3(2, 0x13, 1), F3(~2, ~0x13, ~1),                "1,i,d", 0, v6 },
1714
{ "xorcc",        F3(2, 0x13, 1), F3(~2, ~0x13, ~1),                "i,1,d", 0, v6 },
1715

    
1716
{ "not",        F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS, v6 }, /* xnor rs1,%0,rd */
1717
{ "not",        F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS, v6 }, /* xnor rd,%0,rd */
1718

    
1719
{ "btog",        F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0),        "2,r", F_ALIAS, v6 }, /* xor rd,rs2,rd */
1720
{ "btog",        F3(2, 0x03, 1), F3(~2, ~0x03, ~1),                "i,r", F_ALIAS, v6 }, /* xor rd,i,rd */
1721

    
1722
/* FPop1 and FPop2 are not instructions.  Don't accept them.  */
1723

    
1724
{ "fdtoi",        F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0, "B,g", F_FLOAT, v6 },
1725
{ "fstoi",        F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", F_FLOAT, v6 },
1726
{ "fqtoi",        F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", F_FLOAT, v8 },
1727

    
1728
{ "fdtox",        F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,g", F_FLOAT, v9 },
1729
{ "fstox",        F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,g", F_FLOAT, v9 },
1730
{ "fqtox",        F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,g", F_FLOAT, v9 },
1731

    
1732
{ "fitod",        F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", F_FLOAT, v6 },
1733
{ "fitos",        F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", F_FLOAT, v6 },
1734
{ "fitoq",        F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", F_FLOAT, v8 },
1735

    
1736
{ "fxtod",        F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "f,H", F_FLOAT, v9 },
1737
{ "fxtos",        F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "f,g", F_FLOAT, v9 },
1738
{ "fxtoq",        F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "f,J", F_FLOAT, v9 },
1739

    
1740
{ "fdtoq",        F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", F_FLOAT, v8 },
1741
{ "fdtos",        F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", F_FLOAT, v6 },
1742
{ "fqtod",        F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0, "R,H", F_FLOAT, v8 },
1743
{ "fqtos",        F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "R,g", F_FLOAT, v8 },
1744
{ "fstod",        F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0, "f,H", F_FLOAT, v6 },
1745
{ "fstoq",        F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0, "f,J", F_FLOAT, v8 },
1746

    
1747
{ "fdivd",        F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", F_FLOAT, v6 },
1748
{ "fdivq",        F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT, v8 },
1749
{ "fdivx",        F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT|F_ALIAS, v8 },
1750
{ "fdivs",        F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", F_FLOAT, v6 },
1751
{ "fmuld",        F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", F_FLOAT, v6 },
1752
{ "fmulq",        F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT, v8 },
1753
{ "fmulx",        F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT|F_ALIAS, v8 },
1754
{ "fmuls",        F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", F_FLOAT, v6 },
1755

    
1756
{ "fdmulq",        F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT, v8 },
1757
{ "fdmulx",        F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT|F_ALIAS, v8 },
1758
{ "fsmuld",        F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", F_FLOAT, v8 },
1759

    
1760
{ "fsqrtd",        F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0, "B,H", F_FLOAT, v7 },
1761
{ "fsqrtq",        F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT, v8 },
1762
{ "fsqrtx",        F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v8 },
1763
{ "fsqrts",        F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0, "f,g", F_FLOAT, v7 },
1764

    
1765
{ "fabsd",        F3F(2, 0x34, 0x00a), F3F(~2, ~0x34, ~0x00a)|RS1_G0, "B,H", F_FLOAT, v9 },
1766
{ "fabsq",        F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT, v9 },
1767
{ "fabsx",        F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 },
1768
{ "fabss",        F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0, "f,g", F_FLOAT, v6 },
1769
{ "fmovd",        F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0, "B,H", F_FLOAT, v9 },
1770
{ "fmovq",        F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT, v9 },
1771
{ "fmovx",        F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 },
1772
{ "fmovs",        F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0, "f,g", F_FLOAT, v6 },
1773
{ "fnegd",        F3F(2, 0x34, 0x006), F3F(~2, ~0x34, ~0x006)|RS1_G0, "B,H", F_FLOAT, v9 },
1774
{ "fnegq",        F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT, v9 },
1775
{ "fnegx",        F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 },
1776
{ "fnegs",        F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0, "f,g", F_FLOAT, v6 },
1777

    
1778
{ "faddd",        F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", F_FLOAT, v6 },
1779
{ "faddq",        F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT, v8 },
1780
{ "faddx",        F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT|F_ALIAS, v8 },
1781
{ "fadds",        F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", F_FLOAT, v6 },
1782
{ "fsubd",        F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", F_FLOAT, v6 },
1783
{ "fsubq",        F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT, v8 },
1784
{ "fsubx",        F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT|F_ALIAS, v8 },
1785
{ "fsubs",        F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", F_FLOAT, v6 },
1786

    
1787
#define CMPFCC(x)        (((x)&0x3)<<25)
1788

    
1789
{ "fcmpd",                  F3F(2, 0x35, 0x052),            F3F(~2, ~0x35, ~0x052)|RD_G0,  "v,B",   F_FLOAT, v6 },
1790
{ "fcmpd",        CMPFCC(0)|F3F(2, 0x35, 0x052), CMPFCC(~0)|F3F(~2, ~0x35, ~0x052),         "6,v,B", F_FLOAT, v9 },
1791
{ "fcmpd",        CMPFCC(1)|F3F(2, 0x35, 0x052), CMPFCC(~1)|F3F(~2, ~0x35, ~0x052),         "7,v,B", F_FLOAT, v9 },
1792
{ "fcmpd",        CMPFCC(2)|F3F(2, 0x35, 0x052), CMPFCC(~2)|F3F(~2, ~0x35, ~0x052),         "8,v,B", F_FLOAT, v9 },
1793
{ "fcmpd",        CMPFCC(3)|F3F(2, 0x35, 0x052), CMPFCC(~3)|F3F(~2, ~0x35, ~0x052),         "9,v,B", F_FLOAT, v9 },
1794
{ "fcmped",                  F3F(2, 0x35, 0x056),            F3F(~2, ~0x35, ~0x056)|RD_G0,  "v,B",   F_FLOAT, v6 },
1795
{ "fcmped",        CMPFCC(0)|F3F(2, 0x35, 0x056), CMPFCC(~0)|F3F(~2, ~0x35, ~0x056),         "6,v,B", F_FLOAT, v9 },
1796
{ "fcmped",        CMPFCC(1)|F3F(2, 0x35, 0x056), CMPFCC(~1)|F3F(~2, ~0x35, ~0x056),         "7,v,B", F_FLOAT, v9 },
1797
{ "fcmped",        CMPFCC(2)|F3F(2, 0x35, 0x056), CMPFCC(~2)|F3F(~2, ~0x35, ~0x056),         "8,v,B", F_FLOAT, v9 },
1798
{ "fcmped",        CMPFCC(3)|F3F(2, 0x35, 0x056), CMPFCC(~3)|F3F(~2, ~0x35, ~0x056),         "9,v,B", F_FLOAT, v9 },
1799
{ "fcmpq",                  F3F(2, 0x35, 0x053),            F3F(~2, ~0x35, ~0x053)|RD_G0,         "V,R", F_FLOAT, v8 },
1800
{ "fcmpq",        CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053),         "6,V,R", F_FLOAT, v9 },
1801
{ "fcmpq",        CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053),         "7,V,R", F_FLOAT, v9 },
1802
{ "fcmpq",        CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053),         "8,V,R", F_FLOAT, v9 },
1803
{ "fcmpq",        CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053),         "9,V,R", F_FLOAT, v9 },
1804
{ "fcmpeq",                  F3F(2, 0x35, 0x057),            F3F(~2, ~0x35, ~0x057)|RD_G0,         "V,R", F_FLOAT, v8 },
1805
{ "fcmpeq",        CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057),         "6,V,R", F_FLOAT, v9 },
1806
{ "fcmpeq",        CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057),         "7,V,R", F_FLOAT, v9 },
1807
{ "fcmpeq",        CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057),         "8,V,R", F_FLOAT, v9 },
1808
{ "fcmpeq",        CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057),         "9,V,R", F_FLOAT, v9 },
1809
{ "fcmpx",                  F3F(2, 0x35, 0x053),            F3F(~2, ~0x35, ~0x053)|RD_G0,         "V,R", F_FLOAT|F_ALIAS, v8 },
1810
{ "fcmpx",        CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053),         "6,V,R", F_FLOAT|F_ALIAS, v9 },
1811
{ "fcmpx",        CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053),         "7,V,R", F_FLOAT|F_ALIAS, v9 },
1812
{ "fcmpx",        CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053),         "8,V,R", F_FLOAT|F_ALIAS, v9 },
1813
{ "fcmpx",        CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053),         "9,V,R", F_FLOAT|F_ALIAS, v9 },
1814
{ "fcmpex",                  F3F(2, 0x35, 0x057),            F3F(~2, ~0x35, ~0x057)|RD_G0,         "V,R", F_FLOAT|F_ALIAS, v8 },
1815
{ "fcmpex",        CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057),         "6,V,R", F_FLOAT|F_ALIAS, v9 },
1816
{ "fcmpex",        CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057),         "7,V,R", F_FLOAT|F_ALIAS, v9 },
1817
{ "fcmpex",        CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057),         "8,V,R", F_FLOAT|F_ALIAS, v9 },
1818
{ "fcmpex",        CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057),         "9,V,R", F_FLOAT|F_ALIAS, v9 },
1819
{ "fcmps",                  F3F(2, 0x35, 0x051),            F3F(~2, ~0x35, ~0x051)|RD_G0, "e,f",   F_FLOAT, v6 },
1820
{ "fcmps",        CMPFCC(0)|F3F(2, 0x35, 0x051), CMPFCC(~0)|F3F(~2, ~0x35, ~0x051),         "6,e,f", F_FLOAT, v9 },
1821
{ "fcmps",        CMPFCC(1)|F3F(2, 0x35, 0x051), CMPFCC(~1)|F3F(~2, ~0x35, ~0x051),         "7,e,f", F_FLOAT, v9 },
1822
{ "fcmps",        CMPFCC(2)|F3F(2, 0x35, 0x051), CMPFCC(~2)|F3F(~2, ~0x35, ~0x051),         "8,e,f", F_FLOAT, v9 },
1823
{ "fcmps",        CMPFCC(3)|F3F(2, 0x35, 0x051), CMPFCC(~3)|F3F(~2, ~0x35, ~0x051),         "9,e,f", F_FLOAT, v9 },
1824
{ "fcmpes",                  F3F(2, 0x35, 0x055),            F3F(~2, ~0x35, ~0x055)|RD_G0, "e,f",   F_FLOAT, v6 },
1825
{ "fcmpes",        CMPFCC(0)|F3F(2, 0x35, 0x055), CMPFCC(~0)|F3F(~2, ~0x35, ~0x055),         "6,e,f", F_FLOAT, v9 },
1826
{ "fcmpes",        CMPFCC(1)|F3F(2, 0x35, 0x055), CMPFCC(~1)|F3F(~2, ~0x35, ~0x055),         "7,e,f", F_FLOAT, v9 },
1827
{ "fcmpes",        CMPFCC(2)|F3F(2, 0x35, 0x055), CMPFCC(~2)|F3F(~2, ~0x35, ~0x055),         "8,e,f", F_FLOAT, v9 },
1828
{ "fcmpes",        CMPFCC(3)|F3F(2, 0x35, 0x055), CMPFCC(~3)|F3F(~2, ~0x35, ~0x055),         "9,e,f", F_FLOAT, v9 },
1829

    
1830
/* These Extended FPop (FIFO) instructions are new in the Fujitsu
1831
   MB86934, replacing the CPop instructions from v6 and later
1832
   processors.  */
1833

    
1834
#define EFPOP1_2(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op)|RS1_G0, args, 0, sparclite }
1835
#define EFPOP1_3(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op),        args, 0, sparclite }
1836
#define EFPOP2_2(name, op, args) { name, F3F(2, 0x37, op), F3F(~2, ~0x37, ~op)|RD_G0,  args, 0, sparclite }
1837

    
1838
EFPOP1_2 ("efitod",        0x0c8, "f,H"),
1839
EFPOP1_2 ("efitos",        0x0c4, "f,g"),
1840
EFPOP1_2 ("efdtoi",        0x0d2, "B,g"),
1841
EFPOP1_2 ("efstoi",        0x0d1, "f,g"),
1842
EFPOP1_2 ("efstod",        0x0c9, "f,H"),
1843
EFPOP1_2 ("efdtos",        0x0c6, "B,g"),
1844
EFPOP1_2 ("efmovs",        0x001, "f,g"),
1845
EFPOP1_2 ("efnegs",        0x005, "f,g"),
1846
EFPOP1_2 ("efabss",        0x009, "f,g"),
1847
EFPOP1_2 ("efsqrtd",        0x02a, "B,H"),
1848
EFPOP1_2 ("efsqrts",        0x029, "f,g"),
1849
EFPOP1_3 ("efaddd",        0x042, "v,B,H"),
1850
EFPOP1_3 ("efadds",        0x041, "e,f,g"),
1851
EFPOP1_3 ("efsubd",        0x046, "v,B,H"),
1852
EFPOP1_3 ("efsubs",        0x045, "e,f,g"),
1853
EFPOP1_3 ("efdivd",        0x04e, "v,B,H"),
1854
EFPOP1_3 ("efdivs",        0x04d, "e,f,g"),
1855
EFPOP1_3 ("efmuld",        0x04a, "v,B,H"),
1856
EFPOP1_3 ("efmuls",        0x049, "e,f,g"),
1857
EFPOP1_3 ("efsmuld",        0x069, "e,f,H"),
1858
EFPOP2_2 ("efcmpd",        0x052, "v,B"),
1859
EFPOP2_2 ("efcmped",        0x056, "v,B"),
1860
EFPOP2_2 ("efcmps",        0x051, "e,f"),
1861
EFPOP2_2 ("efcmpes",        0x055, "e,f"),
1862

    
1863
#undef EFPOP1_2
1864
#undef EFPOP1_3
1865
#undef EFPOP2_2
1866

    
1867
/* These are marked F_ALIAS, so that they won't conflict with sparclite insns
1868
   present.  Otherwise, the F_ALIAS flag is ignored.  */
1869
{ "cpop1",        F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d", F_ALIAS, v6notv9 },
1870
{ "cpop2",        F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", F_ALIAS, v6notv9 },
1871

    
1872
/* sparclet specific insns */
1873

    
1874
COMMUTEOP ("umac", 0x3e, sparclet),
1875
COMMUTEOP ("smac", 0x3f, sparclet),
1876
COMMUTEOP ("umacd", 0x2e, sparclet),
1877
COMMUTEOP ("smacd", 0x2f, sparclet),
1878
COMMUTEOP ("umuld", 0x09, sparclet),
1879
COMMUTEOP ("smuld", 0x0d, sparclet),
1880

    
1881
{ "shuffle",        F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0),        "1,2,d", 0, sparclet },
1882
{ "shuffle",        F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1),                "1,i,d", 0, sparclet },
1883

    
1884
/* The manual isn't completely accurate on these insns.  The `rs2' field is
1885
   treated as being 6 bits to account for 6 bit immediates to cpush.  It is
1886
   assumed that it is intended that bit 5 is 0 when rs2 contains a reg.  */
1887
#define BIT5 (1<<5)
1888
{ "crdcxt",        F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5|RS2(~0),        "U,d", 0, sparclet },
1889
{ "cwrcxt",        F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5|RS2(~0),        "1,u", 0, sparclet },
1890
{ "cpush",        F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5|RD(~0),        "1,2", 0, sparclet },
1891
{ "cpush",        F3(2, 0x36, 1)|SLCPOP(0), F3(~2, ~0x36, ~1)|SLCPOP(~0)|RD(~0),                "1,Y", 0, sparclet },
1892
{ "cpusha",        F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5|RD(~0),        "1,2", 0, sparclet },
1893
{ "cpusha",        F3(2, 0x36, 1)|SLCPOP(1), F3(~2, ~0x36, ~1)|SLCPOP(~1)|RD(~0),                "1,Y", 0, sparclet },
1894
{ "cpull",        F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5|RS1(~0)|RS2(~0), "d", 0, sparclet },
1895
#undef BIT5
1896

    
1897
/* sparclet coprocessor branch insns */
1898
#define SLCBCC2(opcode, mask, lose) \
1899
 { opcode, (mask), ANNUL|(lose), "l",    F_DELAYED|F_CONDBR, sparclet }, \
1900
 { opcode, (mask)|ANNUL, (lose), ",a l", F_DELAYED|F_CONDBR, sparclet }
1901
#define SLCBCC(opcode, mask) \
1902
  SLCBCC2(opcode, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)))
1903

    
1904
/* cbn,cba can't be defined here because they're defined elsewhere and GAS
1905
   requires all mnemonics of the same name to be consecutive.  */
1906
/*SLCBCC("cbn", 0), - already defined */
1907
SLCBCC("cbe", 1),
1908
SLCBCC("cbf", 2),
1909
SLCBCC("cbef", 3),
1910
SLCBCC("cbr", 4),
1911
SLCBCC("cber", 5),
1912
SLCBCC("cbfr", 6),
1913
SLCBCC("cbefr", 7),
1914
/*SLCBCC("cba", 8), - already defined */
1915
SLCBCC("cbne", 9),
1916
SLCBCC("cbnf", 10),
1917
SLCBCC("cbnef", 11),
1918
SLCBCC("cbnr", 12),
1919
SLCBCC("cbner", 13),
1920
SLCBCC("cbnfr", 14),
1921
SLCBCC("cbnefr", 15),
1922

    
1923
#undef SLCBCC2
1924
#undef SLCBCC
1925

    
1926
{ "casa",        F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, v9 },
1927
{ "casa",        F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, v9 },
1928
{ "casxa",        F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, v9 },
1929
{ "casxa",        F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, v9 },
1930

    
1931
/* v9 synthetic insns */
1932
{ "iprefetch",        F2(0, 1)|(2<<20)|BPRED, F2(~0, ~1)|(1<<20)|ANNUL|COND(~0), "G", 0, v9 }, /* bn,a,pt %xcc,label */
1933
{ "signx",        F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* sra rs1,%g0,rd */
1934
{ "signx",        F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* sra rd,%g0,rd */
1935
{ "clruw",        F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* srl rs1,%g0,rd */
1936
{ "clruw",        F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* srl rd,%g0,rd */
1937
{ "cas",        F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P,rs2,rd */
1938
{ "casl",        F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P_L,rs2,rd */
1939
{ "casx",        F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P,rs2,rd */
1940
{ "casxl",        F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */
1941

    
1942
/* Ultrasparc extensions */
1943
{ "shutdown",        F3F(2, 0x36, 0x080), F3F(~2, ~0x36, ~0x080)|RD_G0|RS1_G0|RS2_G0, "", 0, v9a },
1944

    
1945
/* FIXME: Do we want to mark these as F_FLOAT, or something similar?  */
1946
{ "fpadd16",        F3F(2, 0x36, 0x050), F3F(~2, ~0x36, ~0x050), "v,B,H", 0, v9a },
1947
{ "fpadd16s",        F3F(2, 0x36, 0x051), F3F(~2, ~0x36, ~0x051), "e,f,g", 0, v9a },
1948
{ "fpadd32",        F3F(2, 0x36, 0x052), F3F(~2, ~0x36, ~0x052), "v,B,H", 0, v9a },
1949
{ "fpadd32s",        F3F(2, 0x36, 0x053), F3F(~2, ~0x36, ~0x053), "e,f,g", 0, v9a },
1950
{ "fpsub16",        F3F(2, 0x36, 0x054), F3F(~2, ~0x36, ~0x054), "v,B,H", 0, v9a },
1951
{ "fpsub16s",        F3F(2, 0x36, 0x055), F3F(~2, ~0x36, ~0x055), "e,f,g", 0, v9a },
1952
{ "fpsub32",        F3F(2, 0x36, 0x056), F3F(~2, ~0x36, ~0x056), "v,B,H", 0, v9a },
1953
{ "fpsub32s",        F3F(2, 0x36, 0x057), F3F(~2, ~0x36, ~0x057), "e,f,g", 0, v9a },
1954

    
1955
{ "fpack32",        F3F(2, 0x36, 0x03a), F3F(~2, ~0x36, ~0x03a), "v,B,H", 0, v9a },
1956
{ "fpack16",        F3F(2, 0x36, 0x03b), F3F(~2, ~0x36, ~0x03b)|RS1_G0, "B,g", 0, v9a },
1957
{ "fpackfix",        F3F(2, 0x36, 0x03d), F3F(~2, ~0x36, ~0x03d)|RS1_G0, "B,g", 0, v9a },
1958
{ "fexpand",        F3F(2, 0x36, 0x04d), F3F(~2, ~0x36, ~0x04d)|RS1_G0, "f,H", 0, v9a },
1959
{ "fpmerge",        F3F(2, 0x36, 0x04b), F3F(~2, ~0x36, ~0x04b), "e,f,H", 0, v9a },
1960

    
1961
/* Note that the mixing of 32/64 bit regs is intentional.  */
1962
{ "fmul8x16",                F3F(2, 0x36, 0x031), F3F(~2, ~0x36, ~0x031), "e,B,H", 0, v9a },
1963
{ "fmul8x16au",                F3F(2, 0x36, 0x033), F3F(~2, ~0x36, ~0x033), "e,f,H", 0, v9a },
1964
{ "fmul8x16al",                F3F(2, 0x36, 0x035), F3F(~2, ~0x36, ~0x035), "e,f,H", 0, v9a },
1965
{ "fmul8sux16",                F3F(2, 0x36, 0x036), F3F(~2, ~0x36, ~0x036), "v,B,H", 0, v9a },
1966
{ "fmul8ulx16",                F3F(2, 0x36, 0x037), F3F(~2, ~0x36, ~0x037), "v,B,H", 0, v9a },
1967
{ "fmuld8sux16",        F3F(2, 0x36, 0x038), F3F(~2, ~0x36, ~0x038), "e,f,H", 0, v9a },
1968
{ "fmuld8ulx16",        F3F(2, 0x36, 0x039), F3F(~2, ~0x36, ~0x039), "e,f,H", 0, v9a },
1969

    
1970
{ "alignaddr",        F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d", 0, v9a },
1971
{ "alignaddrl",        F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, v9a },
1972
{ "faligndata",        F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, v9a },
1973

    
1974
{ "fzero",        F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, v9a },
1975
{ "fzeros",        F3F(2, 0x36, 0x061), F3F(~2, ~0x36, ~0x061), "g", 0, v9a },
1976
{ "fone",        F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", 0, v9a },
1977
{ "fones",        F3F(2, 0x36, 0x07f), F3F(~2, ~0x36, ~0x07f), "g", 0, v9a },
1978
{ "fsrc1",        F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", 0, v9a },
1979
{ "fsrc1s",        F3F(2, 0x36, 0x075), F3F(~2, ~0x36, ~0x075), "e,g", 0, v9a },
1980
{ "fsrc2",        F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", 0, v9a },
1981
{ "fsrc2s",        F3F(2, 0x36, 0x079), F3F(~2, ~0x36, ~0x079), "f,g", 0, v9a },
1982
{ "fnot1",        F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", 0, v9a },
1983
{ "fnot1s",        F3F(2, 0x36, 0x06b), F3F(~2, ~0x36, ~0x06b), "e,g", 0, v9a },
1984
{ "fnot2",        F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", 0, v9a },
1985
{ "fnot2s",        F3F(2, 0x36, 0x067), F3F(~2, ~0x36, ~0x067), "f,g", 0, v9a },
1986
{ "for",        F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", 0, v9a },
1987
{ "fors",        F3F(2, 0x36, 0x07d), F3F(~2, ~0x36, ~0x07d), "e,f,g", 0, v9a },
1988
{ "fnor",        F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", 0, v9a },
1989
{ "fnors",        F3F(2, 0x36, 0x063), F3F(~2, ~0x36, ~0x063), "e,f,g", 0, v9a },
1990
{ "fand",        F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", 0, v9a },
1991
{ "fands",        F3F(2, 0x36, 0x071), F3F(~2, ~0x36, ~0x071), "e,f,g", 0, v9a },
1992
{ "fnand",        F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", 0, v9a },
1993
{ "fnands",        F3F(2, 0x36, 0x06f), F3F(~2, ~0x36, ~0x06f), "e,f,g", 0, v9a },
1994
{ "fxor",        F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", 0, v9a },
1995
{ "fxors",        F3F(2, 0x36, 0x06d), F3F(~2, ~0x36, ~0x06d), "e,f,g", 0, v9a },
1996
{ "fxnor",        F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", 0, v9a },
1997
{ "fxnors",        F3F(2, 0x36, 0x073), F3F(~2, ~0x36, ~0x073), "e,f,g", 0, v9a },
1998
{ "fornot1",        F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", 0, v9a },
1999
{ "fornot1s",        F3F(2, 0x36, 0x07b), F3F(~2, ~0x36, ~0x07b), "e,f,g", 0, v9a },
2000
{ "fornot2",        F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", 0, v9a },
2001
{ "fornot2s",        F3F(2, 0x36, 0x077), F3F(~2, ~0x36, ~0x077), "e,f,g", 0, v9a },
2002
{ "fandnot1",        F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", 0, v9a },
2003
{ "fandnot1s",        F3F(2, 0x36, 0x069), F3F(~2, ~0x36, ~0x069), "e,f,g", 0, v9a },
2004
{ "fandnot2",        F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", 0, v9a },
2005
{ "fandnot2s",        F3F(2, 0x36, 0x065), F3F(~2, ~0x36, ~0x065), "e,f,g", 0, v9a },
2006

    
2007
{ "fcmpgt16",        F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", 0, v9a },
2008
{ "fcmpgt32",        F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", 0, v9a },
2009
{ "fcmple16",        F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", 0, v9a },
2010
{ "fcmple32",        F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", 0, v9a },
2011
{ "fcmpne16",        F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", 0, v9a },
2012
{ "fcmpne32",        F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", 0, v9a },
2013
{ "fcmpeq16",        F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", 0, v9a },
2014
{ "fcmpeq32",        F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", 0, v9a },
2015

    
2016
{ "edge8",        F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", 0, v9a },
2017
{ "edge8l",        F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", 0, v9a },
2018
{ "edge16",        F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", 0, v9a },
2019
{ "edge16l",        F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", 0, v9a },
2020
{ "edge32",        F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", 0, v9a },
2021
{ "edge32l",        F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", 0, v9a },
2022

    
2023
{ "pdist",        F3F(2, 0x36, 0x03e), F3F(~2, ~0x36, ~0x03e), "v,B,H", 0, v9a },
2024

    
2025
{ "array8",        F3F(2, 0x36, 0x010), F3F(~2, ~0x36, ~0x010), "1,2,d", 0, v9a },
2026
{ "array16",        F3F(2, 0x36, 0x012), F3F(~2, ~0x36, ~0x012), "1,2,d", 0, v9a },
2027
{ "array32",        F3F(2, 0x36, 0x014), F3F(~2, ~0x36, ~0x014), "1,2,d", 0, v9a },
2028

    
2029
/* Cheetah instructions */
2030
{ "edge8n",    F3F(2, 0x36, 0x001), F3F(~2, ~0x36, ~0x001), "1,2,d", 0, v9b },
2031
{ "edge8ln",   F3F(2, 0x36, 0x003), F3F(~2, ~0x36, ~0x003), "1,2,d", 0, v9b },
2032
{ "edge16n",   F3F(2, 0x36, 0x005), F3F(~2, ~0x36, ~0x005), "1,2,d", 0, v9b },
2033
{ "edge16ln",  F3F(2, 0x36, 0x007), F3F(~2, ~0x36, ~0x007), "1,2,d", 0, v9b },
2034
{ "edge32n",   F3F(2, 0x36, 0x009), F3F(~2, ~0x36, ~0x009), "1,2,d", 0, v9b },
2035
{ "edge32ln",  F3F(2, 0x36, 0x00b), F3F(~2, ~0x36, ~0x00b), "1,2,d", 0, v9b },
2036

    
2037
{ "bmask",     F3F(2, 0x36, 0x019), F3F(~2, ~0x36, ~0x019), "1,2,d", 0, v9b },
2038
{ "bshuffle",  F3F(2, 0x36, 0x04c), F3F(~2, ~0x36, ~0x04c), "v,B,H", 0, v9b },
2039

    
2040
{ "siam",      F3F(2, 0x36, 0x081), F3F(~2, ~0x36, ~0x081)|RD_G0|RS1_G0|RS2(~7), "3", 0, v9b },
2041

    
2042
/* More v9 specific insns, these need to come last so they do not clash
2043
   with v9a instructions such as "edge8" which looks like impdep1. */
2044

    
2045
#define IMPDEP(name, code) \
2046
{ name,        F3(2, code, 0), F3(~2, ~code, ~0)|ASI(~0), "1,2,d", 0, v9notv9a }, \
2047
{ name,        F3(2, code, 1), F3(~2, ~code, ~1),           "1,i,d", 0, v9notv9a }, \
2048
{ name, F3(2, code, 0), F3(~2, ~code, ~0),         "x,1,2,d", 0, v9notv9a }, \
2049
{ name, F3(2, code, 0), F3(~2, ~code, ~0),         "x,e,f,g", 0, v9notv9a }
2050

    
2051
IMPDEP ("impdep1", 0x36),
2052
IMPDEP ("impdep2", 0x37),
2053

    
2054
#undef IMPDEP
2055

    
2056
};
2057

    
2058
const int sparc_num_opcodes = ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0]));
2059
 
2060
/* Utilities for argument parsing.  */
2061

    
2062
typedef struct
2063
{
2064
  int value;
2065
  const char *name;
2066
} arg;
2067

    
2068
/* Look up NAME in TABLE.  */
2069

    
2070
static int lookup_name PARAMS ((const arg *, const char *));
2071
static const char *lookup_value PARAMS ((const arg *, int));
2072

    
2073
static int
2074
lookup_name (table, name)
2075
     const arg *table;
2076
     const char *name;
2077
{
2078
  const arg *p;
2079

    
2080
  for (p = table; p->name; ++p)
2081
    if (strcmp (name, p->name) == 0)
2082
      return p->value;
2083

    
2084
  return -1;
2085
}
2086

    
2087
/* Look up VALUE in TABLE.  */
2088

    
2089
static const char *
2090
lookup_value (table, value)
2091
     const arg *table;
2092
     int value;
2093
{
2094
  const arg *p;
2095

    
2096
  for (p = table; p->name; ++p)
2097
    if (value == p->value)
2098
      return p->name;
2099

    
2100
  return (char *) 0;
2101
}
2102
 
2103
/* Handle ASI's.  */
2104

    
2105
static const arg asi_table_v8[] =
2106
{
2107
  { 0x00, "#ASI_M_RES00" },
2108
  { 0x01, "#ASI_M_UNA01" },
2109
  { 0x02, "#ASI_M_MXCC" },
2110
  { 0x03, "#ASI_M_FLUSH_PROBE" },
2111
  { 0x04, "#ASI_M_MMUREGS" },
2112
  { 0x05, "#ASI_M_TLBDIAG" },
2113
  { 0x06, "#ASI_M_DIAGS" },
2114
  { 0x07, "#ASI_M_IODIAG" },
2115
  { 0x08, "#ASI_M_USERTXT" },
2116
  { 0x09, "#ASI_M_KERNELTXT" },
2117
  { 0x0A, "#ASI_M_USERDATA" },
2118
  { 0x0B, "#ASI_M_KERNELDATA" },
2119
  { 0x0C, "#ASI_M_TXTC_TAG" },
2120
  { 0x0D, "#ASI_M_TXTC_DATA" },
2121
  { 0x0E, "#ASI_M_DATAC_TAG" },
2122
  { 0x0F, "#ASI_M_DATAC_DATA" },
2123
  { 0x10, "#ASI_M_FLUSH_PAGE" },
2124
  { 0x11, "#ASI_M_FLUSH_SEG" },
2125
  { 0x12, "#ASI_M_FLUSH_REGION" },
2126
  { 0x13, "#ASI_M_FLUSH_CTX" },
2127
  { 0x14, "#ASI_M_FLUSH_USER" },
2128
  { 0x17, "#ASI_M_BCOPY" },
2129
  { 0x18, "#ASI_M_IFLUSH_PAGE" },
2130
  { 0x19, "#ASI_M_IFLUSH_SEG" },
2131
  { 0x1A, "#ASI_M_IFLUSH_REGION" },
2132
  { 0x1B, "#ASI_M_IFLUSH_CTX" },
2133
  { 0x1C, "#ASI_M_IFLUSH_USER" },
2134
  { 0x1F, "#ASI_M_BFILL" },
2135
  { 0x20, "#ASI_M_BYPASS" },
2136
  { 0x29, "#ASI_M_FBMEM" },
2137
  { 0x2A, "#ASI_M_VMEUS" },
2138
  { 0x2B, "#ASI_M_VMEPS" },
2139
  { 0x2C, "#ASI_M_VMEUT" },
2140
  { 0x2D, "#ASI_M_VMEPT" },
2141
  { 0x2E, "#ASI_M_SBUS" },
2142
  { 0x2F, "#ASI_M_CTL" },
2143
  { 0x31, "#ASI_M_FLUSH_IWHOLE" },
2144
  { 0x36, "#ASI_M_IC_FLCLEAR" },
2145
  { 0x37, "#ASI_M_DC_FLCLEAR" },
2146
  { 0x39, "#ASI_M_DCDR" },
2147
  { 0x40, "#ASI_M_VIKING_TMP1" },
2148
  { 0x41, "#ASI_M_VIKING_TMP2" },
2149
  { 0x4c, "#ASI_M_ACTION" },
2150
  { 0, 0 }
2151
};
2152

    
2153
static const arg asi_table_v9[] =
2154
{
2155
  /* These are in the v9 architecture manual.  */
2156
  /* The shorter versions appear first, they're here because Sun's as has them.
2157
     Sun's as uses #ASI_P_L instead of #ASI_PL (which appears in the
2158
     UltraSPARC architecture manual).  */
2159
  { 0x04, "#ASI_N" },
2160
  { 0x0c, "#ASI_N_L" },
2161
  { 0x10, "#ASI_AIUP" },
2162
  { 0x11, "#ASI_AIUS" },
2163
  { 0x18, "#ASI_AIUP_L" },