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/*
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 *  Alpha emulation cpu definitions for qemu.
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 *
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 *  Copyright (c) 2007 Jocelyn Mayer
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#if !defined (__CPU_ALPHA_H__)
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#define __CPU_ALPHA_H__
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#include "config.h"
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#define TARGET_LONG_BITS 64
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#include "cpu-defs.h"
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#include <setjmp.h>
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#include "softfloat.h"
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/* XXX: put this in a common place */
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#define likely(x)   __builtin_expect(!!(x), 1)
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#define unlikely(x)   __builtin_expect(!!(x), 0)
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#define TARGET_HAS_ICE 1
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#define ELF_MACHINE        EM_ALPHA
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#define ICACHE_LINE_SIZE 32
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#define DCACHE_LINE_SIZE 32
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#define TARGET_PAGE_BITS 12
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#define VA_BITS 43
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/* Alpha major type */
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enum {
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    ALPHA_EV3  = 1,
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    ALPHA_EV4  = 2,
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    ALPHA_SIM  = 3,
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    ALPHA_LCA  = 4,
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    ALPHA_EV5  = 5, /* 21164 */
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    ALPHA_EV45 = 6, /* 21064A */
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    ALPHA_EV56 = 7, /* 21164A */
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};
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/* EV4 minor type */
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enum {
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    ALPHA_EV4_2 = 0,
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    ALPHA_EV4_3 = 1,
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};
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/* LCA minor type */
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enum {
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    ALPHA_LCA_1 = 1, /* 21066 */
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    ALPHA_LCA_2 = 2, /* 20166 */
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    ALPHA_LCA_3 = 3, /* 21068 */
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    ALPHA_LCA_4 = 4, /* 21068 */
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    ALPHA_LCA_5 = 5, /* 21066A */
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    ALPHA_LCA_6 = 6, /* 21068A */
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};
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/* EV5 minor type */
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enum {
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    ALPHA_EV5_1 = 1, /* Rev BA, CA */
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    ALPHA_EV5_2 = 2, /* Rev DA, EA */
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    ALPHA_EV5_3 = 3, /* Pass 3 */
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    ALPHA_EV5_4 = 4, /* Pass 3.2 */
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    ALPHA_EV5_5 = 5, /* Pass 4 */
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};
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/* EV45 minor type */
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enum {
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    ALPHA_EV45_1 = 1, /* Pass 1 */
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    ALPHA_EV45_2 = 2, /* Pass 1.1 */
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    ALPHA_EV45_3 = 3, /* Pass 2 */
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};
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/* EV56 minor type */
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enum {
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    ALPHA_EV56_1 = 1, /* Pass 1 */
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    ALPHA_EV56_2 = 2, /* Pass 2 */
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};
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enum {
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    IMPLVER_2106x = 0, /* EV4, EV45 & LCA45 */
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    IMPLVER_21164 = 1, /* EV5, EV56 & PCA45 */
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    IMPLVER_21264 = 2, /* EV6, EV67 & EV68x */
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    IMPLVER_21364 = 3, /* EV7 & EV79 */
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};
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enum {
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    AMASK_BWX      = 0x00000001,
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    AMASK_FIX      = 0x00000002,
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    AMASK_CIX      = 0x00000004,
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    AMASK_MVI      = 0x00000100,
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    AMASK_TRAP     = 0x00000200,
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    AMASK_PREFETCH = 0x00001000,
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};
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enum {
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    VAX_ROUND_NORMAL = 0,
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    VAX_ROUND_CHOPPED,
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};
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enum {
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    IEEE_ROUND_NORMAL = 0,
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    IEEE_ROUND_DYNAMIC,
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    IEEE_ROUND_PLUS,
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    IEEE_ROUND_MINUS,
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    IEEE_ROUND_CHOPPED,
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};
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/* IEEE floating-point operations encoding */
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/* Trap mode */
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enum {
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    FP_TRAP_I   = 0x0,
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    FP_TRAP_U   = 0x1,
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    FP_TRAP_S  = 0x4,
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    FP_TRAP_SU  = 0x5,
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    FP_TRAP_SUI = 0x7,
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};
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/* Rounding mode */
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enum {
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    FP_ROUND_CHOPPED = 0x0,
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    FP_ROUND_MINUS   = 0x1,
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    FP_ROUND_NORMAL  = 0x2,
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    FP_ROUND_DYNAMIC = 0x3,
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};
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/* Internal processor registers */
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/* XXX: TOFIX: most of those registers are implementation dependant */
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enum {
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    /* Ebox IPRs */
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    IPR_CC           = 0xC0,
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    IPR_CC_CTL       = 0xC1,
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    IPR_VA           = 0xC2,
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    IPR_VA_CTL       = 0xC4,
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    IPR_VA_FORM      = 0xC3,
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    /* Ibox IPRs */
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    IPR_ITB_TAG      = 0x00,
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    IPR_ITB_PTE      = 0x01,
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    IPT_ITB_IAP      = 0x02,
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    IPT_ITB_IA       = 0x03,
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    IPT_ITB_IS       = 0x04,
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    IPR_PMPC         = 0x05,
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    IPR_EXC_ADDR     = 0x06,
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    IPR_IVA_FORM     = 0x07,
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    IPR_CM           = 0x09,
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    IPR_IER          = 0x0A,
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    IPR_SIRR         = 0x0C,
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    IPR_ISUM         = 0x0D,
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    IPR_HW_INT_CLR   = 0x0E,
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    IPR_EXC_SUM      = 0x0F,
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    IPR_PAL_BASE     = 0x10,
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    IPR_I_CTL        = 0x11,
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    IPR_I_STAT       = 0x16,
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    IPR_IC_FLUSH     = 0x13,
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    IPR_IC_FLUSH_ASM = 0x12,
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    IPR_CLR_MAP      = 0x15,
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    IPR_SLEEP        = 0x17,
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    IPR_PCTX         = 0x40,
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    IPR_PCTR_CTL     = 0x14,
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    /* Mbox IPRs */
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    IPR_DTB_TAG0     = 0x20,
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    IPR_DTB_TAG1     = 0xA0,
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    IPR_DTB_PTE0     = 0x21,
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    IPR_DTB_PTE1     = 0xA1,
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    IPR_DTB_ALTMODE  = 0xA6,
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    IPR_DTB_IAP      = 0xA2,
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    IPR_DTB_IA       = 0xA3,
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    IPR_DTB_IS0      = 0x24,
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    IPR_DTB_IS1      = 0xA4,
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    IPR_DTB_ASN0     = 0x25,
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    IPR_DTB_ASN1     = 0xA5,
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    IPR_MM_STAT      = 0x27,
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    IPR_M_CTL        = 0x28,
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    IPR_DC_CTL       = 0x29,
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    IPR_DC_STAT      = 0x2A,
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    /* Cbox IPRs */
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    IPR_C_DATA       = 0x2B,
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    IPR_C_SHIFT      = 0x2C,
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    IPR_ASN,
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    IPR_ASTEN,
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    IPR_ASTSR,
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    IPR_DATFX,
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    IPR_ESP,
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    IPR_FEN,
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    IPR_IPIR,
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    IPR_IPL,
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    IPR_KSP,
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    IPR_MCES,
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    IPR_PERFMON,
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    IPR_PCBB,
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    IPR_PRBR,
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    IPR_PTBR,
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    IPR_SCBB,
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    IPR_SISR,
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    IPR_SSP,
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    IPR_SYSPTBR,
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    IPR_TBCHK,
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    IPR_TBIA,
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    IPR_TBIAP,
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    IPR_TBIS,
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    IPR_TBISD,
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    IPR_TBISI,
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    IPR_USP,
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    IPR_VIRBND,
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    IPR_VPTB,
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    IPR_WHAMI,
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    IPR_ALT_MODE,
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    IPR_LAST,
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};
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typedef struct CPUAlphaState CPUAlphaState;
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typedef struct pal_handler_t pal_handler_t;
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struct pal_handler_t {
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    /* Reset */
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    void (*reset)(CPUAlphaState *env);
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    /* Uncorrectable hardware error */
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    void (*machine_check)(CPUAlphaState *env);
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    /* Arithmetic exception */
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    void (*arithmetic)(CPUAlphaState *env);
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    /* Interrupt / correctable hardware error */
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    void (*interrupt)(CPUAlphaState *env);
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    /* Data fault */
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    void (*dfault)(CPUAlphaState *env);
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    /* DTB miss pal */
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    void (*dtb_miss_pal)(CPUAlphaState *env);
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    /* DTB miss native */
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    void (*dtb_miss_native)(CPUAlphaState *env);
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    /* Unaligned access */
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    void (*unalign)(CPUAlphaState *env);
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    /* ITB miss */
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    void (*itb_miss)(CPUAlphaState *env);
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    /* Instruction stream access violation */
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    void (*itb_acv)(CPUAlphaState *env);
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    /* Reserved or privileged opcode */
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    void (*opcdec)(CPUAlphaState *env);
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    /* Floating point exception */
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    void (*fen)(CPUAlphaState *env);
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    /* Call pal instruction */
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    void (*call_pal)(CPUAlphaState *env, uint32_t palcode);
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};
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struct CPUAlphaState {
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    uint64_t ir[31];
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    float64  fir[31];
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    float_status fp_status;
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    uint64_t fpcr;
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    uint64_t pc;
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    uint64_t lock;
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    uint32_t pcc[2];
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    uint64_t ipr[IPR_LAST];
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    uint64_t ps;
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    uint64_t unique;
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    int saved_mode; /* Used for HW_LD / HW_ST */
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#if TARGET_LONG_BITS > HOST_LONG_BITS
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    /* temporary fixed-point registers
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     * used to emulate 64 bits target on 32 bits hosts
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     */
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    target_ulong t0, t1, t2;
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#endif
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    /* */
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    double ft0, ft1, ft2;
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    /* Those resources are used only in Qemu core */
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    CPU_COMMON
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    jmp_buf jmp_env;
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    int user_mode_only; /* user mode only simulation */
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    uint32_t hflags;
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    int halted;
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    int exception_index;
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    int error_code;
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    int interrupt_request;
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    uint32_t features;
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    uint32_t amask;
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    int implver;
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    pal_handler_t *pal_handler;
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};
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#define CPUState CPUAlphaState
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#define cpu_init cpu_alpha_init
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#define cpu_exec cpu_alpha_exec
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#define cpu_gen_code cpu_alpha_gen_code
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#define cpu_signal_handler cpu_alpha_signal_handler
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#include "cpu-all.h"
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enum {
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    FEATURE_ASN    = 0x00000001,
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    FEATURE_SPS    = 0x00000002,
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    FEATURE_VIRBND = 0x00000004,
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    FEATURE_TBCHK  = 0x00000008,
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};
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enum {
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    EXCP_RESET            = 0x0000,
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    EXCP_MCHK             = 0x0020,
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    EXCP_ARITH            = 0x0060,
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    EXCP_HW_INTERRUPT     = 0x00E0,
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    EXCP_DFAULT           = 0x01E0,
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    EXCP_DTB_MISS_PAL     = 0x09E0,
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    EXCP_ITB_MISS         = 0x03E0,
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    EXCP_ITB_ACV          = 0x07E0,
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    EXCP_DTB_MISS_NATIVE  = 0x08E0,
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    EXCP_UNALIGN          = 0x11E0,
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    EXCP_OPCDEC           = 0x13E0,
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    EXCP_FEN              = 0x17E0,
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    EXCP_CALL_PAL         = 0x2000,
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    EXCP_CALL_PALP        = 0x3000,
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    EXCP_CALL_PALE        = 0x4000,
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    /* Pseudo exception for console */
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    EXCP_CONSOLE_DISPATCH = 0x4001,
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    EXCP_CONSOLE_FIXUP    = 0x4002,
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};
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/* Arithmetic exception */
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enum {
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    EXCP_ARITH_OVERFLOW,
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};
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enum {
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    PALCODE_CALL = 0x00000000,
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    PALCODE_LD   = 0x01000000,
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    PALCODE_ST   = 0x02000000,
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    PALCODE_MFPR = 0x03000000,
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    PALCODE_MTPR = 0x04000000,
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    PALCODE_REI  = 0x05000000,
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    PALCODE_INIT = 0xF0000000,
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};
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enum {
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    IR_V0   = 0,
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    IR_T0   = 1,
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    IR_T1   = 2,
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    IR_T2   = 3,
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    IR_T3   = 4,
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    IR_T4   = 5,
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    IR_T5   = 6,
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    IR_T6   = 7,
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    IR_T7   = 8,
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    IR_S0   = 9,
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    IR_S1   = 10,
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    IR_S2   = 11,
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    IR_S3   = 12,
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    IR_S4   = 13,
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    IR_S5   = 14,
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    IR_S6   = 15,
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#define IR_FP IR_S6
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    IR_A0   = 16,
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    IR_A1   = 17,
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    IR_A2   = 18,
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    IR_A3   = 19,
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    IR_A4   = 20,
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    IR_A5   = 21,
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    IR_T8   = 22,
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    IR_T9   = 23,
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    IR_T10  = 24,
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    IR_T11  = 25,
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    IR_RA   = 26,
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    IR_T12  = 27,
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#define IR_PV IR_T12
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    IR_AT   = 28,
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    IR_GP   = 29,
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    IR_SP   = 30,
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    IR_ZERO = 31,
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};
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CPUAlphaState * cpu_alpha_init (void);
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int cpu_alpha_exec(CPUAlphaState *s);
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/* you can call this signal handler from your SIGBUS and SIGSEGV
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   signal handlers to inform the virtual CPU of exceptions. non zero
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   is returned if the signal was handled by the virtual CPU.  */
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int cpu_alpha_signal_handler(int host_signum, void *pinfo,
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                             void *puc);
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int cpu_alpha_mfpr (CPUState *env, int iprn, uint64_t *valp);
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int cpu_alpha_mtpr (CPUState *env, int iprn, uint64_t val, uint64_t *oldvalp);
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void cpu_loop_exit (void);
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void pal_init (CPUState *env);
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void call_pal (CPUState *env, int palcode);
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#endif /* !defined (__CPU_ALPHA_H__) */