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/*
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 *  Alpha emulation cpu helpers for qemu.
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 *
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 *  Copyright (c) 2007 Jocelyn Mayer
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include <stdint.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include "cpu.h"
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#include "exec-all.h"
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#if defined(CONFIG_USER_ONLY)
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int cpu_alpha_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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                                int is_user, int is_softmmu)
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{
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    if (rw == 2)
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        env->exception_index = EXCP_ITB_MISS;
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    else
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        env->exception_index = EXCP_DFAULT;
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    env->ipr[IPR_EXC_ADDR] = address;
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    return 1;
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}
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target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
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{
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    return addr;
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}
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void do_interrupt (CPUState *env)
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{
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    env->exception_index = -1;
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}
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#else
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target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
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{
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    return -1;
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}
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int cpu_alpha_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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                                int is_user, int is_softmmu)
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{
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    uint32_t opc;
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    if (rw == 2) {
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        /* Instruction translation buffer miss */
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        env->exception_index = EXCP_ITB_MISS;
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    } else {
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        if (env->ipr[IPR_EXC_ADDR] & 1)
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            env->exception_index = EXCP_DTB_MISS_PAL;
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        else
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            env->exception_index = EXCP_DTB_MISS_NATIVE;
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        opc = (ldl_code(env->pc) >> 21) << 4;
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        if (rw) {
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            opc |= 0x9;
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        } else {
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            opc |= 0x4;
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        }
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        env->ipr[IPR_MM_STAT] = opc;
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    }
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    return 1;
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}
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int cpu_alpha_mfpr (CPUState *env, int iprn, uint64_t *valp)
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{
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    uint64_t hwpcb;
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    int ret = 0;
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    hwpcb = env->ipr[IPR_PCBB];
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    switch (iprn) {
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    case IPR_ASN:
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        if (env->features & FEATURE_ASN)
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            *valp = env->ipr[IPR_ASN];
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        else
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            *valp = 0;
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        break;
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    case IPR_ASTEN:
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        *valp = ((int64_t)(env->ipr[IPR_ASTEN] << 60)) >> 60;
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        break;
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    case IPR_ASTSR:
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        *valp = ((int64_t)(env->ipr[IPR_ASTSR] << 60)) >> 60;
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        break;
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    case IPR_DATFX:
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        /* Write only */
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        ret = -1;
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        break;
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    case IPR_ESP:
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        if (env->features & FEATURE_SPS)
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            *valp = env->ipr[IPR_ESP];
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        else
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            *valp = ldq_raw(hwpcb + 8);
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        break;
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    case IPR_FEN:
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        *valp = ((int64_t)(env->ipr[IPR_FEN] << 63)) >> 63;
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        break;
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    case IPR_IPIR:
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        /* Write-only */
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        ret = -1;
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        break;
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    case IPR_IPL:
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        *valp = ((int64_t)(env->ipr[IPR_IPL] << 59)) >> 59;
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        break;
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    case IPR_KSP:
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        if (!(env->ipr[IPR_EXC_ADDR] & 1)) {
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            ret = -1;
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        } else {
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            if (env->features & FEATURE_SPS)
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                *valp = env->ipr[IPR_KSP];
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            else
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                *valp = ldq_raw(hwpcb + 0);
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        }
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        break;
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    case IPR_MCES:
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        *valp = ((int64_t)(env->ipr[IPR_MCES] << 59)) >> 59;
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        break;
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    case IPR_PERFMON:
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        /* Implementation specific */
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        *valp = 0;
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        break;
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    case IPR_PCBB:
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        *valp = ((int64_t)env->ipr[IPR_PCBB] << 16) >> 16;
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        break;
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    case IPR_PRBR:
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        *valp = env->ipr[IPR_PRBR];
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        break;
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    case IPR_PTBR:
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        *valp = env->ipr[IPR_PTBR];
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        break;
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    case IPR_SCBB:
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        *valp = (int64_t)((int32_t)env->ipr[IPR_SCBB]);
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        break;
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    case IPR_SIRR:
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        /* Write-only */
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        ret = -1;
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        break;
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    case IPR_SISR:
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        *valp = (int64_t)((int16_t)env->ipr[IPR_SISR]);
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    case IPR_SSP:
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        if (env->features & FEATURE_SPS)
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            *valp = env->ipr[IPR_SSP];
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        else
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            *valp = ldq_raw(hwpcb + 16);
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        break;
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    case IPR_SYSPTBR:
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        if (env->features & FEATURE_VIRBND)
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            *valp = env->ipr[IPR_SYSPTBR];
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        else
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            ret = -1;
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        break;
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    case IPR_TBCHK:
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        if ((env->features & FEATURE_TBCHK)) {
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            /* XXX: TODO */
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            *valp = 0;
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            ret = -1;
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        } else {
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            ret = -1;
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        }
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        break;
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    case IPR_TBIA:
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        /* Write-only */
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        ret = -1;
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        break;
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    case IPR_TBIAP:
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        /* Write-only */
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        ret = -1;
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        break;
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    case IPR_TBIS:
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        /* Write-only */
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        ret = -1;
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        break;
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    case IPR_TBISD:
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        /* Write-only */
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        ret = -1;
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        break;
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    case IPR_TBISI:
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        /* Write-only */
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        ret = -1;
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        break;
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    case IPR_USP:
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        if (env->features & FEATURE_SPS)
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            *valp = env->ipr[IPR_USP];
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        else
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            *valp = ldq_raw(hwpcb + 24);
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        break;
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    case IPR_VIRBND:
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        if (env->features & FEATURE_VIRBND)
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            *valp = env->ipr[IPR_VIRBND];
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        else
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            ret = -1;
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        break;
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    case IPR_VPTB:
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        *valp = env->ipr[IPR_VPTB];
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        break;
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    case IPR_WHAMI:
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        *valp = env->ipr[IPR_WHAMI];
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        break;
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    default:
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        /* Invalid */
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        ret = -1;
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        break;
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    }
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    return ret;
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}
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int cpu_alpha_mtpr (CPUState *env, int iprn, uint64_t val, uint64_t *oldvalp)
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{
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    uint64_t hwpcb, tmp64;
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    uint8_t tmp8;
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    int ret = 0;
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    hwpcb = env->ipr[IPR_PCBB];
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    switch (iprn) {
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    case IPR_ASN:
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        /* Read-only */
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        ret = -1;
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        break;
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    case IPR_ASTEN:
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        tmp8 = ((int8_t)(env->ipr[IPR_ASTEN] << 4)) >> 4;
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        *oldvalp = tmp8;
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        tmp8 &= val & 0xF;
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        tmp8 |= (val >> 4) & 0xF;
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        env->ipr[IPR_ASTEN] &= ~0xF;
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        env->ipr[IPR_ASTEN] |= tmp8;
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        ret = 1;
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        break;
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    case IPR_ASTSR:
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        tmp8 = ((int8_t)(env->ipr[IPR_ASTSR] << 4)) >> 4;
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        *oldvalp = tmp8;
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        tmp8 &= val & 0xF;
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        tmp8 |= (val >> 4) & 0xF;
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        env->ipr[IPR_ASTSR] &= ~0xF;
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        env->ipr[IPR_ASTSR] |= tmp8;
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        ret = 1;
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    case IPR_DATFX:
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        env->ipr[IPR_DATFX] &= ~0x1;
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        env->ipr[IPR_DATFX] |= val & 1;
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        tmp64 = ldq_raw(hwpcb + 56);
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        tmp64 &= ~0x8000000000000000ULL;
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        tmp64 |= (val & 1) << 63;
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        stq_raw(hwpcb + 56, tmp64);
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        break;
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    case IPR_ESP:
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        if (env->features & FEATURE_SPS)
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            env->ipr[IPR_ESP] = val;
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        else
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            stq_raw(hwpcb + 8, val);
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        break;
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    case IPR_FEN:
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        env->ipr[IPR_FEN] = val & 1;
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        tmp64 = ldq_raw(hwpcb + 56);
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        tmp64 &= ~1;
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        tmp64 |= val & 1;
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        stq_raw(hwpcb + 56, tmp64);
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        break;
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    case IPR_IPIR:
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        /* XXX: TODO: Send IRQ to CPU #ir[16] */
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        break;
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    case IPR_IPL:
280
        *oldvalp = ((int64_t)(env->ipr[IPR_IPL] << 59)) >> 59;
281
        env->ipr[IPR_IPL] &= ~0x1F;
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        env->ipr[IPR_IPL] |= val & 0x1F;
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        /* XXX: may issue an interrupt or ASR _now_ */
284
        ret = 1;
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        break;
286
    case IPR_KSP:
287
        if (!(env->ipr[IPR_EXC_ADDR] & 1)) {
288
            ret = -1;
289
        } else {
290
            if (env->features & FEATURE_SPS)
291
                env->ipr[IPR_KSP] = val;
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            else
293
                stq_raw(hwpcb + 0, val);
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        }
295
        break;
296
    case IPR_MCES:
297
        env->ipr[IPR_MCES] &= ~((val & 0x7) | 0x18);
298
        env->ipr[IPR_MCES] |= val & 0x18;
299
        break;
300
    case IPR_PERFMON:
301
        /* Implementation specific */
302
        *oldvalp = 0;
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        ret = 1;
304
        break;
305
    case IPR_PCBB:
306
        /* Read-only */
307
        ret = -1;
308
        break;
309
    case IPR_PRBR:
310
        env->ipr[IPR_PRBR] = val;
311
        break;
312
    case IPR_PTBR:
313
        /* Read-only */
314
        ret = -1;
315
        break;
316
    case IPR_SCBB:
317
        env->ipr[IPR_SCBB] = (uint32_t)val;
318
        break;
319
    case IPR_SIRR:
320
        if (val & 0xF) {
321
            env->ipr[IPR_SISR] |= 1 << (val & 0xF);
322
            /* XXX: request a software interrupt _now_ */
323
        }
324
        break;
325
    case IPR_SISR:
326
        /* Read-only */
327
        ret = -1;
328
        break;
329
    case IPR_SSP:
330
        if (env->features & FEATURE_SPS)
331
            env->ipr[IPR_SSP] = val;
332
        else
333
            stq_raw(hwpcb + 16, val);
334
        break;
335
    case IPR_SYSPTBR:
336
        if (env->features & FEATURE_VIRBND)
337
            env->ipr[IPR_SYSPTBR] = val;
338
        else
339
            ret = -1;
340
    case IPR_TBCHK:
341
        /* Read-only */
342
        ret = -1;
343
        break;
344
    case IPR_TBIA:
345
        tlb_flush(env, 1);
346
        break;
347
    case IPR_TBIAP:
348
        tlb_flush(env, 1);
349
        break;
350
    case IPR_TBIS:
351
        tlb_flush_page(env, val);
352
        break;
353
    case IPR_TBISD:
354
        tlb_flush_page(env, val);
355
        break;
356
    case IPR_TBISI:
357
        tlb_flush_page(env, val);
358
        break;
359
    case IPR_USP:
360
        if (env->features & FEATURE_SPS)
361
            env->ipr[IPR_USP] = val;
362
        else
363
            stq_raw(hwpcb + 24, val);
364
        break;
365
    case IPR_VIRBND:
366
        if (env->features & FEATURE_VIRBND)
367
            env->ipr[IPR_VIRBND] = val;
368
        else
369
            ret = -1;
370
        break;
371
    case IPR_VPTB:
372
        env->ipr[IPR_VPTB] = val;
373
        break;
374
    case IPR_WHAMI:
375
        /* Read-only */
376
        ret = -1;
377
        break;
378
    default:
379
        /* Invalid */
380
        ret = -1;
381
        break;
382
    }
383

    
384
    return ret;
385
}
386

    
387
void do_interrupt (CPUState *env)
388
{
389
    int excp;
390

    
391
    env->ipr[IPR_EXC_ADDR] = env->pc | 1;
392
    excp = env->exception_index;
393
    env->exception_index = 0;
394
    env->error_code = 0;
395
    /* XXX: disable interrupts and memory mapping */
396
    if (env->ipr[IPR_PAL_BASE] != -1ULL) {
397
        /* We use native PALcode */
398
        env->pc = env->ipr[IPR_PAL_BASE] + excp;
399
    } else {
400
        /* We use emulated PALcode */
401
        call_pal(env);
402
        /* Emulate REI */
403
        env->pc = env->ipr[IPR_EXC_ADDR] & ~7;
404
        env->ipr[IPR_EXC_ADDR] = env->ipr[IPR_EXC_ADDR] & 1;
405
        /* XXX: re-enable interrupts and memory mapping */
406
    }
407
}
408
#endif
409

    
410
void cpu_dump_state (CPUState *env, FILE *f,
411
                     int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
412
                     int flags)
413
{
414
    static unsigned char *linux_reg_names[] = {
415
        "v0 ", "t0 ", "t1 ", "t2 ", "t3 ", "t4 ", "t5 ", "t6 ",
416
        "t7 ", "s0 ", "s1 ", "s2 ", "s3 ", "s4 ", "s5 ", "fp ",
417
        "a0 ", "a1 ", "a2 ", "a3 ", "a4 ", "a5 ", "t8 ", "t9 ",
418
        "t10", "t11", "ra ", "t12", "at ", "gp ", "sp ", "zero",
419
    };
420
    int i;
421

    
422
    cpu_fprintf(f, "     PC  " TARGET_FMT_lx "      PS  " TARGET_FMT_lx "\n",
423
                env->pc, env->ps);
424
    for (i = 0; i < 31; i++) {
425
        cpu_fprintf(f, "IR%02d %s " TARGET_FMT_lx " ", i,
426
                    linux_reg_names[i], env->ir[i]);
427
        if ((i % 3) == 2)
428
            cpu_fprintf(f, "\n");
429
    }
430
    cpu_fprintf(f, "\n");
431
    for (i = 0; i < 31; i++) {
432
        cpu_fprintf(f, "FIR%02d    " TARGET_FMT_lx " ", i,
433
                    *((uint64_t *)(&env->fir[i])));
434
        if ((i % 3) == 2)
435
            cpu_fprintf(f, "\n");
436
    }
437
    cpu_fprintf(f, "FT " TARGET_FMT_lx " " TARGET_FMT_lx " " TARGET_FMT_lx,
438
                *((uint64_t *)(&env->ft0)), *((uint64_t *)(&env->ft1)),
439
                *((uint64_t *)(&env->ft2)));
440
    cpu_fprintf(f, "\nMEM " TARGET_FMT_lx " %d %d\n",
441
                ldq_raw(0x000000004007df60ULL),
442
                (uint8_t *)(&env->ft0), (uint8_t *)(&env->fir[0]));
443
}
444

    
445
void cpu_dump_EA (target_ulong EA)
446
{
447
    FILE *f;
448

    
449
    if (logfile)
450
        f = logfile;
451
    else
452
        f = stdout;
453
    fprintf(f, "Memory access at address " TARGET_FMT_lx "\n", EA);
454
}