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/*
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 * ARM virtual CPU header
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 *
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 *  Copyright (c) 2003 Fabrice Bellard
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#ifndef CPU_ARM_H
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#define CPU_ARM_H
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#define TARGET_LONG_BITS 32
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#define ELF_MACHINE        EM_ARM
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#include "cpu-defs.h"
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#include "softfloat.h"
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#define TARGET_HAS_ICE 1
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#define EXCP_UDEF            1   /* undefined instruction */
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#define EXCP_SWI             2   /* software interrupt */
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#define EXCP_PREFETCH_ABORT  3
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#define EXCP_DATA_ABORT      4
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#define EXCP_IRQ             5
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#define EXCP_FIQ             6
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#define EXCP_BKPT            7
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typedef void ARMWriteCPFunc(void *opaque, int cp_info,
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                            int srcreg, int operand, uint32_t value);
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typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
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                               int dstreg, int operand);
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/* We currently assume float and double are IEEE single and double
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   precision respectively.
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   Doing runtime conversions is tricky because VFP registers may contain
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   integer values (eg. as the result of a FTOSI instruction).
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   s<2n> maps to the least significant half of d<n>
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   s<2n+1> maps to the most significant half of d<n>
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 */
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typedef struct CPUARMState {
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    /* Regs for current mode.  */
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    uint32_t regs[16];
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    /* Frequently accessed CPSR bits are stored separately for efficiently.
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       This contains all the other bits.  Use cpsr_{read,write} to access
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       the whole CPSR.  */
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    uint32_t uncached_cpsr;
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    uint32_t spsr;
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    /* Banked registers.  */
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    uint32_t banked_spsr[6];
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    uint32_t banked_r13[6];
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    uint32_t banked_r14[6];
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    /* These hold r8-r12.  */
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    uint32_t usr_regs[5];
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    uint32_t fiq_regs[5];
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    /* cpsr flag cache for faster execution */
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    uint32_t CF; /* 0 or 1 */
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    uint32_t VF; /* V is the bit 31. All other bits are undefined */
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    uint32_t NZF; /* N is bit 31. Z is computed from NZF */
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    uint32_t QF; /* 0 or 1 */
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    int thumb; /* 0 = arm mode, 1 = thumb mode */
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    /* System control coprocessor (cp15) */
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    struct {
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        uint32_t c0_cpuid;
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        uint32_t c0_cachetype;
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        uint32_t c1_sys; /* System control register.  */
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        uint32_t c1_coproc; /* Coprocessor access register.  */
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        uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
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        uint32_t c2_base; /* MMU translation table base.  */
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        uint32_t c2_data; /* MPU data cachable bits.  */
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        uint32_t c2_insn; /* MPU instruction cachable bits.  */
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        uint32_t c3; /* MMU domain access control register
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                        MPU write buffer control.  */
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        uint32_t c5_insn; /* Fault status registers.  */
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        uint32_t c5_data;
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        uint32_t c6_region[8]; /* MPU base/size registers.  */
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        uint32_t c6_insn; /* Fault address registers.  */
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        uint32_t c6_data;
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        uint32_t c9_insn; /* Cache lockdown registers.  */
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        uint32_t c9_data;
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        uint32_t c13_fcse; /* FCSE PID.  */
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        uint32_t c13_context; /* Context ID.  */
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        uint32_t c15_cpar; /* XScale Coprocessor Access Register */
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        uint32_t c15_ticonfig; /* TI925T configuration byte.  */
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        uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
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        uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
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        uint32_t c15_threadid; /* TI debugger thread-ID.  */
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    } cp15;
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    /* Coprocessor IO used by peripherals */
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    struct {
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        ARMReadCPFunc *cp_read;
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        ARMWriteCPFunc *cp_write;
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        void *opaque;
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    } cp[15];
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    /* Internal CPU feature flags.  */
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    uint32_t features;
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    /* exception/interrupt handling */
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    jmp_buf jmp_env;
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    int exception_index;
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    int interrupt_request;
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    int user_mode_only;
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    int halted;
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    /* VFP coprocessor state.  */
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    struct {
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        float64 regs[16];
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        uint32_t xregs[16];
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        /* We store these fpcsr fields separately for convenience.  */
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        int vec_len;
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        int vec_stride;
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        /* Temporary variables if we don't have spare fp regs.  */
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        float32 tmp0s, tmp1s;
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        float64 tmp0d, tmp1d;
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        float_status fp_status;
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    } vfp;
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    /* iwMMXt coprocessor state.  */
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    struct {
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        uint64_t regs[16];
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        uint64_t val;
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        uint32_t cregs[16];
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    } iwmmxt;
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#if defined(CONFIG_USER_ONLY)
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    /* For usermode syscall translation.  */
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    int eabi;
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#endif
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    CPU_COMMON
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    /* These fields after the common ones so they are preserved on reset.  */
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    int ram_size;
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    const char *kernel_filename;
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    const char *kernel_cmdline;
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    const char *initrd_filename;
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    int board_id;
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    target_phys_addr_t loader_start;
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} CPUARMState;
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CPUARMState *cpu_arm_init(void);
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int cpu_arm_exec(CPUARMState *s);
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void cpu_arm_close(CPUARMState *s);
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void do_interrupt(CPUARMState *);
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void switch_mode(CPUARMState *, int);
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/* you can call this signal handler from your SIGBUS and SIGSEGV
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   signal handlers to inform the virtual CPU of exceptions. non zero
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   is returned if the signal was handled by the virtual CPU.  */
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int cpu_arm_signal_handler(int host_signum, void *pinfo,
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                           void *puc);
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#define CPSR_M (0x1f)
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#define CPSR_T (1 << 5)
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#define CPSR_F (1 << 6)
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#define CPSR_I (1 << 7)
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#define CPSR_A (1 << 8)
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#define CPSR_E (1 << 9)
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#define CPSR_IT_2_7 (0xfc00)
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/* Bits 20-23 reserved.  */
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#define CPSR_J (1 << 24)
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#define CPSR_IT_0_1 (3 << 25)
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#define CPSR_Q (1 << 27)
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#define CPSR_NZCV (0xf << 28)
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#define CACHED_CPSR_BITS (CPSR_T | CPSR_Q | CPSR_NZCV)
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/* Return the current CPSR value.  */
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static inline uint32_t cpsr_read(CPUARMState *env)
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{
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    int ZF;
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    ZF = (env->NZF == 0);
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    return env->uncached_cpsr | (env->NZF & 0x80000000) | (ZF << 30) |
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        (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
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        | (env->thumb << 5);
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}
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/* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
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static inline void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
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{
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    /* NOTE: N = 1 and Z = 1 cannot be stored currently */
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    if (mask & CPSR_NZCV) {
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        env->NZF = (val & 0xc0000000) ^ 0x40000000;
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        env->CF = (val >> 29) & 1;
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        env->VF = (val << 3) & 0x80000000;
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    }
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    if (mask & CPSR_Q)
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        env->QF = ((val & CPSR_Q) != 0);
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    if (mask & CPSR_T)
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        env->thumb = ((val & CPSR_T) != 0);
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    if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
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        switch_mode(env, val & CPSR_M);
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    }
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    mask &= ~CACHED_CPSR_BITS;
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    env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
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}
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enum arm_cpu_mode {
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  ARM_CPU_MODE_USR = 0x10,
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  ARM_CPU_MODE_FIQ = 0x11,
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  ARM_CPU_MODE_IRQ = 0x12,
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  ARM_CPU_MODE_SVC = 0x13,
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  ARM_CPU_MODE_ABT = 0x17,
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  ARM_CPU_MODE_UND = 0x1b,
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  ARM_CPU_MODE_SYS = 0x1f
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};
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/* VFP system registers.  */
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#define ARM_VFP_FPSID   0
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#define ARM_VFP_FPSCR   1
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#define ARM_VFP_FPEXC   8
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#define ARM_VFP_FPINST  9
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#define ARM_VFP_FPINST2 10
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/* iwMMXt coprocessor control registers.  */
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#define ARM_IWMMXT_wCID                0
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#define ARM_IWMMXT_wCon                1
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#define ARM_IWMMXT_wCSSF        2
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#define ARM_IWMMXT_wCASF        3
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#define ARM_IWMMXT_wCGR0        8
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#define ARM_IWMMXT_wCGR1        9
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#define ARM_IWMMXT_wCGR2        10
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#define ARM_IWMMXT_wCGR3        11
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enum arm_features {
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    ARM_FEATURE_VFP,
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    ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
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    ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
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    ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
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    ARM_FEATURE_MPU,    /* Only has Memory Protection Unit, not full MMU.  */
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    ARM_FEATURE_OMAPCP  /* OMAP specific CP15 ops handling.  */
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};
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static inline int arm_feature(CPUARMState *env, int feature)
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{
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    return (env->features & (1u << feature)) != 0;
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}
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void arm_cpu_list(void);
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void cpu_arm_set_model(CPUARMState *env, const char *name);
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void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
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                       ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
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                       void *opaque);
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#define ARM_CPUID_ARM1026   0x4106a262
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#define ARM_CPUID_ARM926    0x41069265
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#define ARM_CPUID_ARM946    0x41059461
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#define ARM_CPUID_TI915T    0x54029152
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#define ARM_CPUID_TI925T    0x54029252
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#define ARM_CPUID_PXA250    0x69052100
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#define ARM_CPUID_PXA255    0x69052d00
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#define ARM_CPUID_PXA260    0x69052903
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#define ARM_CPUID_PXA261    0x69052d05
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#define ARM_CPUID_PXA262    0x69052d06
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#define ARM_CPUID_PXA270    0x69054110
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#define ARM_CPUID_PXA270_A0 0x69054110
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#define ARM_CPUID_PXA270_A1 0x69054111
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#define ARM_CPUID_PXA270_B0 0x69054112
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#define ARM_CPUID_PXA270_B1 0x69054113
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#define ARM_CPUID_PXA270_C0 0x69054114
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#define ARM_CPUID_PXA270_C5 0x69054117
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#if defined(CONFIG_USER_ONLY)
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#define TARGET_PAGE_BITS 12
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#else
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/* The ARM MMU allows 1k pages.  */
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/* ??? Linux doesn't actually use these, and they're deprecated in recent
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   architecture revisions.  Maybe a configure option to disable them.  */
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#define TARGET_PAGE_BITS 10
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#endif
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#define CPUState CPUARMState
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#define cpu_init cpu_arm_init
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#define cpu_exec cpu_arm_exec
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#define cpu_gen_code cpu_arm_gen_code
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#define cpu_signal_handler cpu_arm_signal_handler
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#include "cpu-all.h"
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#endif