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/*
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    NetWinder Floating Point Emulator
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    (c) Rebel.com, 1998-1999
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    Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
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    This program is free software; you can redistribute it and/or modify
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    it under the terms of the GNU General Public License as published by
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    the Free Software Foundation; either version 2 of the License, or
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    (at your option) any later version.
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    This program is distributed in the hope that it will be useful,
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    but WITHOUT ANY WARRANTY; without even the implied warranty of
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    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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    GNU General Public License for more details.
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    You should have received a copy of the GNU General Public License
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    along with this program; if not, write to the Free Software
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    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __FPSR_H__
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#define __FPSR_H__
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/*
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The FPSR is a 32 bit register consisting of 4 parts, each exactly
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one byte.
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        SYSTEM ID
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        EXCEPTION TRAP ENABLE BYTE
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        SYSTEM CONTROL BYTE
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        CUMULATIVE EXCEPTION FLAGS BYTE
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The FPCR is a 32 bit register consisting of bit flags.
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*/
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/* SYSTEM ID
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------------
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Note: the system id byte is read only  */
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typedef unsigned int FPSR;  /* type for floating point status register */
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typedef unsigned int FPCR;  /* type for floating point control register */
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#define MASK_SYSID                0xff000000
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#define BIT_HARDWARE                0x80000000
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#define FP_EMULATOR                0x01000000        /* System ID for emulator */
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#define FP_ACCELERATOR                0x81000000        /* System ID for FPA11 */
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/* EXCEPTION TRAP ENABLE BYTE
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----------------------------- */
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#define MASK_TRAP_ENABLE        0x00ff0000
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#define MASK_TRAP_ENABLE_STRICT        0x001f0000
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#define BIT_IXE                0x00100000   /* inexact exception enable */
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#define BIT_UFE                0x00080000   /* underflow exception enable */
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#define BIT_OFE                0x00040000   /* overflow exception enable */
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#define BIT_DZE                0x00020000   /* divide by zero exception enable */
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#define BIT_IOE                0x00010000   /* invalid operation exception enable */
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/* SYSTEM CONTROL BYTE
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---------------------- */
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#define MASK_SYSTEM_CONTROL        0x0000ff00
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#define MASK_TRAP_STRICT        0x00001f00
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#define BIT_AC        0x00001000        /* use alternative C-flag definition
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                                   for compares */
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#define BIT_EP        0x00000800        /* use expanded packed decimal format */
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#define BIT_SO        0x00000400        /* select synchronous operation of FPA */
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#define BIT_NE        0x00000200        /* NaN exception bit */
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#define BIT_ND        0x00000100        /* no denormalized numbers bit */
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/* CUMULATIVE EXCEPTION FLAGS BYTE
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---------------------------------- */
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#define MASK_EXCEPTION_FLAGS                0x000000ff
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#define MASK_EXCEPTION_FLAGS_STRICT        0x0000001f
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#define BIT_IXC                0x00000010        /* inexact exception flag */
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#define BIT_UFC                0x00000008        /* underflow exception flag */
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#define BIT_OFC                0x00000004        /* overfloat exception flag */
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#define BIT_DZC                0x00000002        /* divide by zero exception flag */
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#define BIT_IOC                0x00000001        /* invalid operation exception flag */
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/* Floating Point Control Register
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----------------------------------*/
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#define BIT_RU                0x80000000        /* rounded up bit */
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#define BIT_IE                0x10000000        /* inexact bit */
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#define BIT_MO                0x08000000        /* mantissa overflow bit */
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#define BIT_EO                0x04000000        /* exponent overflow bit */
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#define BIT_SB                0x00000800        /* store bounce */
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#define BIT_AB                0x00000400        /* arithmetic bounce */
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#define BIT_RE                0x00000200        /* rounding exception */
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#define BIT_DA                0x00000100        /* disable FPA */
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#define MASK_OP                0x00f08010        /* AU operation code */
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#define MASK_PR                0x00080080        /* AU precision */
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#define MASK_S1                0x00070000        /* AU source register 1 */
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#define MASK_S2                0x00000007        /* AU source register 2 */
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#define MASK_DS                0x00007000        /* AU destination register */
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#define MASK_RM                0x00000060        /* AU rounding mode */
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#define MASK_ALU        0x9cfff2ff        /* only ALU can write these bits */
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#define MASK_RESET        0x00000d00        /* bits set on reset, all others cleared */
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#define MASK_WFC        MASK_RESET
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#define MASK_RFC        ~MASK_RESET
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#endif