root / target-arm / op_iwmmxt.c @ 5fafdf24
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/*
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* iwMMXt micro operations for XScale.
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*
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* Copyright (c) 2007 OpenedHand, Ltd.
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* Written by Andrzej Zaborowski <andrew@openedhand.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#define M1 env->iwmmxt.regs[PARAM1]
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/* iwMMXt macros extracted from GNU gdb. */
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/* Set the SIMD wCASF flags for 8, 16, 32 or 64-bit operations. */
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#define SIMD8_SET( v, n, b) ((v != 0) << ((((b) + 1) * 4) + (n))) |
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#define SIMD16_SET(v, n, h) ((v != 0) << ((((h) + 1) * 8) + (n))) |
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#define SIMD32_SET(v, n, w) ((v != 0) << ((((w) + 1) * 16) + (n))) |
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#define SIMD64_SET(v, n) ((v != 0) << (32 + (n))) |
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/* Flags to pass as "n" above. */
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#define SIMD_NBIT -1 |
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#define SIMD_ZBIT -2 |
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#define SIMD_CBIT -3 |
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#define SIMD_VBIT -4 |
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/* Various status bit macros. */
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#define NBIT8(x) ((x) & 0x80) |
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#define NBIT16(x) ((x) & 0x8000) |
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#define NBIT32(x) ((x) & 0x80000000) |
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#define NBIT64(x) ((x) & 0x8000000000000000ULL) |
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#define ZBIT8(x) (((x) & 0xff) == 0) |
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#define ZBIT16(x) (((x) & 0xffff) == 0) |
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#define ZBIT32(x) (((x) & 0xffffffff) == 0) |
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#define ZBIT64(x) (x == 0) |
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/* Sign extension macros. */
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#define EXTEND8H(a) ((uint16_t) (int8_t) (a))
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#define EXTEND8(a) ((uint32_t) (int8_t) (a))
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#define EXTEND16(a) ((uint32_t) (int16_t) (a))
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#define EXTEND16S(a) ((int32_t) (int16_t) (a))
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#define EXTEND32(a) ((uint64_t) (int32_t) (a))
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void OPPROTO op_iwmmxt_movl_T0_T1_wRn(void) |
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{
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T0 = M1 & ~(uint32_t) 0;
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T1 = M1 >> 32;
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} |
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void OPPROTO op_iwmmxt_movl_wRn_T0_T1(void) |
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{
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M1 = ((uint64_t) T1 << 32) | T0;
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} |
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void OPPROTO op_iwmmxt_movq_M0_wRn(void) |
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{
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M0 = M1; |
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} |
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void OPPROTO op_iwmmxt_orq_M0_wRn(void) |
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{
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M0 |= M1; |
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} |
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void OPPROTO op_iwmmxt_andq_M0_wRn(void) |
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{
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M0 &= M1; |
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} |
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void OPPROTO op_iwmmxt_xorq_M0_wRn(void) |
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{
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M0 ^= M1; |
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} |
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void OPPROTO op_iwmmxt_maddsq_M0_wRn(void) |
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{
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M0 = (( |
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EXTEND16S((M0 >> 0) & 0xffff) * EXTEND16S((M1 >> 0) & 0xffff) + |
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EXTEND16S((M0 >> 16) & 0xffff) * EXTEND16S((M1 >> 16) & 0xffff) |
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) & 0xffffffff) | ((uint64_t) (
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EXTEND16S((M0 >> 32) & 0xffff) * EXTEND16S((M1 >> 32) & 0xffff) + |
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EXTEND16S((M0 >> 48) & 0xffff) * EXTEND16S((M1 >> 48) & 0xffff) |
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) << 32);
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} |
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void OPPROTO op_iwmmxt_madduq_M0_wRn(void) |
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{
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M0 = (( |
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((M0 >> 0) & 0xffff) * ((M1 >> 0) & 0xffff) + |
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((M0 >> 16) & 0xffff) * ((M1 >> 16) & 0xffff) |
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) & 0xffffffff) | ((
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((M0 >> 32) & 0xffff) * ((M1 >> 32) & 0xffff) + |
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((M0 >> 48) & 0xffff) * ((M1 >> 48) & 0xffff) |
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) << 32);
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} |
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void OPPROTO op_iwmmxt_sadb_M0_wRn(void) |
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{
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#define abs(x) (((x) >= 0) ? x : -x) |
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#define SADB(SHR) abs((int) ((M0 >> SHR) & 0xff) - (int) ((M1 >> SHR) & 0xff)) |
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M0 = |
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SADB(0) + SADB(8) + SADB(16) + SADB(24) + |
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SADB(32) + SADB(40) + SADB(48) + SADB(56); |
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#undef SADB
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} |
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void OPPROTO op_iwmmxt_sadw_M0_wRn(void) |
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{
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#define SADW(SHR) \
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abs((int) ((M0 >> SHR) & 0xffff) - (int) ((M1 >> SHR) & 0xffff)) |
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M0 = SADW(0) + SADW(16) + SADW(32) + SADW(48); |
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#undef SADW
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} |
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void OPPROTO op_iwmmxt_addl_M0_wRn(void) |
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{
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M0 += env->iwmmxt.regs[PARAM1] & 0xffffffff;
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} |
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void OPPROTO op_iwmmxt_mulsw_M0_wRn(void) |
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{
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#define MULS(SHR) ((uint64_t) ((( \
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EXTEND16S((M0 >> SHR) & 0xffff) * EXTEND16S((M1 >> SHR) & 0xffff) \ |
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) >> PARAM2) & 0xffff) << SHR)
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M0 = MULS(0) | MULS(16) | MULS(32) | MULS(48); |
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#undef MULS
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} |
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void OPPROTO op_iwmmxt_muluw_M0_wRn(void) |
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{
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#define MULU(SHR) ((uint64_t) ((( \
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((M0 >> SHR) & 0xffff) * ((M1 >> SHR) & 0xffff) \ |
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) >> PARAM2) & 0xffff) << SHR)
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M0 = MULU(0) | MULU(16) | MULU(32) | MULU(48); |
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#undef MULU
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} |
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void OPPROTO op_iwmmxt_macsw_M0_wRn(void) |
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{
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#define MACS(SHR) ( \
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EXTEND16((M0 >> SHR) & 0xffff) * EXTEND16S((M1 >> SHR) & 0xffff)) |
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M0 = (int64_t) (MACS(0) + MACS(16) + MACS(32) + MACS(48)); |
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#undef MACS
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} |
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void OPPROTO op_iwmmxt_macuw_M0_wRn(void) |
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{
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#define MACU(SHR) ( \
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(uint32_t) ((M0 >> SHR) & 0xffff) * \
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(uint32_t) ((M1 >> SHR) & 0xffff))
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M0 = MACU(0) + MACU(16) + MACU(32) + MACU(48); |
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#undef MACU
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} |
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void OPPROTO op_iwmmxt_addsq_M0_wRn(void) |
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{
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M0 = (int64_t) M0 + (int64_t) M1; |
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} |
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void OPPROTO op_iwmmxt_adduq_M0_wRn(void) |
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{
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M0 += M1; |
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} |
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void OPPROTO op_iwmmxt_movq_wRn_M0(void) |
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{
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M1 = M0; |
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} |
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void OPPROTO op_iwmmxt_movl_wCx_T0(void) |
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{
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env->iwmmxt.cregs[PARAM1] = T0; |
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} |
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void OPPROTO op_iwmmxt_movl_T0_wCx(void) |
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{
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T0 = env->iwmmxt.cregs[PARAM1]; |
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} |
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void OPPROTO op_iwmmxt_movl_T1_wCx(void) |
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{
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T1 = env->iwmmxt.cregs[PARAM1]; |
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} |
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void OPPROTO op_iwmmxt_set_mup(void) |
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{
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env->iwmmxt.cregs[ARM_IWMMXT_wCon] |= 2;
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} |
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void OPPROTO op_iwmmxt_set_cup(void) |
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{
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env->iwmmxt.cregs[ARM_IWMMXT_wCon] |= 1;
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} |
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void OPPROTO op_iwmmxt_setpsr_nz(void) |
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{
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env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
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SIMD64_SET((M0 == 0), SIMD_ZBIT) |
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SIMD64_SET((M0 & (1ULL << 63)), SIMD_NBIT); |
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} |
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void OPPROTO op_iwmmxt_negq_M0(void) |
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{
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M0 = ~M0; |
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} |
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#define NZBIT8(x, i) \
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SIMD8_SET(NBIT8((x) & 0xff), SIMD_NBIT, i) | \
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SIMD8_SET(ZBIT8((x) & 0xff), SIMD_ZBIT, i)
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#define NZBIT16(x, i) \
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SIMD16_SET(NBIT16((x) & 0xffff), SIMD_NBIT, i) | \
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SIMD16_SET(ZBIT16((x) & 0xffff), SIMD_ZBIT, i)
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#define NZBIT32(x, i) \
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SIMD32_SET(NBIT32((x) & 0xffffffff), SIMD_NBIT, i) | \
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SIMD32_SET(ZBIT32((x) & 0xffffffff), SIMD_ZBIT, i)
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#define NZBIT64(x) \
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SIMD64_SET(NBIT64(x), SIMD_NBIT) | \ |
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SIMD64_SET(ZBIT64(x), SIMD_ZBIT) |
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#define IWMMXT_OP_UNPACK(S, SH0, SH1, SH2, SH3) \
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void OPPROTO glue(op_iwmmxt_unpack, glue(S, b_M0_wRn))(void) \ |
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{ \
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M0 = \ |
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(((M0 >> SH0) & 0xff) << 0) | (((M1 >> SH0) & 0xff) << 8) | \ |
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(((M0 >> SH1) & 0xff) << 16) | (((M1 >> SH1) & 0xff) << 24) | \ |
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(((M0 >> SH2) & 0xff) << 32) | (((M1 >> SH2) & 0xff) << 40) | \ |
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(((M0 >> SH3) & 0xff) << 48) | (((M1 >> SH3) & 0xff) << 56); \ |
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env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \ |
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NZBIT8(M0 >> 0, 0) | NZBIT8(M0 >> 8, 1) | \ |
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NZBIT8(M0 >> 16, 2) | NZBIT8(M0 >> 24, 3) | \ |
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NZBIT8(M0 >> 32, 4) | NZBIT8(M0 >> 40, 5) | \ |
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NZBIT8(M0 >> 48, 6) | NZBIT8(M0 >> 56, 7); \ |
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} \ |
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void OPPROTO glue(op_iwmmxt_unpack, glue(S, w_M0_wRn))(void) \ |
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{ \
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M0 = \ |
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(((M0 >> SH0) & 0xffff) << 0) | \ |
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(((M1 >> SH0) & 0xffff) << 16) | \ |
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(((M0 >> SH2) & 0xffff) << 32) | \ |
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(((M1 >> SH2) & 0xffff) << 48); \ |
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env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \ |
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NZBIT8(M0 >> 0, 0) | NZBIT8(M0 >> 16, 1) | \ |
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NZBIT8(M0 >> 32, 2) | NZBIT8(M0 >> 48, 3); \ |
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} \ |
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void OPPROTO glue(op_iwmmxt_unpack, glue(S, l_M0_wRn))(void) \ |
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{ \
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M0 = \ |
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(((M0 >> SH0) & 0xffffffff) << 0) | \ |
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(((M1 >> SH0) & 0xffffffff) << 32); \ |
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env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \ |
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NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1); \ |
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} \ |
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void OPPROTO glue(op_iwmmxt_unpack, glue(S, ub_M0))(void) \ |
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{ \
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M0 = \ |
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(((M0 >> SH0) & 0xff) << 0) | \ |
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(((M0 >> SH1) & 0xff) << 16) | \ |
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(((M0 >> SH2) & 0xff) << 32) | \ |
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(((M0 >> SH3) & 0xff) << 48); \ |
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env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \ |
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NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) | \ |
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NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3); \ |
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} \ |
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void OPPROTO glue(op_iwmmxt_unpack, glue(S, uw_M0))(void) \ |
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{ \
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M0 = \ |
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(((M0 >> SH0) & 0xffff) << 0) | \ |
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(((M0 >> SH2) & 0xffff) << 32); \ |
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env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \ |
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NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1); \ |
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} \ |
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void OPPROTO glue(op_iwmmxt_unpack, glue(S, ul_M0))(void) \ |
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{ \
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M0 = (((M0 >> SH0) & 0xffffffff) << 0); \ |
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env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0 >> 0); \
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} \ |
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void OPPROTO glue(op_iwmmxt_unpack, glue(S, sb_M0))(void) \ |
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{ \
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M0 = \ |
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((uint64_t) EXTEND8H((M0 >> SH0) & 0xff) << 0) | \ |
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((uint64_t) EXTEND8H((M0 >> SH1) & 0xff) << 16) | \ |
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((uint64_t) EXTEND8H((M0 >> SH2) & 0xff) << 32) | \ |
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((uint64_t) EXTEND8H((M0 >> SH3) & 0xff) << 48); \ |
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env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \ |
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NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) | \ |
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NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3); \ |
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} \ |
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void OPPROTO glue(op_iwmmxt_unpack, glue(S, sw_M0))(void) \ |
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{ \
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M0 = \ |
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((uint64_t) EXTEND16((M0 >> SH0) & 0xffff) << 0) | \ |
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((uint64_t) EXTEND16((M0 >> SH2) & 0xffff) << 32); \ |
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env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \ |
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NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1); \ |
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} \ |
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void OPPROTO glue(op_iwmmxt_unpack, glue(S, sl_M0))(void) \ |
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{ \
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M0 = EXTEND32((M0 >> SH0) & 0xffffffff); \
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env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0 >> 0); \
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} |
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IWMMXT_OP_UNPACK(l, 0, 8, 16, 24) |
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IWMMXT_OP_UNPACK(h, 32, 40, 48, 56) |
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#define IWMMXT_OP_CMP(SUFF, Tb, Tw, Tl, O) \
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void OPPROTO glue(op_iwmmxt_, glue(SUFF, b_M0_wRn))(void) \ |
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{ \
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M0 = \ |
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CMP(0, Tb, O, 0xff) | CMP(8, Tb, O, 0xff) | \ |
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CMP(16, Tb, O, 0xff) | CMP(24, Tb, O, 0xff) | \ |
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CMP(32, Tb, O, 0xff) | CMP(40, Tb, O, 0xff) | \ |
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CMP(48, Tb, O, 0xff) | CMP(56, Tb, O, 0xff); \ |
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env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \ |
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NZBIT8(M0 >> 0, 0) | NZBIT8(M0 >> 8, 1) | \ |
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NZBIT8(M0 >> 16, 2) | NZBIT8(M0 >> 24, 3) | \ |
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NZBIT8(M0 >> 32, 4) | NZBIT8(M0 >> 40, 5) | \ |
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NZBIT8(M0 >> 48, 6) | NZBIT8(M0 >> 56, 7); \ |
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} \ |
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void OPPROTO glue(op_iwmmxt_, glue(SUFF, w_M0_wRn))(void) \ |
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{ \
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M0 = CMP(0, Tw, O, 0xffff) | CMP(16, Tw, O, 0xffff) | \ |
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CMP(32, Tw, O, 0xffff) | CMP(48, Tw, O, 0xffff); \ |
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env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \ |
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NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) | \ |
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NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3); \ |
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} \ |
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void OPPROTO glue(op_iwmmxt_, glue(SUFF, l_M0_wRn))(void) \ |
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{ \
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M0 = CMP(0, Tl, O, 0xffffffff) | \ |
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CMP(32, Tl, O, 0xffffffff); \ |
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env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \ |
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NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1); \ |
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} |
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#define CMP(SHR, TYPE, OPER, MASK) ((((TYPE) ((M0 >> SHR) & MASK) OPER \
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(TYPE) ((M1 >> SHR) & MASK)) ? (uint64_t) MASK : 0) << SHR)
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IWMMXT_OP_CMP(cmpeq, uint8_t, uint16_t, uint32_t, ==) |
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IWMMXT_OP_CMP(cmpgts, int8_t, int16_t, int32_t, >) |
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IWMMXT_OP_CMP(cmpgtu, uint8_t, uint16_t, uint32_t, >) |
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#undef CMP
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#define CMP(SHR, TYPE, OPER, MASK) ((((TYPE) ((M0 >> SHR) & MASK) OPER \
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(TYPE) ((M1 >> SHR) & MASK)) ? M0 : M1) & ((uint64_t) MASK << SHR)) |
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IWMMXT_OP_CMP(mins, int8_t, int16_t, int32_t, <) |
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IWMMXT_OP_CMP(minu, uint8_t, uint16_t, uint32_t, <) |
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IWMMXT_OP_CMP(maxs, int8_t, int16_t, int32_t, >) |
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IWMMXT_OP_CMP(maxu, uint8_t, uint16_t, uint32_t, >) |
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#undef CMP
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#define CMP(SHR, TYPE, OPER, MASK) ((uint64_t) (((TYPE) ((M0 >> SHR) & MASK) \
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OPER (TYPE) ((M1 >> SHR) & MASK)) & MASK) << SHR) |
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IWMMXT_OP_CMP(subn, uint8_t, uint16_t, uint32_t, -) |
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IWMMXT_OP_CMP(addn, uint8_t, uint16_t, uint32_t, +) |
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#undef CMP
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/* TODO Signed- and Unsigned-Saturation */
|
| 359 |
#define CMP(SHR, TYPE, OPER, MASK) ((uint64_t) (((TYPE) ((M0 >> SHR) & MASK) \
|
| 360 |
OPER (TYPE) ((M1 >> SHR) & MASK)) & MASK) << SHR) |
| 361 |
IWMMXT_OP_CMP(subu, uint8_t, uint16_t, uint32_t, -) |
| 362 |
IWMMXT_OP_CMP(addu, uint8_t, uint16_t, uint32_t, +) |
| 363 |
IWMMXT_OP_CMP(subs, int8_t, int16_t, int32_t, -) |
| 364 |
IWMMXT_OP_CMP(adds, int8_t, int16_t, int32_t, +) |
| 365 |
#undef CMP
|
| 366 |
#undef IWMMXT_OP_CMP
|
| 367 |
|
| 368 |
void OPPROTO op_iwmmxt_avgb_M0_wRn(void) |
| 369 |
{
|
| 370 |
#define AVGB(SHR) ((( \
|
| 371 |
((M0 >> SHR) & 0xff) + ((M1 >> SHR) & 0xff) + PARAM2) >> 1) << SHR) |
| 372 |
M0 = |
| 373 |
AVGB(0) | AVGB(8) | AVGB(16) | AVGB(24) | |
| 374 |
AVGB(32) | AVGB(40) | AVGB(48) | AVGB(56); |
| 375 |
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
| 376 |
SIMD8_SET(ZBIT8((M0 >> 0) & 0xff), SIMD_ZBIT, 0) | |
| 377 |
SIMD8_SET(ZBIT8((M0 >> 8) & 0xff), SIMD_ZBIT, 1) | |
| 378 |
SIMD8_SET(ZBIT8((M0 >> 16) & 0xff), SIMD_ZBIT, 2) | |
| 379 |
SIMD8_SET(ZBIT8((M0 >> 24) & 0xff), SIMD_ZBIT, 3) | |
| 380 |
SIMD8_SET(ZBIT8((M0 >> 32) & 0xff), SIMD_ZBIT, 4) | |
| 381 |
SIMD8_SET(ZBIT8((M0 >> 40) & 0xff), SIMD_ZBIT, 5) | |
| 382 |
SIMD8_SET(ZBIT8((M0 >> 48) & 0xff), SIMD_ZBIT, 6) | |
| 383 |
SIMD8_SET(ZBIT8((M0 >> 56) & 0xff), SIMD_ZBIT, 7); |
| 384 |
#undef AVGB
|
| 385 |
} |
| 386 |
|
| 387 |
void OPPROTO op_iwmmxt_avgw_M0_wRn(void) |
| 388 |
{
|
| 389 |
#define AVGW(SHR) ((( \
|
| 390 |
((M0 >> SHR) & 0xffff) + ((M1 >> SHR) & 0xffff) + PARAM2) >> 1) << SHR) |
| 391 |
M0 = AVGW(0) | AVGW(16) | AVGW(32) | AVGW(48); |
| 392 |
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
| 393 |
SIMD16_SET(ZBIT16((M0 >> 0) & 0xffff), SIMD_ZBIT, 0) | |
| 394 |
SIMD16_SET(ZBIT16((M0 >> 16) & 0xffff), SIMD_ZBIT, 1) | |
| 395 |
SIMD16_SET(ZBIT16((M0 >> 32) & 0xffff), SIMD_ZBIT, 2) | |
| 396 |
SIMD16_SET(ZBIT16((M0 >> 48) & 0xffff), SIMD_ZBIT, 3); |
| 397 |
#undef AVGW
|
| 398 |
} |
| 399 |
|
| 400 |
void OPPROTO op_iwmmxt_msadb_M0_wRn(void) |
| 401 |
{
|
| 402 |
M0 = ((((M0 >> 0) & 0xffff) * ((M1 >> 0) & 0xffff) + |
| 403 |
((M0 >> 16) & 0xffff) * ((M1 >> 16) & 0xffff)) & 0xffffffff) | |
| 404 |
((((M0 >> 32) & 0xffff) * ((M1 >> 32) & 0xffff) + |
| 405 |
((M0 >> 48) & 0xffff) * ((M1 >> 48) & 0xffff)) << 32); |
| 406 |
} |
| 407 |
|
| 408 |
void OPPROTO op_iwmmxt_align_M0_T0_wRn(void) |
| 409 |
{
|
| 410 |
M0 >>= T0 << 3;
|
| 411 |
M0 |= M1 << (64 - (T0 << 3)); |
| 412 |
} |
| 413 |
|
| 414 |
void OPPROTO op_iwmmxt_insr_M0_T0_T1(void) |
| 415 |
{
|
| 416 |
M0 &= ~((uint64_t) T1 << PARAM1); |
| 417 |
M0 |= (uint64_t) (T0 & T1) << PARAM1; |
| 418 |
} |
| 419 |
|
| 420 |
void OPPROTO op_iwmmxt_extrsb_T0_M0(void) |
| 421 |
{
|
| 422 |
T0 = EXTEND8((M0 >> PARAM1) & 0xff);
|
| 423 |
} |
| 424 |
|
| 425 |
void OPPROTO op_iwmmxt_extrsw_T0_M0(void) |
| 426 |
{
|
| 427 |
T0 = EXTEND16((M0 >> PARAM1) & 0xffff);
|
| 428 |
} |
| 429 |
|
| 430 |
void OPPROTO op_iwmmxt_extru_T0_M0_T1(void) |
| 431 |
{
|
| 432 |
T0 = (M0 >> PARAM1) & T1; |
| 433 |
} |
| 434 |
|
| 435 |
void OPPROTO op_iwmmxt_bcstb_M0_T0(void) |
| 436 |
{
|
| 437 |
T0 &= 0xff;
|
| 438 |
M0 = |
| 439 |
((uint64_t) T0 << 0) | ((uint64_t) T0 << 8) | |
| 440 |
((uint64_t) T0 << 16) | ((uint64_t) T0 << 24) | |
| 441 |
((uint64_t) T0 << 32) | ((uint64_t) T0 << 40) | |
| 442 |
((uint64_t) T0 << 48) | ((uint64_t) T0 << 56); |
| 443 |
} |
| 444 |
|
| 445 |
void OPPROTO op_iwmmxt_bcstw_M0_T0(void) |
| 446 |
{
|
| 447 |
T0 &= 0xffff;
|
| 448 |
M0 = |
| 449 |
((uint64_t) T0 << 0) | ((uint64_t) T0 << 16) | |
| 450 |
((uint64_t) T0 << 32) | ((uint64_t) T0 << 48); |
| 451 |
} |
| 452 |
|
| 453 |
void OPPROTO op_iwmmxt_bcstl_M0_T0(void) |
| 454 |
{
|
| 455 |
M0 = ((uint64_t) T0 << 0) | ((uint64_t) T0 << 32); |
| 456 |
} |
| 457 |
|
| 458 |
void OPPROTO op_iwmmxt_addcb_M0(void) |
| 459 |
{
|
| 460 |
M0 = |
| 461 |
((M0 >> 0) & 0xff) + ((M0 >> 8) & 0xff) + |
| 462 |
((M0 >> 16) & 0xff) + ((M0 >> 24) & 0xff) + |
| 463 |
((M0 >> 32) & 0xff) + ((M0 >> 40) & 0xff) + |
| 464 |
((M0 >> 48) & 0xff) + ((M0 >> 56) & 0xff); |
| 465 |
} |
| 466 |
|
| 467 |
void OPPROTO op_iwmmxt_addcw_M0(void) |
| 468 |
{
|
| 469 |
M0 = |
| 470 |
((M0 >> 0) & 0xffff) + ((M0 >> 16) & 0xffff) + |
| 471 |
((M0 >> 32) & 0xffff) + ((M0 >> 48) & 0xffff); |
| 472 |
} |
| 473 |
|
| 474 |
void OPPROTO op_iwmmxt_addcl_M0(void) |
| 475 |
{
|
| 476 |
M0 = (M0 & 0xffffffff) + (M0 >> 32); |
| 477 |
} |
| 478 |
|
| 479 |
void OPPROTO op_iwmmxt_msbb_T0_M0(void) |
| 480 |
{
|
| 481 |
T0 = |
| 482 |
((M0 >> 7) & 0x01) | ((M0 >> 14) & 0x02) | |
| 483 |
((M0 >> 21) & 0x04) | ((M0 >> 28) & 0x08) | |
| 484 |
((M0 >> 35) & 0x10) | ((M0 >> 42) & 0x20) | |
| 485 |
((M0 >> 49) & 0x40) | ((M0 >> 56) & 0x80); |
| 486 |
} |
| 487 |
|
| 488 |
void OPPROTO op_iwmmxt_msbw_T0_M0(void) |
| 489 |
{
|
| 490 |
T0 = |
| 491 |
((M0 >> 15) & 0x01) | ((M0 >> 30) & 0x02) | |
| 492 |
((M0 >> 45) & 0x04) | ((M0 >> 52) & 0x08); |
| 493 |
} |
| 494 |
|
| 495 |
void OPPROTO op_iwmmxt_msbl_T0_M0(void) |
| 496 |
{
|
| 497 |
T0 = ((M0 >> 31) & 0x01) | ((M0 >> 62) & 0x02); |
| 498 |
} |
| 499 |
|
| 500 |
void OPPROTO op_iwmmxt_srlw_M0_T0(void) |
| 501 |
{
|
| 502 |
M0 = |
| 503 |
(((M0 & (0xffffll << 0)) >> T0) & (0xffffll << 0)) | |
| 504 |
(((M0 & (0xffffll << 16)) >> T0) & (0xffffll << 16)) | |
| 505 |
(((M0 & (0xffffll << 32)) >> T0) & (0xffffll << 32)) | |
| 506 |
(((M0 & (0xffffll << 48)) >> T0) & (0xffffll << 48)); |
| 507 |
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
| 508 |
NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) | |
| 509 |
NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3); |
| 510 |
} |
| 511 |
|
| 512 |
void OPPROTO op_iwmmxt_srll_M0_T0(void) |
| 513 |
{
|
| 514 |
M0 = |
| 515 |
((M0 & (0xffffffffll << 0)) >> T0) | |
| 516 |
((M0 >> T0) & (0xffffffffll << 32)); |
| 517 |
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
| 518 |
NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1); |
| 519 |
} |
| 520 |
|
| 521 |
void OPPROTO op_iwmmxt_srlq_M0_T0(void) |
| 522 |
{
|
| 523 |
M0 >>= T0; |
| 524 |
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0); |
| 525 |
} |
| 526 |
|
| 527 |
void OPPROTO op_iwmmxt_sllw_M0_T0(void) |
| 528 |
{
|
| 529 |
M0 = |
| 530 |
(((M0 & (0xffffll << 0)) << T0) & (0xffffll << 0)) | |
| 531 |
(((M0 & (0xffffll << 16)) << T0) & (0xffffll << 16)) | |
| 532 |
(((M0 & (0xffffll << 32)) << T0) & (0xffffll << 32)) | |
| 533 |
(((M0 & (0xffffll << 48)) << T0) & (0xffffll << 48)); |
| 534 |
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
| 535 |
NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) | |
| 536 |
NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3); |
| 537 |
} |
| 538 |
|
| 539 |
void OPPROTO op_iwmmxt_slll_M0_T0(void) |
| 540 |
{
|
| 541 |
M0 = |
| 542 |
((M0 << T0) & (0xffffffffll << 0)) | |
| 543 |
((M0 & (0xffffffffll << 32)) << T0); |
| 544 |
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
| 545 |
NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1); |
| 546 |
} |
| 547 |
|
| 548 |
void OPPROTO op_iwmmxt_sllq_M0_T0(void) |
| 549 |
{
|
| 550 |
M0 <<= T0; |
| 551 |
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0); |
| 552 |
} |
| 553 |
|
| 554 |
void OPPROTO op_iwmmxt_sraw_M0_T0(void) |
| 555 |
{
|
| 556 |
M0 = |
| 557 |
((uint64_t) ((EXTEND16(M0 >> 0) >> T0) & 0xffff) << 0) | |
| 558 |
((uint64_t) ((EXTEND16(M0 >> 16) >> T0) & 0xffff) << 16) | |
| 559 |
((uint64_t) ((EXTEND16(M0 >> 32) >> T0) & 0xffff) << 32) | |
| 560 |
((uint64_t) ((EXTEND16(M0 >> 48) >> T0) & 0xffff) << 48); |
| 561 |
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
| 562 |
NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) | |
| 563 |
NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3); |
| 564 |
} |
| 565 |
|
| 566 |
void OPPROTO op_iwmmxt_sral_M0_T0(void) |
| 567 |
{
|
| 568 |
M0 = |
| 569 |
(((EXTEND32(M0 >> 0) >> T0) & 0xffffffff) << 0) | |
| 570 |
(((EXTEND32(M0 >> 32) >> T0) & 0xffffffff) << 32); |
| 571 |
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
| 572 |
NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1); |
| 573 |
} |
| 574 |
|
| 575 |
void OPPROTO op_iwmmxt_sraq_M0_T0(void) |
| 576 |
{
|
| 577 |
M0 = (int64_t) M0 >> T0; |
| 578 |
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0); |
| 579 |
} |
| 580 |
|
| 581 |
void OPPROTO op_iwmmxt_rorw_M0_T0(void) |
| 582 |
{
|
| 583 |
M0 = |
| 584 |
((((M0 & (0xffffll << 0)) >> T0) | |
| 585 |
((M0 & (0xffffll << 0)) << (16 - T0))) & (0xffffll << 0)) | |
| 586 |
((((M0 & (0xffffll << 16)) >> T0) | |
| 587 |
((M0 & (0xffffll << 16)) << (16 - T0))) & (0xffffll << 16)) | |
| 588 |
((((M0 & (0xffffll << 32)) >> T0) | |
| 589 |
((M0 & (0xffffll << 32)) << (16 - T0))) & (0xffffll << 32)) | |
| 590 |
((((M0 & (0xffffll << 48)) >> T0) | |
| 591 |
((M0 & (0xffffll << 48)) << (16 - T0))) & (0xffffll << 48)); |
| 592 |
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
| 593 |
NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) | |
| 594 |
NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3); |
| 595 |
} |
| 596 |
|
| 597 |
void OPPROTO op_iwmmxt_rorl_M0_T0(void) |
| 598 |
{
|
| 599 |
M0 = |
| 600 |
((M0 & (0xffffffffll << 0)) >> T0) | |
| 601 |
((M0 >> T0) & (0xffffffffll << 32)) | |
| 602 |
((M0 << (32 - T0)) & (0xffffffffll << 0)) | |
| 603 |
((M0 & (0xffffffffll << 32)) << (32 - T0)); |
| 604 |
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
| 605 |
NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1); |
| 606 |
} |
| 607 |
|
| 608 |
void OPPROTO op_iwmmxt_rorq_M0_T0(void) |
| 609 |
{
|
| 610 |
M0 = (M0 >> T0) | (M0 << (64 - T0));
|
| 611 |
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0); |
| 612 |
} |
| 613 |
|
| 614 |
void OPPROTO op_iwmmxt_shufh_M0_T0(void) |
| 615 |
{
|
| 616 |
M0 = |
| 617 |
(((M0 >> ((T0 << 4) & 0x30)) & 0xffff) << 0) | |
| 618 |
(((M0 >> ((T0 << 2) & 0x30)) & 0xffff) << 16) | |
| 619 |
(((M0 >> ((T0 << 0) & 0x30)) & 0xffff) << 32) | |
| 620 |
(((M0 >> ((T0 >> 2) & 0x30)) & 0xffff) << 48); |
| 621 |
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
| 622 |
NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) | |
| 623 |
NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3); |
| 624 |
} |
| 625 |
|
| 626 |
/* TODO: Unsigned-Saturation */
|
| 627 |
void OPPROTO op_iwmmxt_packuw_M0_wRn(void) |
| 628 |
{
|
| 629 |
M0 = |
| 630 |
(((M0 >> 0) & 0xff) << 0) | (((M0 >> 16) & 0xff) << 8) | |
| 631 |
(((M0 >> 32) & 0xff) << 16) | (((M0 >> 48) & 0xff) << 24) | |
| 632 |
(((M1 >> 0) & 0xff) << 32) | (((M1 >> 16) & 0xff) << 40) | |
| 633 |
(((M1 >> 32) & 0xff) << 48) | (((M1 >> 48) & 0xff) << 56); |
| 634 |
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
| 635 |
NZBIT8(M0 >> 0, 0) | NZBIT8(M0 >> 8, 1) | |
| 636 |
NZBIT8(M0 >> 16, 2) | NZBIT8(M0 >> 24, 3) | |
| 637 |
NZBIT8(M0 >> 32, 4) | NZBIT8(M0 >> 40, 5) | |
| 638 |
NZBIT8(M0 >> 48, 6) | NZBIT8(M0 >> 56, 7); |
| 639 |
} |
| 640 |
|
| 641 |
void OPPROTO op_iwmmxt_packul_M0_wRn(void) |
| 642 |
{
|
| 643 |
M0 = |
| 644 |
(((M0 >> 0) & 0xffff) << 0) | (((M0 >> 32) & 0xffff) << 16) | |
| 645 |
(((M1 >> 0) & 0xffff) << 32) | (((M1 >> 32) & 0xffff) << 48); |
| 646 |
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
| 647 |
NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) | |
| 648 |
NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3); |
| 649 |
} |
| 650 |
|
| 651 |
void OPPROTO op_iwmmxt_packuq_M0_wRn(void) |
| 652 |
{
|
| 653 |
M0 = (M0 & 0xffffffff) | ((M1 & 0xffffffff) << 32); |
| 654 |
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
| 655 |
NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1); |
| 656 |
} |
| 657 |
|
| 658 |
/* TODO: Signed-Saturation */
|
| 659 |
void OPPROTO op_iwmmxt_packsw_M0_wRn(void) |
| 660 |
{
|
| 661 |
M0 = |
| 662 |
(((M0 >> 0) & 0xff) << 0) | (((M0 >> 16) & 0xff) << 8) | |
| 663 |
(((M0 >> 32) & 0xff) << 16) | (((M0 >> 48) & 0xff) << 24) | |
| 664 |
(((M1 >> 0) & 0xff) << 32) | (((M1 >> 16) & 0xff) << 40) | |
| 665 |
(((M1 >> 32) & 0xff) << 48) | (((M1 >> 48) & 0xff) << 56); |
| 666 |
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
| 667 |
NZBIT8(M0 >> 0, 0) | NZBIT8(M0 >> 8, 1) | |
| 668 |
NZBIT8(M0 >> 16, 2) | NZBIT8(M0 >> 24, 3) | |
| 669 |
NZBIT8(M0 >> 32, 4) | NZBIT8(M0 >> 40, 5) | |
| 670 |
NZBIT8(M0 >> 48, 6) | NZBIT8(M0 >> 56, 7); |
| 671 |
} |
| 672 |
|
| 673 |
void OPPROTO op_iwmmxt_packsl_M0_wRn(void) |
| 674 |
{
|
| 675 |
M0 = |
| 676 |
(((M0 >> 0) & 0xffff) << 0) | (((M0 >> 32) & 0xffff) << 16) | |
| 677 |
(((M1 >> 0) & 0xffff) << 32) | (((M1 >> 32) & 0xffff) << 48); |
| 678 |
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
| 679 |
NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) | |
| 680 |
NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3); |
| 681 |
} |
| 682 |
|
| 683 |
void OPPROTO op_iwmmxt_packsq_M0_wRn(void) |
| 684 |
{
|
| 685 |
M0 = (M0 & 0xffffffff) | ((M1 & 0xffffffff) << 32); |
| 686 |
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = |
| 687 |
NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1); |
| 688 |
} |
| 689 |
|
| 690 |
void OPPROTO op_iwmmxt_muladdsl_M0_T0_T1(void) |
| 691 |
{
|
| 692 |
M0 += (int32_t) EXTEND32(T0) * (int32_t) EXTEND32(T1); |
| 693 |
} |
| 694 |
|
| 695 |
void OPPROTO op_iwmmxt_muladdsw_M0_T0_T1(void) |
| 696 |
{
|
| 697 |
M0 += EXTEND32(EXTEND16S((T0 >> 0) & 0xffff) * |
| 698 |
EXTEND16S((T1 >> 0) & 0xffff)); |
| 699 |
M0 += EXTEND32(EXTEND16S((T0 >> 16) & 0xffff) * |
| 700 |
EXTEND16S((T1 >> 16) & 0xffff)); |
| 701 |
} |
| 702 |
|
| 703 |
void OPPROTO op_iwmmxt_muladdswl_M0_T0_T1(void) |
| 704 |
{
|
| 705 |
M0 += EXTEND32(EXTEND16S(T0 & 0xffff) *
|
| 706 |
EXTEND16S(T1 & 0xffff));
|
| 707 |
} |