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1
/*
2
 *  MIPS emulation micro-operations for qemu.
3
 *
4
 *  Copyright (c) 2004-2005 Jocelyn Mayer
5
 *  Copyright (c) 2006 Marius Groeger (FPU operations)
6
 *  Copyright (c) 2007 Thiemo Seufer (64-bit FPU support)
7
 *
8
 * This library is free software; you can redistribute it and/or
9
 * modify it under the terms of the GNU Lesser General Public
10
 * License as published by the Free Software Foundation; either
11
 * version 2 of the License, or (at your option) any later version.
12
 *
13
 * This library is distributed in the hope that it will be useful,
14
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
16
 * Lesser General Public License for more details.
17
 *
18
 * You should have received a copy of the GNU Lesser General Public
19
 * License along with this library; if not, write to the Free Software
20
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
21
 */
22

    
23
#include "config.h"
24
#include "exec.h"
25

    
26
#ifndef CALL_FROM_TB0
27
#define CALL_FROM_TB0(func) func()
28
#endif
29
#ifndef CALL_FROM_TB1
30
#define CALL_FROM_TB1(func, arg0) func(arg0)
31
#endif
32
#ifndef CALL_FROM_TB1_CONST16
33
#define CALL_FROM_TB1_CONST16(func, arg0) CALL_FROM_TB1(func, arg0)
34
#endif
35
#ifndef CALL_FROM_TB2
36
#define CALL_FROM_TB2(func, arg0, arg1) func(arg0, arg1)
37
#endif
38
#ifndef CALL_FROM_TB2_CONST16
39
#define CALL_FROM_TB2_CONST16(func, arg0, arg1)     \
40
        CALL_FROM_TB2(func, arg0, arg1)
41
#endif
42
#ifndef CALL_FROM_TB3
43
#define CALL_FROM_TB3(func, arg0, arg1, arg2) func(arg0, arg1, arg2)
44
#endif
45
#ifndef CALL_FROM_TB4
46
#define CALL_FROM_TB4(func, arg0, arg1, arg2, arg3) \
47
        func(arg0, arg1, arg2, arg3)
48
#endif
49

    
50
#define REG 1
51
#include "op_template.c"
52
#undef REG
53
#define REG 2
54
#include "op_template.c"
55
#undef REG
56
#define REG 3
57
#include "op_template.c"
58
#undef REG
59
#define REG 4
60
#include "op_template.c"
61
#undef REG
62
#define REG 5
63
#include "op_template.c"
64
#undef REG
65
#define REG 6
66
#include "op_template.c"
67
#undef REG
68
#define REG 7
69
#include "op_template.c"
70
#undef REG
71
#define REG 8
72
#include "op_template.c"
73
#undef REG
74
#define REG 9
75
#include "op_template.c"
76
#undef REG
77
#define REG 10
78
#include "op_template.c"
79
#undef REG
80
#define REG 11
81
#include "op_template.c"
82
#undef REG
83
#define REG 12
84
#include "op_template.c"
85
#undef REG
86
#define REG 13
87
#include "op_template.c"
88
#undef REG
89
#define REG 14
90
#include "op_template.c"
91
#undef REG
92
#define REG 15
93
#include "op_template.c"
94
#undef REG
95
#define REG 16
96
#include "op_template.c"
97
#undef REG
98
#define REG 17
99
#include "op_template.c"
100
#undef REG
101
#define REG 18
102
#include "op_template.c"
103
#undef REG
104
#define REG 19
105
#include "op_template.c"
106
#undef REG
107
#define REG 20
108
#include "op_template.c"
109
#undef REG
110
#define REG 21
111
#include "op_template.c"
112
#undef REG
113
#define REG 22
114
#include "op_template.c"
115
#undef REG
116
#define REG 23
117
#include "op_template.c"
118
#undef REG
119
#define REG 24
120
#include "op_template.c"
121
#undef REG
122
#define REG 25
123
#include "op_template.c"
124
#undef REG
125
#define REG 26
126
#include "op_template.c"
127
#undef REG
128
#define REG 27
129
#include "op_template.c"
130
#undef REG
131
#define REG 28
132
#include "op_template.c"
133
#undef REG
134
#define REG 29
135
#include "op_template.c"
136
#undef REG
137
#define REG 30
138
#include "op_template.c"
139
#undef REG
140
#define REG 31
141
#include "op_template.c"
142
#undef REG
143

    
144
#define TN
145
#include "op_template.c"
146
#undef TN
147

    
148
#define FREG 0
149
#include "fop_template.c"
150
#undef FREG
151
#define FREG 1
152
#include "fop_template.c"
153
#undef FREG
154
#define FREG 2
155
#include "fop_template.c"
156
#undef FREG
157
#define FREG 3
158
#include "fop_template.c"
159
#undef FREG
160
#define FREG 4
161
#include "fop_template.c"
162
#undef FREG
163
#define FREG 5
164
#include "fop_template.c"
165
#undef FREG
166
#define FREG 6
167
#include "fop_template.c"
168
#undef FREG
169
#define FREG 7
170
#include "fop_template.c"
171
#undef FREG
172
#define FREG 8
173
#include "fop_template.c"
174
#undef FREG
175
#define FREG 9
176
#include "fop_template.c"
177
#undef FREG
178
#define FREG 10
179
#include "fop_template.c"
180
#undef FREG
181
#define FREG 11
182
#include "fop_template.c"
183
#undef FREG
184
#define FREG 12
185
#include "fop_template.c"
186
#undef FREG
187
#define FREG 13
188
#include "fop_template.c"
189
#undef FREG
190
#define FREG 14
191
#include "fop_template.c"
192
#undef FREG
193
#define FREG 15
194
#include "fop_template.c"
195
#undef FREG
196
#define FREG 16
197
#include "fop_template.c"
198
#undef FREG
199
#define FREG 17
200
#include "fop_template.c"
201
#undef FREG
202
#define FREG 18
203
#include "fop_template.c"
204
#undef FREG
205
#define FREG 19
206
#include "fop_template.c"
207
#undef FREG
208
#define FREG 20
209
#include "fop_template.c"
210
#undef FREG
211
#define FREG 21
212
#include "fop_template.c"
213
#undef FREG
214
#define FREG 22
215
#include "fop_template.c"
216
#undef FREG
217
#define FREG 23
218
#include "fop_template.c"
219
#undef FREG
220
#define FREG 24
221
#include "fop_template.c"
222
#undef FREG
223
#define FREG 25
224
#include "fop_template.c"
225
#undef FREG
226
#define FREG 26
227
#include "fop_template.c"
228
#undef FREG
229
#define FREG 27
230
#include "fop_template.c"
231
#undef FREG
232
#define FREG 28
233
#include "fop_template.c"
234
#undef FREG
235
#define FREG 29
236
#include "fop_template.c"
237
#undef FREG
238
#define FREG 30
239
#include "fop_template.c"
240
#undef FREG
241
#define FREG 31
242
#include "fop_template.c"
243
#undef FREG
244

    
245
#define FTN
246
#include "fop_template.c"
247
#undef FTN
248

    
249
void op_dup_T0 (void)
250
{
251
    T2 = T0;
252
    RETURN();
253
}
254

    
255
void op_load_HI (void)
256
{
257
    T0 = env->HI[PARAM1][env->current_tc];
258
    RETURN();
259
}
260

    
261
void op_store_HI (void)
262
{
263
    env->HI[PARAM1][env->current_tc] = T0;
264
    RETURN();
265
}
266

    
267
void op_load_LO (void)
268
{
269
    T0 = env->LO[PARAM1][env->current_tc];
270
    RETURN();
271
}
272

    
273
void op_store_LO (void)
274
{
275
    env->LO[PARAM1][env->current_tc] = T0;
276
    RETURN();
277
}
278

    
279
/* Load and store */
280
#define MEMSUFFIX _raw
281
#include "op_mem.c"
282
#undef MEMSUFFIX
283
#if !defined(CONFIG_USER_ONLY)
284
#define MEMSUFFIX _user
285
#include "op_mem.c"
286
#undef MEMSUFFIX
287

    
288
#define MEMSUFFIX _kernel
289
#include "op_mem.c"
290
#undef MEMSUFFIX
291
#endif
292

    
293
/* Addresses computation */
294
void op_addr_add (void)
295
{
296
/* For compatibility with 32-bit code, data reference in user mode
297
   with Status_UX = 0 should be casted to 32-bit and sign extended.
298
   See the MIPS64 PRA manual, section 4.10. */
299
#ifdef TARGET_MIPS64
300
    if ((env->hflags & MIPS_HFLAG_UM) &&
301
        !(env->CP0_Status & (1 << CP0St_UX)))
302
        T0 = (int64_t)(int32_t)(T0 + T1);
303
    else
304
#endif
305
        T0 += T1;
306
    RETURN();
307
}
308

    
309
/* Arithmetic */
310
void op_add (void)
311
{
312
    T0 = (int32_t)((int32_t)T0 + (int32_t)T1);
313
    RETURN();
314
}
315

    
316
void op_addo (void)
317
{
318
    target_ulong tmp;
319

    
320
    tmp = (int32_t)T0;
321
    T0 = (int32_t)T0 + (int32_t)T1;
322
    if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 31) {
323
        /* operands of same sign, result different sign */
324
        CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
325
    }
326
    T0 = (int32_t)T0;
327
    RETURN();
328
}
329

    
330
void op_sub (void)
331
{
332
    T0 = (int32_t)((int32_t)T0 - (int32_t)T1);
333
    RETURN();
334
}
335

    
336
void op_subo (void)
337
{
338
    target_ulong tmp;
339

    
340
    tmp = (int32_t)T0;
341
    T0 = (int32_t)T0 - (int32_t)T1;
342
    if (((tmp ^ T1) & (tmp ^ T0)) >> 31) {
343
        /* operands of different sign, first operand and result different sign */
344
        CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
345
    }
346
    T0 = (int32_t)T0;
347
    RETURN();
348
}
349

    
350
void op_mul (void)
351
{
352
    T0 = (int32_t)((int32_t)T0 * (int32_t)T1);
353
    RETURN();
354
}
355

    
356
#if HOST_LONG_BITS < 64
357
void op_div (void)
358
{
359
    CALL_FROM_TB0(do_div);
360
    RETURN();
361
}
362
#else
363
void op_div (void)
364
{
365
    if (T1 != 0) {
366
        env->LO[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1);
367
        env->HI[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1);
368
    }
369
    RETURN();
370
}
371
#endif
372

    
373
void op_divu (void)
374
{
375
    if (T1 != 0) {
376
        env->LO[0][env->current_tc] = (int32_t)((uint32_t)T0 / (uint32_t)T1);
377
        env->HI[0][env->current_tc] = (int32_t)((uint32_t)T0 % (uint32_t)T1);
378
    }
379
    RETURN();
380
}
381

    
382
#ifdef TARGET_MIPS64
383
/* Arithmetic */
384
void op_dadd (void)
385
{
386
    T0 += T1;
387
    RETURN();
388
}
389

    
390
void op_daddo (void)
391
{
392
    target_long tmp;
393

    
394
    tmp = T0;
395
    T0 += T1;
396
    if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 63) {
397
        /* operands of same sign, result different sign */
398
        CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
399
    }
400
    RETURN();
401
}
402

    
403
void op_dsub (void)
404
{
405
    T0 -= T1;
406
    RETURN();
407
}
408

    
409
void op_dsubo (void)
410
{
411
    target_long tmp;
412

    
413
    tmp = T0;
414
    T0 = (int64_t)T0 - (int64_t)T1;
415
    if (((tmp ^ T1) & (tmp ^ T0)) >> 63) {
416
        /* operands of different sign, first operand and result different sign */
417
        CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
418
    }
419
    RETURN();
420
}
421

    
422
void op_dmul (void)
423
{
424
    T0 = (int64_t)T0 * (int64_t)T1;
425
    RETURN();
426
}
427

    
428
/* Those might call libgcc functions.  */
429
void op_ddiv (void)
430
{
431
    do_ddiv();
432
    RETURN();
433
}
434

    
435
#if TARGET_LONG_BITS > HOST_LONG_BITS
436
void op_ddivu (void)
437
{
438
    do_ddivu();
439
    RETURN();
440
}
441
#else
442
void op_ddivu (void)
443
{
444
    if (T1 != 0) {
445
        env->LO[0][env->current_tc] = T0 / T1;
446
        env->HI[0][env->current_tc] = T0 % T1;
447
    }
448
    RETURN();
449
}
450
#endif
451
#endif /* TARGET_MIPS64 */
452

    
453
/* Logical */
454
void op_and (void)
455
{
456
    T0 &= T1;
457
    RETURN();
458
}
459

    
460
void op_nor (void)
461
{
462
    T0 = ~(T0 | T1);
463
    RETURN();
464
}
465

    
466
void op_or (void)
467
{
468
    T0 |= T1;
469
    RETURN();
470
}
471

    
472
void op_xor (void)
473
{
474
    T0 ^= T1;
475
    RETURN();
476
}
477

    
478
void op_sll (void)
479
{
480
    T0 = (int32_t)((uint32_t)T0 << T1);
481
    RETURN();
482
}
483

    
484
void op_sra (void)
485
{
486
    T0 = (int32_t)((int32_t)T0 >> T1);
487
    RETURN();
488
}
489

    
490
void op_srl (void)
491
{
492
    T0 = (int32_t)((uint32_t)T0 >> T1);
493
    RETURN();
494
}
495

    
496
void op_rotr (void)
497
{
498
    target_ulong tmp;
499

    
500
    if (T1) {
501
       tmp = (int32_t)((uint32_t)T0 << (0x20 - T1));
502
       T0 = (int32_t)((uint32_t)T0 >> T1) | tmp;
503
    }
504
    RETURN();
505
}
506

    
507
void op_sllv (void)
508
{
509
    T0 = (int32_t)((uint32_t)T1 << ((uint32_t)T0 & 0x1F));
510
    RETURN();
511
}
512

    
513
void op_srav (void)
514
{
515
    T0 = (int32_t)((int32_t)T1 >> (T0 & 0x1F));
516
    RETURN();
517
}
518

    
519
void op_srlv (void)
520
{
521
    T0 = (int32_t)((uint32_t)T1 >> (T0 & 0x1F));
522
    RETURN();
523
}
524

    
525
void op_rotrv (void)
526
{
527
    target_ulong tmp;
528

    
529
    T0 &= 0x1F;
530
    if (T0) {
531
       tmp = (int32_t)((uint32_t)T1 << (0x20 - T0));
532
       T0 = (int32_t)((uint32_t)T1 >> T0) | tmp;
533
    } else
534
       T0 = T1;
535
    RETURN();
536
}
537

    
538
void op_clo (void)
539
{
540
    int n;
541

    
542
    if (T0 == ~((target_ulong)0)) {
543
        T0 = 32;
544
    } else {
545
        for (n = 0; n < 32; n++) {
546
            if (!(T0 & (1 << 31)))
547
                break;
548
            T0 = T0 << 1;
549
        }
550
        T0 = n;
551
    }
552
    RETURN();
553
}
554

    
555
void op_clz (void)
556
{
557
    int n;
558

    
559
    if (T0 == 0) {
560
        T0 = 32;
561
    } else {
562
        for (n = 0; n < 32; n++) {
563
            if (T0 & (1 << 31))
564
                break;
565
            T0 = T0 << 1;
566
        }
567
        T0 = n;
568
    }
569
    RETURN();
570
}
571

    
572
#ifdef TARGET_MIPS64
573

    
574
#if TARGET_LONG_BITS > HOST_LONG_BITS
575
/* Those might call libgcc functions.  */
576
void op_dsll (void)
577
{
578
    CALL_FROM_TB0(do_dsll);
579
    RETURN();
580
}
581

    
582
void op_dsll32 (void)
583
{
584
    CALL_FROM_TB0(do_dsll32);
585
    RETURN();
586
}
587

    
588
void op_dsra (void)
589
{
590
    CALL_FROM_TB0(do_dsra);
591
    RETURN();
592
}
593

    
594
void op_dsra32 (void)
595
{
596
    CALL_FROM_TB0(do_dsra32);
597
    RETURN();
598
}
599

    
600
void op_dsrl (void)
601
{
602
    CALL_FROM_TB0(do_dsrl);
603
    RETURN();
604
}
605

    
606
void op_dsrl32 (void)
607
{
608
    CALL_FROM_TB0(do_dsrl32);
609
    RETURN();
610
}
611

    
612
void op_drotr (void)
613
{
614
    CALL_FROM_TB0(do_drotr);
615
    RETURN();
616
}
617

    
618
void op_drotr32 (void)
619
{
620
    CALL_FROM_TB0(do_drotr32);
621
    RETURN();
622
}
623

    
624
void op_dsllv (void)
625
{
626
    CALL_FROM_TB0(do_dsllv);
627
    RETURN();
628
}
629

    
630
void op_dsrav (void)
631
{
632
    CALL_FROM_TB0(do_dsrav);
633
    RETURN();
634
}
635

    
636
void op_dsrlv (void)
637
{
638
    CALL_FROM_TB0(do_dsrlv);
639
    RETURN();
640
}
641

    
642
void op_drotrv (void)
643
{
644
    CALL_FROM_TB0(do_drotrv);
645
    RETURN();
646
}
647

    
648
#else /* TARGET_LONG_BITS > HOST_LONG_BITS */
649

    
650
void op_dsll (void)
651
{
652
    T0 = T0 << T1;
653
    RETURN();
654
}
655

    
656
void op_dsll32 (void)
657
{
658
    T0 = T0 << (T1 + 32);
659
    RETURN();
660
}
661

    
662
void op_dsra (void)
663
{
664
    T0 = (int64_t)T0 >> T1;
665
    RETURN();
666
}
667

    
668
void op_dsra32 (void)
669
{
670
    T0 = (int64_t)T0 >> (T1 + 32);
671
    RETURN();
672
}
673

    
674
void op_dsrl (void)
675
{
676
    T0 = T0 >> T1;
677
    RETURN();
678
}
679

    
680
void op_dsrl32 (void)
681
{
682
    T0 = T0 >> (T1 + 32);
683
    RETURN();
684
}
685

    
686
void op_drotr (void)
687
{
688
    target_ulong tmp;
689

    
690
    if (T1) {
691
       tmp = T0 << (0x40 - T1);
692
       T0 = (T0 >> T1) | tmp;
693
    }
694
    RETURN();
695
}
696

    
697
void op_drotr32 (void)
698
{
699
    target_ulong tmp;
700

    
701
    if (T1) {
702
       tmp = T0 << (0x40 - (32 + T1));
703
       T0 = (T0 >> (32 + T1)) | tmp;
704
    }
705
    RETURN();
706
}
707

    
708
void op_dsllv (void)
709
{
710
    T0 = T1 << (T0 & 0x3F);
711
    RETURN();
712
}
713

    
714
void op_dsrav (void)
715
{
716
    T0 = (int64_t)T1 >> (T0 & 0x3F);
717
    RETURN();
718
}
719

    
720
void op_dsrlv (void)
721
{
722
    T0 = T1 >> (T0 & 0x3F);
723
    RETURN();
724
}
725

    
726
void op_drotrv (void)
727
{
728
    target_ulong tmp;
729

    
730
    T0 &= 0x3F;
731
    if (T0) {
732
       tmp = T1 << (0x40 - T0);
733
       T0 = (T1 >> T0) | tmp;
734
    } else
735
       T0 = T1;
736
    RETURN();
737
}
738
#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
739

    
740
void op_dclo (void)
741
{
742
    int n;
743

    
744
    if (T0 == ~((target_ulong)0)) {
745
        T0 = 64;
746
    } else {
747
        for (n = 0; n < 64; n++) {
748
            if (!(T0 & (1ULL << 63)))
749
                break;
750
            T0 = T0 << 1;
751
        }
752
        T0 = n;
753
    }
754
    RETURN();
755
}
756

    
757
void op_dclz (void)
758
{
759
    int n;
760

    
761
    if (T0 == 0) {
762
        T0 = 64;
763
    } else {
764
        for (n = 0; n < 64; n++) {
765
            if (T0 & (1ULL << 63))
766
                break;
767
            T0 = T0 << 1;
768
        }
769
        T0 = n;
770
    }
771
    RETURN();
772
}
773
#endif
774

    
775
/* 64 bits arithmetic */
776
#if TARGET_LONG_BITS > HOST_LONG_BITS
777
void op_mult (void)
778
{
779
    CALL_FROM_TB0(do_mult);
780
    RETURN();
781
}
782

    
783
void op_multu (void)
784
{
785
    CALL_FROM_TB0(do_multu);
786
    RETURN();
787
}
788

    
789
void op_madd (void)
790
{
791
    CALL_FROM_TB0(do_madd);
792
    RETURN();
793
}
794

    
795
void op_maddu (void)
796
{
797
    CALL_FROM_TB0(do_maddu);
798
    RETURN();
799
}
800

    
801
void op_msub (void)
802
{
803
    CALL_FROM_TB0(do_msub);
804
    RETURN();
805
}
806

    
807
void op_msubu (void)
808
{
809
    CALL_FROM_TB0(do_msubu);
810
    RETURN();
811
}
812

    
813
#else /* TARGET_LONG_BITS > HOST_LONG_BITS */
814

    
815
static inline uint64_t get_HILO (void)
816
{
817
    return ((uint64_t)env->HI[0][env->current_tc] << 32) |
818
            ((uint64_t)(uint32_t)env->LO[0][env->current_tc]);
819
}
820

    
821
static inline void set_HILO (uint64_t HILO)
822
{
823
    env->LO[0][env->current_tc] = (int32_t)(HILO & 0xFFFFFFFF);
824
    env->HI[0][env->current_tc] = (int32_t)(HILO >> 32);
825
}
826

    
827
void op_mult (void)
828
{
829
    set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
830
    RETURN();
831
}
832

    
833
void op_multu (void)
834
{
835
    set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
836
    RETURN();
837
}
838

    
839
void op_madd (void)
840
{
841
    int64_t tmp;
842

    
843
    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
844
    set_HILO((int64_t)get_HILO() + tmp);
845
    RETURN();
846
}
847

    
848
void op_maddu (void)
849
{
850
    uint64_t tmp;
851

    
852
    tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
853
    set_HILO(get_HILO() + tmp);
854
    RETURN();
855
}
856

    
857
void op_msub (void)
858
{
859
    int64_t tmp;
860

    
861
    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
862
    set_HILO((int64_t)get_HILO() - tmp);
863
    RETURN();
864
}
865

    
866
void op_msubu (void)
867
{
868
    uint64_t tmp;
869

    
870
    tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
871
    set_HILO(get_HILO() - tmp);
872
    RETURN();
873
}
874
#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
875

    
876
#ifdef TARGET_MIPS64
877
void op_dmult (void)
878
{
879
    CALL_FROM_TB4(muls64, &(env->HI[0][env->current_tc]), &(env->LO[0][env->current_tc]), T0, T1);
880
    RETURN();
881
}
882

    
883
void op_dmultu (void)
884
{
885
    CALL_FROM_TB4(mulu64, &(env->HI[0][env->current_tc]), &(env->LO[0][env->current_tc]), T0, T1);
886
    RETURN();
887
}
888
#endif
889

    
890
/* Conditional moves */
891
void op_movn (void)
892
{
893
    if (T1 != 0)
894
        env->gpr[PARAM1][env->current_tc] = T0;
895
    RETURN();
896
}
897

    
898
void op_movz (void)
899
{
900
    if (T1 == 0)
901
        env->gpr[PARAM1][env->current_tc] = T0;
902
    RETURN();
903
}
904

    
905
void op_movf (void)
906
{
907
    if (!(env->fpu->fcr31 & PARAM1))
908
        T0 = T1;
909
    RETURN();
910
}
911

    
912
void op_movt (void)
913
{
914
    if (env->fpu->fcr31 & PARAM1)
915
        T0 = T1;
916
    RETURN();
917
}
918

    
919
/* Tests */
920
#define OP_COND(name, cond) \
921
void glue(op_, name) (void) \
922
{                           \
923
    if (cond) {             \
924
        T0 = 1;             \
925
    } else {                \
926
        T0 = 0;             \
927
    }                       \
928
    RETURN();               \
929
}
930

    
931
OP_COND(eq, T0 == T1);
932
OP_COND(ne, T0 != T1);
933
OP_COND(ge, (target_long)T0 >= (target_long)T1);
934
OP_COND(geu, T0 >= T1);
935
OP_COND(lt, (target_long)T0 < (target_long)T1);
936
OP_COND(ltu, T0 < T1);
937
OP_COND(gez, (target_long)T0 >= 0);
938
OP_COND(gtz, (target_long)T0 > 0);
939
OP_COND(lez, (target_long)T0 <= 0);
940
OP_COND(ltz, (target_long)T0 < 0);
941

    
942
/* Branches */
943
void OPPROTO op_goto_tb0(void)
944
{
945
    GOTO_TB(op_goto_tb0, PARAM1, 0);
946
    RETURN();
947
}
948

    
949
void OPPROTO op_goto_tb1(void)
950
{
951
    GOTO_TB(op_goto_tb1, PARAM1, 1);
952
    RETURN();
953
}
954

    
955
/* Branch to register */
956
void op_save_breg_target (void)
957
{
958
    env->btarget = T2;
959
    RETURN();
960
}
961

    
962
void op_restore_breg_target (void)
963
{
964
    T2 = env->btarget;
965
    RETURN();
966
}
967

    
968
void op_breg (void)
969
{
970
    env->PC[env->current_tc] = T2;
971
    RETURN();
972
}
973

    
974
void op_save_btarget (void)
975
{
976
    env->btarget = PARAM1;
977
    RETURN();
978
}
979

    
980
#ifdef TARGET_MIPS64
981
void op_save_btarget64 (void)
982
{
983
    env->btarget = ((uint64_t)PARAM1 << 32) | (uint32_t)PARAM2;
984
    RETURN();
985
}
986
#endif
987

    
988
/* Conditional branch */
989
void op_set_bcond (void)
990
{
991
    T2 = T0;
992
    RETURN();
993
}
994

    
995
void op_save_bcond (void)
996
{
997
    env->bcond = T2;
998
    RETURN();
999
}
1000

    
1001
void op_restore_bcond (void)
1002
{
1003
    T2 = env->bcond;
1004
    RETURN();
1005
}
1006

    
1007
void op_jnz_T2 (void)
1008
{
1009
    if (T2)
1010
        GOTO_LABEL_PARAM(1);
1011
    RETURN();
1012
}
1013

    
1014
/* CP0 functions */
1015
void op_mfc0_index (void)
1016
{
1017
    T0 = env->CP0_Index;
1018
    RETURN();
1019
}
1020

    
1021
void op_mfc0_mvpcontrol (void)
1022
{
1023
    T0 = env->mvp->CP0_MVPControl;
1024
    RETURN();
1025
}
1026

    
1027
void op_mfc0_mvpconf0 (void)
1028
{
1029
    T0 = env->mvp->CP0_MVPConf0;
1030
    RETURN();
1031
}
1032

    
1033
void op_mfc0_mvpconf1 (void)
1034
{
1035
    T0 = env->mvp->CP0_MVPConf1;
1036
    RETURN();
1037
}
1038

    
1039
void op_mfc0_random (void)
1040
{
1041
    CALL_FROM_TB0(do_mfc0_random);
1042
    RETURN();
1043
}
1044

    
1045
void op_mfc0_vpecontrol (void)
1046
{
1047
    T0 = env->CP0_VPEControl;
1048
    RETURN();
1049
}
1050

    
1051
void op_mfc0_vpeconf0 (void)
1052
{
1053
    T0 = env->CP0_VPEConf0;
1054
    RETURN();
1055
}
1056

    
1057
void op_mfc0_vpeconf1 (void)
1058
{
1059
    T0 = env->CP0_VPEConf1;
1060
    RETURN();
1061
}
1062

    
1063
void op_mfc0_yqmask (void)
1064
{
1065
    T0 = env->CP0_YQMask;
1066
    RETURN();
1067
}
1068

    
1069
void op_mfc0_vpeschedule (void)
1070
{
1071
    T0 = env->CP0_VPESchedule;
1072
    RETURN();
1073
}
1074

    
1075
void op_mfc0_vpeschefback (void)
1076
{
1077
    T0 = env->CP0_VPEScheFBack;
1078
    RETURN();
1079
}
1080

    
1081
void op_mfc0_vpeopt (void)
1082
{
1083
    T0 = env->CP0_VPEOpt;
1084
    RETURN();
1085
}
1086

    
1087
void op_mfc0_entrylo0 (void)
1088
{
1089
    T0 = (int32_t)env->CP0_EntryLo0;
1090
    RETURN();
1091
}
1092

    
1093
void op_mfc0_tcstatus (void)
1094
{
1095
    T0 = env->CP0_TCStatus[env->current_tc];
1096
    RETURN();
1097
}
1098

    
1099
void op_mftc0_tcstatus(void)
1100
{
1101
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1102

    
1103
    T0 = env->CP0_TCStatus[other_tc];
1104
    RETURN();
1105
}
1106

    
1107
void op_mfc0_tcbind (void)
1108
{
1109
    T0 = env->CP0_TCBind[env->current_tc];
1110
    RETURN();
1111
}
1112

    
1113
void op_mftc0_tcbind(void)
1114
{
1115
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1116

    
1117
    T0 = env->CP0_TCBind[other_tc];
1118
    RETURN();
1119
}
1120

    
1121
void op_mfc0_tcrestart (void)
1122
{
1123
    T0 = env->PC[env->current_tc];
1124
    RETURN();
1125
}
1126

    
1127
void op_mftc0_tcrestart(void)
1128
{
1129
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1130

    
1131
    T0 = env->PC[other_tc];
1132
    RETURN();
1133
}
1134

    
1135
void op_mfc0_tchalt (void)
1136
{
1137
    T0 = env->CP0_TCHalt[env->current_tc];
1138
    RETURN();
1139
}
1140

    
1141
void op_mftc0_tchalt(void)
1142
{
1143
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1144

    
1145
    T0 = env->CP0_TCHalt[other_tc];
1146
    RETURN();
1147
}
1148

    
1149
void op_mfc0_tccontext (void)
1150
{
1151
    T0 = env->CP0_TCContext[env->current_tc];
1152
    RETURN();
1153
}
1154

    
1155
void op_mftc0_tccontext(void)
1156
{
1157
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1158

    
1159
    T0 = env->CP0_TCContext[other_tc];
1160
    RETURN();
1161
}
1162

    
1163
void op_mfc0_tcschedule (void)
1164
{
1165
    T0 = env->CP0_TCSchedule[env->current_tc];
1166
    RETURN();
1167
}
1168

    
1169
void op_mftc0_tcschedule(void)
1170
{
1171
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1172

    
1173
    T0 = env->CP0_TCSchedule[other_tc];
1174
    RETURN();
1175
}
1176

    
1177
void op_mfc0_tcschefback (void)
1178
{
1179
    T0 = env->CP0_TCScheFBack[env->current_tc];
1180
    RETURN();
1181
}
1182

    
1183
void op_mftc0_tcschefback(void)
1184
{
1185
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1186

    
1187
    T0 = env->CP0_TCScheFBack[other_tc];
1188
    RETURN();
1189
}
1190

    
1191
void op_mfc0_entrylo1 (void)
1192
{
1193
    T0 = (int32_t)env->CP0_EntryLo1;
1194
    RETURN();
1195
}
1196

    
1197
void op_mfc0_context (void)
1198
{
1199
    T0 = (int32_t)env->CP0_Context;
1200
    RETURN();
1201
}
1202

    
1203
void op_mfc0_pagemask (void)
1204
{
1205
    T0 = env->CP0_PageMask;
1206
    RETURN();
1207
}
1208

    
1209
void op_mfc0_pagegrain (void)
1210
{
1211
    T0 = env->CP0_PageGrain;
1212
    RETURN();
1213
}
1214

    
1215
void op_mfc0_wired (void)
1216
{
1217
    T0 = env->CP0_Wired;
1218
    RETURN();
1219
}
1220

    
1221
void op_mfc0_srsconf0 (void)
1222
{
1223
    T0 = env->CP0_SRSConf0;
1224
    RETURN();
1225
}
1226

    
1227
void op_mfc0_srsconf1 (void)
1228
{
1229
    T0 = env->CP0_SRSConf1;
1230
    RETURN();
1231
}
1232

    
1233
void op_mfc0_srsconf2 (void)
1234
{
1235
    T0 = env->CP0_SRSConf2;
1236
    RETURN();
1237
}
1238

    
1239
void op_mfc0_srsconf3 (void)
1240
{
1241
    T0 = env->CP0_SRSConf3;
1242
    RETURN();
1243
}
1244

    
1245
void op_mfc0_srsconf4 (void)
1246
{
1247
    T0 = env->CP0_SRSConf4;
1248
    RETURN();
1249
}
1250

    
1251
void op_mfc0_hwrena (void)
1252
{
1253
    T0 = env->CP0_HWREna;
1254
    RETURN();
1255
}
1256

    
1257
void op_mfc0_badvaddr (void)
1258
{
1259
    T0 = (int32_t)env->CP0_BadVAddr;
1260
    RETURN();
1261
}
1262

    
1263
void op_mfc0_count (void)
1264
{
1265
    CALL_FROM_TB0(do_mfc0_count);
1266
    RETURN();
1267
}
1268

    
1269
void op_mfc0_entryhi (void)
1270
{
1271
    T0 = (int32_t)env->CP0_EntryHi;
1272
    RETURN();
1273
}
1274

    
1275
void op_mftc0_entryhi(void)
1276
{
1277
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1278

    
1279
    T0 = (env->CP0_EntryHi & ~0xff) | (env->CP0_TCStatus[other_tc] & 0xff);
1280
    RETURN();
1281
}
1282

    
1283
void op_mfc0_compare (void)
1284
{
1285
    T0 = env->CP0_Compare;
1286
    RETURN();
1287
}
1288

    
1289
void op_mfc0_status (void)
1290
{
1291
    T0 = env->CP0_Status;
1292
    RETURN();
1293
}
1294

    
1295
void op_mftc0_status(void)
1296
{
1297
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1298
    uint32_t tcstatus = env->CP0_TCStatus[other_tc];
1299

    
1300
    T0 = env->CP0_Status & ~0xf1000018;
1301
    T0 |= tcstatus & (0xf << CP0TCSt_TCU0);
1302
    T0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);
1303
    T0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_R0);
1304
    RETURN();
1305
}
1306

    
1307
void op_mfc0_intctl (void)
1308
{
1309
    T0 = env->CP0_IntCtl;
1310
    RETURN();
1311
}
1312

    
1313
void op_mfc0_srsctl (void)
1314
{
1315
    T0 = env->CP0_SRSCtl;
1316
    RETURN();
1317
}
1318

    
1319
void op_mfc0_srsmap (void)
1320
{
1321
    T0 = env->CP0_SRSMap;
1322
    RETURN();
1323
}
1324

    
1325
void op_mfc0_cause (void)
1326
{
1327
    T0 = env->CP0_Cause;
1328
    RETURN();
1329
}
1330

    
1331
void op_mfc0_epc (void)
1332
{
1333
    T0 = (int32_t)env->CP0_EPC;
1334
    RETURN();
1335
}
1336

    
1337
void op_mfc0_prid (void)
1338
{
1339
    T0 = env->CP0_PRid;
1340
    RETURN();
1341
}
1342

    
1343
void op_mfc0_ebase (void)
1344
{
1345
    T0 = env->CP0_EBase;
1346
    RETURN();
1347
}
1348

    
1349
void op_mfc0_config0 (void)
1350
{
1351
    T0 = env->CP0_Config0;
1352
    RETURN();
1353
}
1354

    
1355
void op_mfc0_config1 (void)
1356
{
1357
    T0 = env->CP0_Config1;
1358
    RETURN();
1359
}
1360

    
1361
void op_mfc0_config2 (void)
1362
{
1363
    T0 = env->CP0_Config2;
1364
    RETURN();
1365
}
1366

    
1367
void op_mfc0_config3 (void)
1368
{
1369
    T0 = env->CP0_Config3;
1370
    RETURN();
1371
}
1372

    
1373
void op_mfc0_config6 (void)
1374
{
1375
    T0 = env->CP0_Config6;
1376
    RETURN();
1377
}
1378

    
1379
void op_mfc0_config7 (void)
1380
{
1381
    T0 = env->CP0_Config7;
1382
    RETURN();
1383
}
1384

    
1385
void op_mfc0_lladdr (void)
1386
{
1387
    T0 = (int32_t)env->CP0_LLAddr >> 4;
1388
    RETURN();
1389
}
1390

    
1391
void op_mfc0_watchlo (void)
1392
{
1393
    T0 = (int32_t)env->CP0_WatchLo[PARAM1];
1394
    RETURN();
1395
}
1396

    
1397
void op_mfc0_watchhi (void)
1398
{
1399
    T0 = env->CP0_WatchHi[PARAM1];
1400
    RETURN();
1401
}
1402

    
1403
void op_mfc0_xcontext (void)
1404
{
1405
    T0 = (int32_t)env->CP0_XContext;
1406
    RETURN();
1407
}
1408

    
1409
void op_mfc0_framemask (void)
1410
{
1411
    T0 = env->CP0_Framemask;
1412
    RETURN();
1413
}
1414

    
1415
void op_mfc0_debug (void)
1416
{
1417
    T0 = env->CP0_Debug;
1418
    if (env->hflags & MIPS_HFLAG_DM)
1419
        T0 |= 1 << CP0DB_DM;
1420
    RETURN();
1421
}
1422

    
1423
void op_mftc0_debug(void)
1424
{
1425
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1426

    
1427
    /* XXX: Might be wrong, check with EJTAG spec. */
1428
    T0 = (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1429
         (env->CP0_Debug_tcstatus[other_tc] &
1430
          ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1431
    RETURN();
1432
}
1433

    
1434
void op_mfc0_depc (void)
1435
{
1436
    T0 = (int32_t)env->CP0_DEPC;
1437
    RETURN();
1438
}
1439

    
1440
void op_mfc0_performance0 (void)
1441
{
1442
    T0 = env->CP0_Performance0;
1443
    RETURN();
1444
}
1445

    
1446
void op_mfc0_taglo (void)
1447
{
1448
    T0 = env->CP0_TagLo;
1449
    RETURN();
1450
}
1451

    
1452
void op_mfc0_datalo (void)
1453
{
1454
    T0 = env->CP0_DataLo;
1455
    RETURN();
1456
}
1457

    
1458
void op_mfc0_taghi (void)
1459
{
1460
    T0 = env->CP0_TagHi;
1461
    RETURN();
1462
}
1463

    
1464
void op_mfc0_datahi (void)
1465
{
1466
    T0 = env->CP0_DataHi;
1467
    RETURN();
1468
}
1469

    
1470
void op_mfc0_errorepc (void)
1471
{
1472
    T0 = (int32_t)env->CP0_ErrorEPC;
1473
    RETURN();
1474
}
1475

    
1476
void op_mfc0_desave (void)
1477
{
1478
    T0 = env->CP0_DESAVE;
1479
    RETURN();
1480
}
1481

    
1482
void op_mtc0_index (void)
1483
{
1484
    env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 % env->tlb->nb_tlb);
1485
    RETURN();
1486
}
1487

    
1488
void op_mtc0_mvpcontrol (void)
1489
{
1490
    uint32_t mask = 0;
1491
    uint32_t newval;
1492

    
1493
    if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
1494
        mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
1495
                (1 << CP0MVPCo_EVP);
1496
    if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1497
        mask |= (1 << CP0MVPCo_STLB);
1498
    newval = (env->mvp->CP0_MVPControl & ~mask) | (T0 & mask);
1499

    
1500
    // TODO: Enable/disable shared TLB, enable/disable VPEs.
1501

    
1502
    env->mvp->CP0_MVPControl = newval;
1503
    RETURN();
1504
}
1505

    
1506
void op_mtc0_vpecontrol (void)
1507
{
1508
    uint32_t mask;
1509
    uint32_t newval;
1510

    
1511
    mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1512
           (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1513
    newval = (env->CP0_VPEControl & ~mask) | (T0 & mask);
1514

    
1515
    /* Yield scheduler intercept not implemented. */
1516
    /* Gating storage scheduler intercept not implemented. */
1517

    
1518
    // TODO: Enable/disable TCs.
1519

    
1520
    env->CP0_VPEControl = newval;
1521
    RETURN();
1522
}
1523

    
1524
void op_mtc0_vpeconf0 (void)
1525
{
1526
    uint32_t mask = 0;
1527
    uint32_t newval;
1528

    
1529
    if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1530
        if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1531
            mask |= (0xff << CP0VPEC0_XTC);
1532
        mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1533
    }
1534
    newval = (env->CP0_VPEConf0 & ~mask) | (T0 & mask);
1535

    
1536
    // TODO: TC exclusive handling due to ERL/EXL.
1537

    
1538
    env->CP0_VPEConf0 = newval;
1539
    RETURN();
1540
}
1541

    
1542
void op_mtc0_vpeconf1 (void)
1543
{
1544
    uint32_t mask = 0;
1545
    uint32_t newval;
1546

    
1547
    if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1548
        mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1549
                (0xff << CP0VPEC1_NCP1);
1550
    newval = (env->CP0_VPEConf1 & ~mask) | (T0 & mask);
1551

    
1552
    /* UDI not implemented. */
1553
    /* CP2 not implemented. */
1554

    
1555
    // TODO: Handle FPU (CP1) binding.
1556

    
1557
    env->CP0_VPEConf1 = newval;
1558
    RETURN();
1559
}
1560

    
1561
void op_mtc0_yqmask (void)
1562
{
1563
    /* Yield qualifier inputs not implemented. */
1564
    env->CP0_YQMask = 0x00000000;
1565
    RETURN();
1566
}
1567

    
1568
void op_mtc0_vpeschedule (void)
1569
{
1570
    env->CP0_VPESchedule = T0;
1571
    RETURN();
1572
}
1573

    
1574
void op_mtc0_vpeschefback (void)
1575
{
1576
    env->CP0_VPEScheFBack = T0;
1577
    RETURN();
1578
}
1579

    
1580
void op_mtc0_vpeopt (void)
1581
{
1582
    env->CP0_VPEOpt = T0 & 0x0000ffff;
1583
    RETURN();
1584
}
1585

    
1586
void op_mtc0_entrylo0 (void)
1587
{
1588
    /* Large physaddr not implemented */
1589
    /* 1k pages not implemented */
1590
    env->CP0_EntryLo0 = T0 & 0x3FFFFFFF;
1591
    RETURN();
1592
}
1593

    
1594
void op_mtc0_tcstatus (void)
1595
{
1596
    uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1597
    uint32_t newval;
1598

    
1599
    newval = (env->CP0_TCStatus[env->current_tc] & ~mask) | (T0 & mask);
1600

    
1601
    // TODO: Sync with CP0_Status.
1602

    
1603
    env->CP0_TCStatus[env->current_tc] = newval;
1604
    RETURN();
1605
}
1606

    
1607
void op_mttc0_tcstatus (void)
1608
{
1609
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1610

    
1611
    // TODO: Sync with CP0_Status.
1612

    
1613
    env->CP0_TCStatus[other_tc] = T0;
1614
    RETURN();
1615
}
1616

    
1617
void op_mtc0_tcbind (void)
1618
{
1619
    uint32_t mask = (1 << CP0TCBd_TBE);
1620
    uint32_t newval;
1621

    
1622
    if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1623
        mask |= (1 << CP0TCBd_CurVPE);
1624
    newval = (env->CP0_TCBind[env->current_tc] & ~mask) | (T0 & mask);
1625
    env->CP0_TCBind[env->current_tc] = newval;
1626
    RETURN();
1627
}
1628

    
1629
void op_mttc0_tcbind (void)
1630
{
1631
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1632
    uint32_t mask = (1 << CP0TCBd_TBE);
1633
    uint32_t newval;
1634

    
1635
    if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1636
        mask |= (1 << CP0TCBd_CurVPE);
1637
    newval = (env->CP0_TCBind[other_tc] & ~mask) | (T0 & mask);
1638
    env->CP0_TCBind[other_tc] = newval;
1639
    RETURN();
1640
}
1641

    
1642
void op_mtc0_tcrestart (void)
1643
{
1644
    env->PC[env->current_tc] = T0;
1645
    env->CP0_TCStatus[env->current_tc] &= ~(1 << CP0TCSt_TDS);
1646
    env->CP0_LLAddr = 0ULL;
1647
    /* MIPS16 not implemented. */
1648
    RETURN();
1649
}
1650

    
1651
void op_mttc0_tcrestart (void)
1652
{
1653
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1654

    
1655
    env->PC[other_tc] = T0;
1656
    env->CP0_TCStatus[other_tc] &= ~(1 << CP0TCSt_TDS);
1657
    env->CP0_LLAddr = 0ULL;
1658
    /* MIPS16 not implemented. */
1659
    RETURN();
1660
}
1661

    
1662
void op_mtc0_tchalt (void)
1663
{
1664
    env->CP0_TCHalt[env->current_tc] = T0 & 0x1;
1665

    
1666
    // TODO: Halt TC / Restart (if allocated+active) TC.
1667

    
1668
    RETURN();
1669
}
1670

    
1671
void op_mttc0_tchalt (void)
1672
{
1673
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1674

    
1675
    // TODO: Halt TC / Restart (if allocated+active) TC.
1676

    
1677
    env->CP0_TCHalt[other_tc] = T0;
1678
    RETURN();
1679
}
1680

    
1681
void op_mtc0_tccontext (void)
1682
{
1683
    env->CP0_TCContext[env->current_tc] = T0;
1684
    RETURN();
1685
}
1686

    
1687
void op_mttc0_tccontext (void)
1688
{
1689
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1690

    
1691
    env->CP0_TCContext[other_tc] = T0;
1692
    RETURN();
1693
}
1694

    
1695
void op_mtc0_tcschedule (void)
1696
{
1697
    env->CP0_TCSchedule[env->current_tc] = T0;
1698
    RETURN();
1699
}
1700

    
1701
void op_mttc0_tcschedule (void)
1702
{
1703
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1704

    
1705
    env->CP0_TCSchedule[other_tc] = T0;
1706
    RETURN();
1707
}
1708

    
1709
void op_mtc0_tcschefback (void)
1710
{
1711
    env->CP0_TCScheFBack[env->current_tc] = T0;
1712
    RETURN();
1713
}
1714

    
1715
void op_mttc0_tcschefback (void)
1716
{
1717
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1718

    
1719
    env->CP0_TCScheFBack[other_tc] = T0;
1720
    RETURN();
1721
}
1722

    
1723
void op_mtc0_entrylo1 (void)
1724
{
1725
    /* Large physaddr not implemented */
1726
    /* 1k pages not implemented */
1727
    env->CP0_EntryLo1 = T0 & 0x3FFFFFFF;
1728
    RETURN();
1729
}
1730

    
1731
void op_mtc0_context (void)
1732
{
1733
    env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF);
1734
    RETURN();
1735
}
1736

    
1737
void op_mtc0_pagemask (void)
1738
{
1739
    /* 1k pages not implemented */
1740
    env->CP0_PageMask = T0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1741
    RETURN();
1742
}
1743

    
1744
void op_mtc0_pagegrain (void)
1745
{
1746
    /* SmartMIPS not implemented */
1747
    /* Large physaddr not implemented */
1748
    /* 1k pages not implemented */
1749
    env->CP0_PageGrain = 0;
1750
    RETURN();
1751
}
1752

    
1753
void op_mtc0_wired (void)
1754
{
1755
    env->CP0_Wired = T0 % env->tlb->nb_tlb;
1756
    RETURN();
1757
}
1758

    
1759
void op_mtc0_srsconf0 (void)
1760
{
1761
    env->CP0_SRSConf0 |= T0 & env->CP0_SRSConf0_rw_bitmask;
1762
    RETURN();
1763
}
1764

    
1765
void op_mtc0_srsconf1 (void)
1766
{
1767
    env->CP0_SRSConf1 |= T0 & env->CP0_SRSConf1_rw_bitmask;
1768
    RETURN();
1769
}
1770

    
1771
void op_mtc0_srsconf2 (void)
1772
{
1773
    env->CP0_SRSConf2 |= T0 & env->CP0_SRSConf2_rw_bitmask;
1774
    RETURN();
1775
}
1776

    
1777
void op_mtc0_srsconf3 (void)
1778
{
1779
    env->CP0_SRSConf3 |= T0 & env->CP0_SRSConf3_rw_bitmask;
1780
    RETURN();
1781
}
1782

    
1783
void op_mtc0_srsconf4 (void)
1784
{
1785
    env->CP0_SRSConf4 |= T0 & env->CP0_SRSConf4_rw_bitmask;
1786
    RETURN();
1787
}
1788

    
1789
void op_mtc0_hwrena (void)
1790
{
1791
    env->CP0_HWREna = T0 & 0x0000000F;
1792
    RETURN();
1793
}
1794

    
1795
void op_mtc0_count (void)
1796
{
1797
    CALL_FROM_TB2(cpu_mips_store_count, env, T0);
1798
    RETURN();
1799
}
1800

    
1801
void op_mtc0_entryhi (void)
1802
{
1803
    target_ulong old, val;
1804

    
1805
    /* 1k pages not implemented */
1806
    val = T0 & ((TARGET_PAGE_MASK << 1) | 0xFF);
1807
#ifdef TARGET_MIPS64
1808
    val &= env->SEGMask;
1809
#endif
1810
    old = env->CP0_EntryHi;
1811
    env->CP0_EntryHi = val;
1812
    if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1813
        uint32_t tcst = env->CP0_TCStatus[env->current_tc] & ~0xff;
1814
        env->CP0_TCStatus[env->current_tc] = tcst | (val & 0xff);
1815
    }
1816
    /* If the ASID changes, flush qemu's TLB.  */
1817
    if ((old & 0xFF) != (val & 0xFF))
1818
        CALL_FROM_TB2(cpu_mips_tlb_flush, env, 1);
1819
    RETURN();
1820
}
1821

    
1822
void op_mttc0_entryhi(void)
1823
{
1824
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1825

    
1826
    env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (T0 & ~0xff);
1827
    env->CP0_TCStatus[other_tc] = (env->CP0_TCStatus[other_tc] & ~0xff) | (T0 & 0xff);
1828
    RETURN();
1829
}
1830

    
1831
void op_mtc0_compare (void)
1832
{
1833
    CALL_FROM_TB2(cpu_mips_store_compare, env, T0);
1834
    RETURN();
1835
}
1836

    
1837
void op_mtc0_status (void)
1838
{
1839
    uint32_t val, old;
1840
    uint32_t mask = env->CP0_Status_rw_bitmask;
1841

    
1842
    val = T0 & mask;
1843
    old = env->CP0_Status;
1844
    if (!(val & (1 << CP0St_EXL)) &&
1845
        !(val & (1 << CP0St_ERL)) &&
1846
        !(env->hflags & MIPS_HFLAG_DM) &&
1847
        (val & (1 << CP0St_UM)))
1848
        env->hflags |= MIPS_HFLAG_UM;
1849
#ifdef TARGET_MIPS64
1850
    if (!(env->CP0_Config0 & (0x3 << CP0C0_AT)) ||
1851
        ((env->hflags & MIPS_HFLAG_UM) &&
1852
        !(val & (1 << CP0St_PX)) &&
1853
        !(val & (1 << CP0St_UX))))
1854
        env->hflags &= ~MIPS_HFLAG_64;
1855
#endif
1856
    if (val & (1 << CP0St_CU1))
1857
        env->hflags |= MIPS_HFLAG_FPU;
1858
    else
1859
        env->hflags &= ~MIPS_HFLAG_FPU;
1860
    if (val & (1 << CP0St_FR))
1861
        env->hflags |= MIPS_HFLAG_F64;
1862
    else
1863
        env->hflags &= ~MIPS_HFLAG_F64;
1864
    env->CP0_Status = (env->CP0_Status & ~mask) | val;
1865
    if (loglevel & CPU_LOG_EXEC)
1866
        CALL_FROM_TB2(do_mtc0_status_debug, old, val);
1867
    CALL_FROM_TB1(cpu_mips_update_irq, env);
1868
    RETURN();
1869
}
1870

    
1871
void op_mttc0_status(void)
1872
{
1873
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1874
    uint32_t tcstatus = env->CP0_TCStatus[other_tc];
1875

    
1876
    env->CP0_Status = T0 & ~0xf1000018;
1877
    tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (T0 & (0xf << CP0St_CU0));
1878
    tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((T0 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));
1879
    tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((T0 & (0x3 << CP0St_R0)) << (CP0TCSt_TKSU - CP0St_R0));
1880
    env->CP0_TCStatus[other_tc] = tcstatus;
1881
    RETURN();
1882
}
1883

    
1884
void op_mtc0_intctl (void)
1885
{
1886
    /* vectored interrupts not implemented, timer on int 7,
1887
       no performance counters. */
1888
    env->CP0_IntCtl |= T0 & 0x000002e0;
1889
    RETURN();
1890
}
1891

    
1892
void op_mtc0_srsctl (void)
1893
{
1894
    uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1895
    env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (T0 & mask);
1896
    RETURN();
1897
}
1898

    
1899
void op_mtc0_srsmap (void)
1900
{
1901
    env->CP0_SRSMap = T0;
1902
    RETURN();
1903
}
1904

    
1905
void op_mtc0_cause (void)
1906
{
1907
    uint32_t mask = 0x00C00300;
1908

    
1909
    if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR))
1910
        mask |= 1 << CP0Ca_DC;
1911

    
1912
    env->CP0_Cause = (env->CP0_Cause & ~mask) | (T0 & mask);
1913

    
1914
    /* Handle the software interrupt as an hardware one, as they
1915
       are very similar */
1916
    if (T0 & CP0Ca_IP_mask) {
1917
        CALL_FROM_TB1(cpu_mips_update_irq, env);
1918
    }
1919
    RETURN();
1920
}
1921

    
1922
void op_mtc0_epc (void)
1923
{
1924
    env->CP0_EPC = T0;
1925
    RETURN();
1926
}
1927

    
1928
void op_mtc0_ebase (void)
1929
{
1930
    /* vectored interrupts not implemented */
1931
    /* Multi-CPU not implemented */
1932
    env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000);
1933
    RETURN();
1934
}
1935

    
1936
void op_mtc0_config0 (void)
1937
{
1938
    env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (T0 & 0x00000007);
1939
    RETURN();
1940
}
1941

    
1942
void op_mtc0_config2 (void)
1943
{
1944
    /* tertiary/secondary caches not implemented */
1945
    env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1946
    RETURN();
1947
}
1948

    
1949
void op_mtc0_watchlo (void)
1950
{
1951
    /* Watch exceptions for instructions, data loads, data stores
1952
       not implemented. */
1953
    env->CP0_WatchLo[PARAM1] = (T0 & ~0x7);
1954
    RETURN();
1955
}
1956

    
1957
void op_mtc0_watchhi (void)
1958
{
1959
    env->CP0_WatchHi[PARAM1] = (T0 & 0x40FF0FF8);
1960
    env->CP0_WatchHi[PARAM1] &= ~(env->CP0_WatchHi[PARAM1] & T0 & 0x7);
1961
    RETURN();
1962
}
1963

    
1964
void op_mtc0_xcontext (void)
1965
{
1966
    target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1967
    env->CP0_XContext = (env->CP0_XContext & mask) | (T0 & ~mask);
1968
    RETURN();
1969
}
1970

    
1971
void op_mtc0_framemask (void)
1972
{
1973
    env->CP0_Framemask = T0; /* XXX */
1974
    RETURN();
1975
}
1976

    
1977
void op_mtc0_debug (void)
1978
{
1979
    env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120);
1980
    if (T0 & (1 << CP0DB_DM))
1981
        env->hflags |= MIPS_HFLAG_DM;
1982
    else
1983
        env->hflags &= ~MIPS_HFLAG_DM;
1984
    RETURN();
1985
}
1986

    
1987
void op_mttc0_debug(void)
1988
{
1989
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1990

    
1991
    /* XXX: Might be wrong, check with EJTAG spec. */
1992
    env->CP0_Debug_tcstatus[other_tc] = T0 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1993
    env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1994
                     (T0 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1995
    RETURN();
1996
}
1997

    
1998
void op_mtc0_depc (void)
1999
{
2000
    env->CP0_DEPC = T0;
2001
    RETURN();
2002
}
2003

    
2004
void op_mtc0_performance0 (void)
2005
{
2006
    env->CP0_Performance0 = T0; /* XXX */
2007
    RETURN();
2008
}
2009

    
2010
void op_mtc0_taglo (void)
2011
{
2012
    env->CP0_TagLo = T0 & 0xFFFFFCF6;
2013
    RETURN();
2014
}
2015

    
2016
void op_mtc0_datalo (void)
2017
{
2018
    env->CP0_DataLo = T0; /* XXX */
2019
    RETURN();
2020
}
2021

    
2022
void op_mtc0_taghi (void)
2023
{
2024
    env->CP0_TagHi = T0; /* XXX */
2025
    RETURN();
2026
}
2027

    
2028
void op_mtc0_datahi (void)
2029
{
2030
    env->CP0_DataHi = T0; /* XXX */
2031
    RETURN();
2032
}
2033

    
2034
void op_mtc0_errorepc (void)
2035
{
2036
    env->CP0_ErrorEPC = T0;
2037
    RETURN();
2038
}
2039

    
2040
void op_mtc0_desave (void)
2041
{
2042
    env->CP0_DESAVE = T0;
2043
    RETURN();
2044
}
2045

    
2046
#ifdef TARGET_MIPS64
2047
void op_dmfc0_yqmask (void)
2048
{
2049
    T0 = env->CP0_YQMask;
2050
    RETURN();
2051
}
2052

    
2053
void op_dmfc0_vpeschedule (void)
2054
{
2055
    T0 = env->CP0_VPESchedule;
2056
    RETURN();
2057
}
2058

    
2059
void op_dmfc0_vpeschefback (void)
2060
{
2061
    T0 = env->CP0_VPEScheFBack;
2062
    RETURN();
2063
}
2064

    
2065
void op_dmfc0_entrylo0 (void)
2066
{
2067
    T0 = env->CP0_EntryLo0;
2068
    RETURN();
2069
}
2070

    
2071
void op_dmfc0_tcrestart (void)
2072
{
2073
    T0 = env->PC[env->current_tc];
2074
    RETURN();
2075
}
2076

    
2077
void op_dmfc0_tchalt (void)
2078
{
2079
    T0 = env->CP0_TCHalt[env->current_tc];
2080
    RETURN();
2081
}
2082

    
2083
void op_dmfc0_tccontext (void)
2084
{
2085
    T0 = env->CP0_TCContext[env->current_tc];
2086
    RETURN();
2087
}
2088

    
2089
void op_dmfc0_tcschedule (void)
2090
{
2091
    T0 = env->CP0_TCSchedule[env->current_tc];
2092
    RETURN();
2093
}
2094

    
2095
void op_dmfc0_tcschefback (void)
2096
{
2097
    T0 = env->CP0_TCScheFBack[env->current_tc];
2098
    RETURN();
2099
}
2100

    
2101
void op_dmfc0_entrylo1 (void)
2102
{
2103
    T0 = env->CP0_EntryLo1;
2104
    RETURN();
2105
}
2106

    
2107
void op_dmfc0_context (void)
2108
{
2109
    T0 = env->CP0_Context;
2110
    RETURN();
2111
}
2112

    
2113
void op_dmfc0_badvaddr (void)
2114
{
2115
    T0 = env->CP0_BadVAddr;
2116
    RETURN();
2117
}
2118

    
2119
void op_dmfc0_entryhi (void)
2120
{
2121
    T0 = env->CP0_EntryHi;
2122
    RETURN();
2123
}
2124

    
2125
void op_dmfc0_epc (void)
2126
{
2127
    T0 = env->CP0_EPC;
2128
    RETURN();
2129
}
2130

    
2131
void op_dmfc0_lladdr (void)
2132
{
2133
    T0 = env->CP0_LLAddr >> 4;
2134
    RETURN();
2135
}
2136

    
2137
void op_dmfc0_watchlo (void)
2138
{
2139
    T0 = env->CP0_WatchLo[PARAM1];
2140
    RETURN();
2141
}
2142

    
2143
void op_dmfc0_xcontext (void)
2144
{
2145
    T0 = env->CP0_XContext;
2146
    RETURN();
2147
}
2148

    
2149
void op_dmfc0_depc (void)
2150
{
2151
    T0 = env->CP0_DEPC;
2152
    RETURN();
2153
}
2154

    
2155
void op_dmfc0_errorepc (void)
2156
{
2157
    T0 = env->CP0_ErrorEPC;
2158
    RETURN();
2159
}
2160
#endif /* TARGET_MIPS64 */
2161

    
2162
/* MIPS MT functions */
2163
void op_mftgpr(void)
2164
{
2165
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2166

    
2167
    T0 = env->gpr[PARAM1][other_tc];
2168
    RETURN();
2169
}
2170

    
2171
void op_mftlo(void)
2172
{
2173
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2174

    
2175
    T0 = env->LO[PARAM1][other_tc];
2176
    RETURN();
2177
}
2178

    
2179
void op_mfthi(void)
2180
{
2181
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2182

    
2183
    T0 = env->HI[PARAM1][other_tc];
2184
    RETURN();
2185
}
2186

    
2187
void op_mftacx(void)
2188
{
2189
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2190

    
2191
    T0 = env->ACX[PARAM1][other_tc];
2192
    RETURN();
2193
}
2194

    
2195
void op_mftdsp(void)
2196
{
2197
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2198

    
2199
    T0 = env->DSPControl[other_tc];
2200
    RETURN();
2201
}
2202

    
2203
void op_mttgpr(void)
2204
{
2205
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2206

    
2207
    T0 = env->gpr[PARAM1][other_tc];
2208
    RETURN();
2209
}
2210

    
2211
void op_mttlo(void)
2212
{
2213
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2214

    
2215
    T0 = env->LO[PARAM1][other_tc];
2216
    RETURN();
2217
}
2218

    
2219
void op_mtthi(void)
2220
{
2221
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2222

    
2223
    T0 = env->HI[PARAM1][other_tc];
2224
    RETURN();
2225
}
2226

    
2227
void op_mttacx(void)
2228
{
2229
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2230

    
2231
    T0 = env->ACX[PARAM1][other_tc];
2232
    RETURN();
2233
}
2234

    
2235
void op_mttdsp(void)
2236
{
2237
    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2238

    
2239
    T0 = env->DSPControl[other_tc];
2240
    RETURN();
2241
}
2242

    
2243

    
2244
void op_dmt(void)
2245
{
2246
    // TODO
2247
    T0 = 0;
2248
    // rt = T0
2249
    RETURN();
2250
}
2251

    
2252
void op_emt(void)
2253
{
2254
    // TODO
2255
    T0 = 0;
2256
    // rt = T0
2257
    RETURN();
2258
}
2259

    
2260
void op_dvpe(void)
2261
{
2262
    // TODO
2263
    T0 = 0;
2264
    // rt = T0
2265
    RETURN();
2266
}
2267

    
2268
void op_evpe(void)
2269
{
2270
    // TODO
2271
    T0 = 0;
2272
    // rt = T0
2273
    RETURN();
2274
}
2275

    
2276
void op_fork(void)
2277
{
2278
    // T0 = rt, T1 = rs
2279
    T0 = 0;
2280
    // TODO: store to TC register
2281
    RETURN();
2282
}
2283

    
2284
void op_yield(void)
2285
{
2286
    if (T0 < 0) {
2287
        /* No scheduling policy implemented. */
2288
        if (T0 != -2) {
2289
            if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
2290
                env->CP0_TCStatus[env->current_tc] & (1 << CP0TCSt_DT)) {
2291
                env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
2292
                env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
2293
                CALL_FROM_TB1(do_raise_exception, EXCP_THREAD);
2294
            }
2295
        }
2296
    } else if (T0 == 0) {
2297
        if (0 /* TODO: TC underflow */) {
2298
            env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
2299
            CALL_FROM_TB1(do_raise_exception, EXCP_THREAD);
2300
        } else {
2301
            // TODO: Deallocate TC
2302
        }
2303
    } else if (T0 > 0) {
2304
        /* Yield qualifier inputs not implemented. */
2305
        env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
2306
        env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
2307
        CALL_FROM_TB1(do_raise_exception, EXCP_THREAD);
2308
    }
2309
    T0 = env->CP0_YQMask;
2310
    RETURN();
2311
}
2312

    
2313
/* CP1 functions */
2314
#if 0
2315
# define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env)
2316
#else
2317
# define DEBUG_FPU_STATE() do { } while(0)
2318
#endif
2319

    
2320
void op_cp0_enabled(void)
2321
{
2322
    if (!(env->CP0_Status & (1 << CP0St_CU0)) &&
2323
        (env->hflags & MIPS_HFLAG_UM)) {
2324
        CALL_FROM_TB2(do_raise_exception_err, EXCP_CpU, 0);
2325
    }
2326
    RETURN();
2327
}
2328

    
2329
void op_cfc1 (void)
2330
{
2331
    CALL_FROM_TB1(do_cfc1, PARAM1);
2332
    DEBUG_FPU_STATE();
2333
    RETURN();
2334
}
2335

    
2336
void op_ctc1 (void)
2337
{
2338
    CALL_FROM_TB1(do_ctc1, PARAM1);
2339
    DEBUG_FPU_STATE();
2340
    RETURN();
2341
}
2342

    
2343
void op_mfc1 (void)
2344
{
2345
    T0 = WT0;
2346
    DEBUG_FPU_STATE();
2347
    RETURN();
2348
}
2349

    
2350
void op_mtc1 (void)
2351
{
2352
    WT0 = T0;
2353
    DEBUG_FPU_STATE();
2354
    RETURN();
2355
}
2356

    
2357
void op_dmfc1 (void)
2358
{
2359
    T0 = DT0;
2360
    DEBUG_FPU_STATE();
2361
    RETURN();
2362
}
2363

    
2364
void op_dmtc1 (void)
2365
{
2366
    DT0 = T0;
2367
    DEBUG_FPU_STATE();
2368
    RETURN();
2369
}
2370

    
2371
void op_mfhc1 (void)
2372
{
2373
    T0 = WTH0;
2374
    DEBUG_FPU_STATE();
2375
    RETURN();
2376
}
2377

    
2378
void op_mthc1 (void)
2379
{
2380
    WTH0 = T0;
2381
    DEBUG_FPU_STATE();
2382
    RETURN();
2383
}
2384

    
2385
/* Float support.
2386
   Single precition routines have a "s" suffix, double precision a
2387
   "d" suffix, 32bit integer "w", 64bit integer "l", paired singe "ps",
2388
   paired single lowwer "pl", paired single upper "pu".  */
2389

    
2390
#define FLOAT_OP(name, p) void OPPROTO op_float_##name##_##p(void)
2391

    
2392
FLOAT_OP(cvtd, s)
2393
{
2394
    CALL_FROM_TB0(do_float_cvtd_s);
2395
    DEBUG_FPU_STATE();
2396
    RETURN();
2397
}
2398
FLOAT_OP(cvtd, w)
2399
{
2400
    CALL_FROM_TB0(do_float_cvtd_w);
2401
    DEBUG_FPU_STATE();
2402
    RETURN();
2403
}
2404
FLOAT_OP(cvtd, l)
2405
{
2406
    CALL_FROM_TB0(do_float_cvtd_l);
2407
    DEBUG_FPU_STATE();
2408
    RETURN();
2409
}
2410
FLOAT_OP(cvtl, d)
2411
{
2412
    CALL_FROM_TB0(do_float_cvtl_d);
2413
    DEBUG_FPU_STATE();
2414
    RETURN();
2415
}
2416
FLOAT_OP(cvtl, s)
2417
{
2418
    CALL_FROM_TB0(do_float_cvtl_s);
2419
    DEBUG_FPU_STATE();
2420
    RETURN();
2421
}
2422
FLOAT_OP(cvtps, s)
2423
{
2424
    WT2 = WT0;
2425
    WTH2 = WT1;
2426
    DEBUG_FPU_STATE();
2427
    RETURN();
2428
}
2429
FLOAT_OP(cvtps, pw)
2430
{
2431
    CALL_FROM_TB0(do_float_cvtps_pw);
2432
    DEBUG_FPU_STATE();
2433
    RETURN();
2434
}
2435
FLOAT_OP(cvtpw, ps)
2436
{
2437
    CALL_FROM_TB0(do_float_cvtpw_ps);
2438
    DEBUG_FPU_STATE();
2439
    RETURN();
2440
}
2441
FLOAT_OP(cvts, d)
2442
{
2443
    CALL_FROM_TB0(do_float_cvts_d);
2444
    DEBUG_FPU_STATE();
2445
    RETURN();
2446
}
2447
FLOAT_OP(cvts, w)
2448
{
2449
    CALL_FROM_TB0(do_float_cvts_w);
2450
    DEBUG_FPU_STATE();
2451
    RETURN();
2452
}
2453
FLOAT_OP(cvts, l)
2454
{
2455
    CALL_FROM_TB0(do_float_cvts_l);
2456
    DEBUG_FPU_STATE();
2457
    RETURN();
2458
}
2459
FLOAT_OP(cvts, pl)
2460
{
2461
    CALL_FROM_TB0(do_float_cvts_pl);
2462
    DEBUG_FPU_STATE();
2463
    RETURN();
2464
}
2465
FLOAT_OP(cvts, pu)
2466
{
2467
    CALL_FROM_TB0(do_float_cvts_pu);
2468
    DEBUG_FPU_STATE();
2469
    RETURN();
2470
}
2471
FLOAT_OP(cvtw, s)
2472
{
2473
    CALL_FROM_TB0(do_float_cvtw_s);
2474
    DEBUG_FPU_STATE();
2475
    RETURN();
2476
}
2477
FLOAT_OP(cvtw, d)
2478
{
2479
    CALL_FROM_TB0(do_float_cvtw_d);
2480
    DEBUG_FPU_STATE();
2481
    RETURN();
2482
}
2483

    
2484
FLOAT_OP(pll, ps)
2485
{
2486
    DT2 = ((uint64_t)WT0 << 32) | WT1;
2487
    DEBUG_FPU_STATE();
2488
    RETURN();
2489
}
2490
FLOAT_OP(plu, ps)
2491
{
2492
    DT2 = ((uint64_t)WT0 << 32) | WTH1;
2493
    DEBUG_FPU_STATE();
2494
    RETURN();
2495
}
2496
FLOAT_OP(pul, ps)
2497
{
2498
    DT2 = ((uint64_t)WTH0 << 32) | WT1;
2499
    DEBUG_FPU_STATE();
2500
    RETURN();
2501
}
2502
FLOAT_OP(puu, ps)
2503
{
2504
    DT2 = ((uint64_t)WTH0 << 32) | WTH1;
2505
    DEBUG_FPU_STATE();
2506
    RETURN();
2507
}
2508

    
2509
#define FLOAT_ROUNDOP(op, ttype, stype)                    \
2510
FLOAT_OP(op ## ttype, stype)                               \
2511
{                                                          \
2512
    CALL_FROM_TB0(do_float_ ## op ## ttype ## _ ## stype); \
2513
    DEBUG_FPU_STATE();                                     \
2514
    RETURN();                                              \
2515
}
2516

    
2517
FLOAT_ROUNDOP(round, l, d)
2518
FLOAT_ROUNDOP(round, l, s)
2519
FLOAT_ROUNDOP(round, w, d)
2520
FLOAT_ROUNDOP(round, w, s)
2521

    
2522
FLOAT_ROUNDOP(trunc, l, d)
2523
FLOAT_ROUNDOP(trunc, l, s)
2524
FLOAT_ROUNDOP(trunc, w, d)
2525
FLOAT_ROUNDOP(trunc, w, s)
2526

    
2527
FLOAT_ROUNDOP(ceil, l, d)
2528
FLOAT_ROUNDOP(ceil, l, s)
2529
FLOAT_ROUNDOP(ceil, w, d)
2530
FLOAT_ROUNDOP(ceil, w, s)
2531

    
2532
FLOAT_ROUNDOP(floor, l, d)
2533
FLOAT_ROUNDOP(floor, l, s)
2534
FLOAT_ROUNDOP(floor, w, d)
2535
FLOAT_ROUNDOP(floor, w, s)
2536
#undef FLOAR_ROUNDOP
2537

    
2538
FLOAT_OP(movf, d)
2539
{
2540
    if (!(env->fpu->fcr31 & PARAM1))
2541
        DT2 = DT0;
2542
    DEBUG_FPU_STATE();
2543
    RETURN();
2544
}
2545
FLOAT_OP(movf, s)
2546
{
2547
    if (!(env->fpu->fcr31 & PARAM1))
2548
        WT2 = WT0;
2549
    DEBUG_FPU_STATE();
2550
    RETURN();
2551
}
2552
FLOAT_OP(movf, ps)
2553
{
2554
    if (!(env->fpu->fcr31 & PARAM1)) {
2555
        WT2 = WT0;
2556
        WTH2 = WTH0;
2557
    }
2558
    DEBUG_FPU_STATE();
2559
    RETURN();
2560
}
2561
FLOAT_OP(movt, d)
2562
{
2563
    if (env->fpu->fcr31 & PARAM1)
2564
        DT2 = DT0;
2565
    DEBUG_FPU_STATE();
2566
    RETURN();
2567
}
2568
FLOAT_OP(movt, s)
2569
{
2570
    if (env->fpu->fcr31 & PARAM1)
2571
        WT2 = WT0;
2572
    DEBUG_FPU_STATE();
2573
    RETURN();
2574
}
2575
FLOAT_OP(movt, ps)
2576
{
2577
    if (env->fpu->fcr31 & PARAM1) {
2578
        WT2 = WT0;
2579
        WTH2 = WTH0;
2580
    }
2581
    DEBUG_FPU_STATE();
2582
    RETURN();
2583
}
2584
FLOAT_OP(movz, d)
2585
{
2586
    if (!T0)
2587
        DT2 = DT0;
2588
    DEBUG_FPU_STATE();
2589
    RETURN();
2590
}
2591
FLOAT_OP(movz, s)
2592
{
2593
    if (!T0)
2594
        WT2 = WT0;
2595
    DEBUG_FPU_STATE();
2596
    RETURN();
2597
}
2598
FLOAT_OP(movz, ps)
2599
{
2600
    if (!T0) {
2601
        WT2 = WT0;
2602
        WTH2 = WTH0;
2603
    }
2604
    DEBUG_FPU_STATE();
2605
    RETURN();
2606
}
2607
FLOAT_OP(movn, d)
2608
{
2609
    if (T0)
2610
        DT2 = DT0;
2611
    DEBUG_FPU_STATE();
2612
    RETURN();
2613
}
2614
FLOAT_OP(movn, s)
2615
{
2616
    if (T0)
2617
        WT2 = WT0;
2618
    DEBUG_FPU_STATE();
2619
    RETURN();
2620
}
2621
FLOAT_OP(movn, ps)
2622
{
2623
    if (T0) {
2624
        WT2 = WT0;
2625
        WTH2 = WTH0;
2626
    }
2627
    DEBUG_FPU_STATE();
2628
    RETURN();
2629
}
2630

    
2631
/* operations calling helpers, for s, d and ps */
2632
#define FLOAT_HOP(name) \
2633
FLOAT_OP(name, d)         \
2634
{                         \
2635
    CALL_FROM_TB0(do_float_ ## name ## _d);  \
2636
    DEBUG_FPU_STATE();    \
2637
    RETURN();             \
2638
}                         \
2639
FLOAT_OP(name, s)         \
2640
{                         \
2641
    CALL_FROM_TB0(do_float_ ## name ## _s);  \
2642
    DEBUG_FPU_STATE();    \
2643
    RETURN();             \
2644
}                         \
2645
FLOAT_OP(name, ps)        \
2646
{                         \
2647
    CALL_FROM_TB0(do_float_ ## name ## _ps); \
2648
    DEBUG_FPU_STATE();    \
2649
    RETURN();             \
2650
}
2651
FLOAT_HOP(add)
2652
FLOAT_HOP(sub)
2653
FLOAT_HOP(mul)
2654
FLOAT_HOP(div)
2655
FLOAT_HOP(recip2)
2656
FLOAT_HOP(rsqrt2)
2657
FLOAT_HOP(rsqrt1)
2658
FLOAT_HOP(recip1)
2659
#undef FLOAT_HOP
2660

    
2661
/* operations calling helpers, for s and d */
2662
#define FLOAT_HOP(name)   \
2663
FLOAT_OP(name, d)         \
2664
{                         \
2665
    CALL_FROM_TB0(do_float_ ## name ## _d);  \
2666
    DEBUG_FPU_STATE();    \
2667
    RETURN();             \
2668
}                         \
2669
FLOAT_OP(name, s)         \
2670
{                         \
2671
    CALL_FROM_TB0(do_float_ ## name ## _s);  \
2672
    DEBUG_FPU_STATE();    \
2673
    RETURN();             \
2674
}
2675
FLOAT_HOP(rsqrt)
2676
FLOAT_HOP(recip)
2677
#undef FLOAT_HOP
2678

    
2679
/* operations calling helpers, for ps */
2680
#define FLOAT_HOP(name)   \
2681
FLOAT_OP(name, ps)        \
2682
{                         \
2683
    CALL_FROM_TB0(do_float_ ## name ## _ps); \
2684
    DEBUG_FPU_STATE();    \
2685
    RETURN();             \
2686
}
2687
FLOAT_HOP(addr)
2688
FLOAT_HOP(mulr)
2689
#undef FLOAT_HOP
2690

    
2691
/* ternary operations */
2692
#define FLOAT_TERNOP(name1, name2) \
2693
FLOAT_OP(name1 ## name2, d)        \
2694
{                                  \
2695
    FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fpu->fp_status);    \
2696
    FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fpu->fp_status);    \
2697
    DEBUG_FPU_STATE();             \
2698
    RETURN();                      \
2699
}                                  \
2700
FLOAT_OP(name1 ## name2, s)        \
2701
{                                  \
2702
    FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status);    \
2703
    FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status);    \
2704
    DEBUG_FPU_STATE();             \
2705
    RETURN();                      \
2706
}                                  \
2707
FLOAT_OP(name1 ## name2, ps)       \
2708
{                                  \
2709
    FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status);    \
2710
    FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fpu->fp_status); \
2711
    FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status);    \
2712
    FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fpu->fp_status); \
2713
    DEBUG_FPU_STATE();             \
2714
    RETURN();                      \
2715
}
2716
FLOAT_TERNOP(mul, add)
2717
FLOAT_TERNOP(mul, sub)
2718
#undef FLOAT_TERNOP
2719

    
2720
/* negated ternary operations */
2721
#define FLOAT_NTERNOP(name1, name2) \
2722
FLOAT_OP(n ## name1 ## name2, d)    \
2723
{                                   \
2724
    FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fpu->fp_status);    \
2725
    FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fpu->fp_status);    \
2726
    FDT2 ^= 1ULL << 63;             \
2727
    DEBUG_FPU_STATE();              \
2728
    RETURN();                       \
2729
}                                   \
2730
FLOAT_OP(n ## name1 ## name2, s)    \
2731
{                                   \
2732
    FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status);    \
2733
    FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status);    \
2734
    FST2 ^= 1 << 31;                \
2735
    DEBUG_FPU_STATE();              \
2736
    RETURN();                       \
2737
}                                   \
2738
FLOAT_OP(n ## name1 ## name2, ps)   \
2739
{                                   \
2740
    FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status);    \
2741
    FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fpu->fp_status); \
2742
    FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status);    \
2743
    FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fpu->fp_status); \
2744
    FST2 ^= 1 << 31;                \
2745
    FSTH2 ^= 1 << 31;               \
2746
    DEBUG_FPU_STATE();              \
2747
    RETURN();                       \
2748
}
2749
FLOAT_NTERNOP(mul, add)
2750
FLOAT_NTERNOP(mul, sub)
2751
#undef FLOAT_NTERNOP
2752

    
2753
/* unary operations, modifying fp status  */
2754
#define FLOAT_UNOP(name)  \
2755
FLOAT_OP(name, d)         \
2756
{                         \
2757
    FDT2 = float64_ ## name(FDT0, &env->fpu->fp_status);   \
2758
    DEBUG_FPU_STATE();    \
2759
    RETURN();                      \
2760
}                         \
2761
FLOAT_OP(name, s)         \
2762
{                         \
2763
    FST2 = float32_ ## name(FST0, &env->fpu->fp_status);   \
2764
    DEBUG_FPU_STATE();    \
2765
    RETURN();             \
2766
}
2767
FLOAT_UNOP(sqrt)
2768
#undef FLOAT_UNOP
2769

    
2770
/* unary operations, not modifying fp status  */
2771
#define FLOAT_UNOP(name)  \
2772
FLOAT_OP(name, d)         \
2773
{                         \
2774
    FDT2 = float64_ ## name(FDT0);   \
2775
    DEBUG_FPU_STATE();    \
2776
    RETURN();             \
2777
}                         \
2778
FLOAT_OP(name, s)         \
2779
{                         \
2780
    FST2 = float32_ ## name(FST0);   \
2781
    DEBUG_FPU_STATE();    \
2782
    RETURN();             \
2783
}                         \
2784
FLOAT_OP(name, ps)        \
2785
{                         \
2786
    FST2 = float32_ ## name(FST0);   \
2787
    FSTH2 = float32_ ## name(FSTH0); \
2788
    DEBUG_FPU_STATE();    \
2789
    RETURN();             \
2790
}
2791
FLOAT_UNOP(abs)
2792
FLOAT_UNOP(chs)
2793
#undef FLOAT_UNOP
2794

    
2795
FLOAT_OP(mov, d)
2796
{
2797
    FDT2 = FDT0;
2798
    DEBUG_FPU_STATE();
2799
    RETURN();
2800
}
2801
FLOAT_OP(mov, s)
2802
{
2803
    FST2 = FST0;
2804
    DEBUG_FPU_STATE();
2805
    RETURN();
2806
}
2807
FLOAT_OP(mov, ps)
2808
{
2809
    FST2 = FST0;
2810
    FSTH2 = FSTH0;
2811
    DEBUG_FPU_STATE();
2812
    RETURN();
2813
}
2814
FLOAT_OP(alnv, ps)
2815
{
2816
    switch (T0 & 0x7) {
2817
    case 0:
2818
        FST2 = FST0;
2819
        FSTH2 = FSTH0;
2820
        break;
2821
    case 4:
2822
#ifdef TARGET_WORDS_BIGENDIAN
2823
        FSTH2 = FST0;
2824
        FST2 = FSTH1;
2825
#else
2826
        FSTH2 = FST1;
2827
        FST2 = FSTH0;
2828
#endif
2829
        break;
2830
    default: /* unpredictable */
2831
        break;
2832
    }
2833
    DEBUG_FPU_STATE();
2834
    RETURN();
2835
}
2836

    
2837
#ifdef CONFIG_SOFTFLOAT
2838
#define clear_invalid() do {                                \
2839
    int flags = get_float_exception_flags(&env->fpu->fp_status); \
2840
    flags &= ~float_flag_invalid;                           \
2841
    set_float_exception_flags(flags, &env->fpu->fp_status);      \
2842
} while(0)
2843
#else
2844
#define clear_invalid() do { } while(0)
2845
#endif
2846

    
2847
extern void dump_fpu_s(CPUState *env);
2848

    
2849
#define CMP_OP(fmt, op)                                \
2850
void OPPROTO op_cmp ## _ ## fmt ## _ ## op(void)       \
2851
{                                                      \
2852
    CALL_FROM_TB1(do_cmp ## _ ## fmt ## _ ## op, PARAM1); \
2853
    DEBUG_FPU_STATE();                                 \
2854
    RETURN();                                          \
2855
}                                                      \
2856
void OPPROTO op_cmpabs ## _ ## fmt ## _ ## op(void)    \
2857
{                                                      \
2858
    CALL_FROM_TB1(do_cmpabs ## _ ## fmt ## _ ## op, PARAM1); \
2859
    DEBUG_FPU_STATE();                                 \
2860
    RETURN();                                          \
2861
}
2862
#define CMP_OPS(op)   \
2863
CMP_OP(d, op)         \
2864
CMP_OP(s, op)         \
2865
CMP_OP(ps, op)
2866

    
2867
CMP_OPS(f)
2868
CMP_OPS(un)
2869
CMP_OPS(eq)
2870
CMP_OPS(ueq)
2871
CMP_OPS(olt)
2872
CMP_OPS(ult)
2873
CMP_OPS(ole)
2874
CMP_OPS(ule)
2875
CMP_OPS(sf)
2876
CMP_OPS(ngle)
2877
CMP_OPS(seq)
2878
CMP_OPS(ngl)
2879
CMP_OPS(lt)
2880
CMP_OPS(nge)
2881
CMP_OPS(le)
2882
CMP_OPS(ngt)
2883
#undef CMP_OPS
2884
#undef CMP_OP
2885

    
2886
void op_bc1f (void)
2887
{
2888
    T0 = !!(~GET_FP_COND(env->fpu) & (0x1 << PARAM1));
2889
    DEBUG_FPU_STATE();
2890
    RETURN();
2891
}
2892
void op_bc1any2f (void)
2893
{
2894
    T0 = !!(~GET_FP_COND(env->fpu) & (0x3 << PARAM1));
2895
    DEBUG_FPU_STATE();
2896
    RETURN();
2897
}
2898
void op_bc1any4f (void)
2899
{
2900
    T0 = !!(~GET_FP_COND(env->fpu) & (0xf << PARAM1));
2901
    DEBUG_FPU_STATE();
2902
    RETURN();
2903
}
2904

    
2905
void op_bc1t (void)
2906
{
2907
    T0 = !!(GET_FP_COND(env->fpu) & (0x1 << PARAM1));
2908
    DEBUG_FPU_STATE();
2909
    RETURN();
2910
}
2911
void op_bc1any2t (void)
2912
{
2913
    T0 = !!(GET_FP_COND(env->fpu) & (0x3 << PARAM1));
2914
    DEBUG_FPU_STATE();
2915
    RETURN();
2916
}
2917
void op_bc1any4t (void)
2918
{
2919
    T0 = !!(GET_FP_COND(env->fpu) & (0xf << PARAM1));
2920
    DEBUG_FPU_STATE();
2921
    RETURN();
2922
}
2923

    
2924
void op_tlbwi (void)
2925
{
2926
    CALL_FROM_TB0(env->tlb->do_tlbwi);
2927
    RETURN();
2928
}
2929

    
2930
void op_tlbwr (void)
2931
{
2932
    CALL_FROM_TB0(env->tlb->do_tlbwr);
2933
    RETURN();
2934
}
2935

    
2936
void op_tlbp (void)
2937
{
2938
    CALL_FROM_TB0(env->tlb->do_tlbp);
2939
    RETURN();
2940
}
2941

    
2942
void op_tlbr (void)
2943
{
2944
    CALL_FROM_TB0(env->tlb->do_tlbr);
2945
    RETURN();
2946
}
2947

    
2948
/* Specials */
2949
#if defined (CONFIG_USER_ONLY)
2950
void op_tls_value (void)
2951
{
2952
    T0 = env->tls_value;
2953
}
2954
#endif
2955

    
2956
void op_pmon (void)
2957
{
2958
    CALL_FROM_TB1(do_pmon, PARAM1);
2959
    RETURN();
2960
}
2961

    
2962
void op_di (void)
2963
{
2964
    T0 = env->CP0_Status;
2965
    env->CP0_Status = T0 & ~(1 << CP0St_IE);
2966
    CALL_FROM_TB1(cpu_mips_update_irq, env);
2967
    RETURN();
2968
}
2969

    
2970
void op_ei (void)
2971
{
2972
    T0 = env->CP0_Status;
2973
    env->CP0_Status = T0 | (1 << CP0St_IE);
2974
    CALL_FROM_TB1(cpu_mips_update_irq, env);
2975
    RETURN();
2976
}
2977

    
2978
void op_trap (void)
2979
{
2980
    if (T0) {
2981
        CALL_FROM_TB1(do_raise_exception, EXCP_TRAP);
2982
    }
2983
    RETURN();
2984
}
2985

    
2986
void op_debug (void)
2987
{
2988
    CALL_FROM_TB1(do_raise_exception, EXCP_DEBUG);
2989
    RETURN();
2990
}
2991

    
2992
void op_set_lladdr (void)
2993
{
2994
    env->CP0_LLAddr = T2;
2995
    RETURN();
2996
}
2997

    
2998
void debug_pre_eret (void);
2999
void debug_post_eret (void);
3000
void op_eret (void)
3001
{
3002
    if (loglevel & CPU_LOG_EXEC)
3003
        CALL_FROM_TB0(debug_pre_eret);
3004
    if (env->CP0_Status & (1 << CP0St_ERL)) {
3005
        env->PC[env->current_tc] = env->CP0_ErrorEPC;
3006
        env->CP0_Status &= ~(1 << CP0St_ERL);
3007
    } else {
3008
        env->PC[env->current_tc] = env->CP0_EPC;
3009
        env->CP0_Status &= ~(1 << CP0St_EXL);
3010
    }
3011
    if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
3012
        !(env->CP0_Status & (1 << CP0St_ERL)) &&
3013
        !(env->hflags & MIPS_HFLAG_DM) &&
3014
        (env->CP0_Status & (1 << CP0St_UM)))
3015
        env->hflags |= MIPS_HFLAG_UM;
3016
#ifdef TARGET_MIPS64
3017
    if (!(env->CP0_Config0 & (0x3 << CP0C0_AT)) ||
3018
        ((env->hflags & MIPS_HFLAG_UM) &&
3019
        !(env->CP0_Status & (1 << CP0St_PX)) &&
3020
        !(env->CP0_Status & (1 << CP0St_UX))))
3021
        env->hflags &= ~MIPS_HFLAG_64;
3022
#endif
3023
    if (loglevel & CPU_LOG_EXEC)
3024
        CALL_FROM_TB0(debug_post_eret);
3025
    env->CP0_LLAddr = 1;
3026
    RETURN();
3027
}
3028

    
3029
void op_deret (void)
3030
{
3031
    if (loglevel & CPU_LOG_EXEC)
3032
        CALL_FROM_TB0(debug_pre_eret);
3033
    env->PC[env->current_tc] = env->CP0_DEPC;
3034
    env->hflags |= MIPS_HFLAG_DM;
3035
    if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
3036
        !(env->CP0_Status & (1 << CP0St_ERL)) &&
3037
        !(env->hflags & MIPS_HFLAG_DM) &&
3038
        (env->CP0_Status & (1 << CP0St_UM)))
3039
        env->hflags |= MIPS_HFLAG_UM;
3040
#ifdef TARGET_MIPS64
3041
    if (!(env->CP0_Config0 & (0x3 << CP0C0_AT)) ||
3042
        ((env->hflags & MIPS_HFLAG_UM) &&
3043
        !(env->CP0_Status & (1 << CP0St_PX)) &&
3044
        !(env->CP0_Status & (1 << CP0St_UX))))
3045
        env->hflags &= ~MIPS_HFLAG_64;
3046
#endif
3047
    if (loglevel & CPU_LOG_EXEC)
3048
        CALL_FROM_TB0(debug_post_eret);
3049
    env->CP0_LLAddr = 1;
3050
    RETURN();
3051
}
3052

    
3053
void op_rdhwr_cpunum(void)
3054
{
3055
    if (!(env->hflags & MIPS_HFLAG_UM) ||
3056
        (env->CP0_HWREna & (1 << 0)) ||
3057
        (env->CP0_Status & (1 << CP0St_CU0)))
3058
        T0 = env->CP0_EBase & 0x3ff;
3059
    else
3060
        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
3061
    RETURN();
3062
}
3063

    
3064
void op_rdhwr_synci_step(void)
3065
{
3066
    if (!(env->hflags & MIPS_HFLAG_UM) ||
3067
        (env->CP0_HWREna & (1 << 1)) ||
3068
        (env->CP0_Status & (1 << CP0St_CU0)))
3069
        T0 = env->SYNCI_Step;
3070
    else
3071
        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
3072
    RETURN();
3073
}
3074

    
3075
void op_rdhwr_cc(void)
3076
{
3077
    if (!(env->hflags & MIPS_HFLAG_UM) ||
3078
        (env->CP0_HWREna & (1 << 2)) ||
3079
        (env->CP0_Status & (1 << CP0St_CU0)))
3080
        T0 = env->CP0_Count;
3081
    else
3082
        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
3083
    RETURN();
3084
}
3085

    
3086
void op_rdhwr_ccres(void)
3087
{
3088
    if (!(env->hflags & MIPS_HFLAG_UM) ||
3089
        (env->CP0_HWREna & (1 << 3)) ||
3090
        (env->CP0_Status & (1 << CP0St_CU0)))
3091
        T0 = env->CCRes;
3092
    else
3093
        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
3094
    RETURN();
3095
}
3096

    
3097
void op_save_state (void)
3098
{
3099
    env->hflags = PARAM1;
3100
    RETURN();
3101
}
3102

    
3103
void op_save_pc (void)
3104
{
3105
    env->PC[env->current_tc] = PARAM1;
3106
    RETURN();
3107
}
3108

    
3109
#ifdef TARGET_MIPS64
3110
void op_save_pc64 (void)
3111
{
3112
    env->PC[env->current_tc] = ((uint64_t)PARAM1 << 32) | (uint32_t)PARAM2;
3113
    RETURN();
3114
}
3115
#endif
3116

    
3117
void op_interrupt_restart (void)
3118
{
3119
    if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
3120
        !(env->CP0_Status & (1 << CP0St_ERL)) &&
3121
        !(env->hflags & MIPS_HFLAG_DM) &&
3122
        (env->CP0_Status & (1 << CP0St_IE)) &&
3123
        (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) {
3124
        env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
3125
        CALL_FROM_TB1(do_raise_exception, EXCP_EXT_INTERRUPT);
3126
    }
3127
    RETURN();
3128
}
3129

    
3130
void op_raise_exception (void)
3131
{
3132
    CALL_FROM_TB1(do_raise_exception, PARAM1);
3133
    RETURN();
3134
}
3135

    
3136
void op_raise_exception_err (void)
3137
{
3138
    CALL_FROM_TB2(do_raise_exception_err, PARAM1, PARAM2);
3139
    RETURN();
3140
}
3141

    
3142
void op_exit_tb (void)
3143
{
3144
    EXIT_TB();
3145
    RETURN();
3146
}
3147

    
3148
void op_wait (void)
3149
{
3150
    env->halted = 1;
3151
    CALL_FROM_TB1(do_raise_exception, EXCP_HLT);
3152
    RETURN();
3153
}
3154

    
3155
/* Bitfield operations. */
3156
void op_ext(void)
3157
{
3158
    unsigned int pos = PARAM1;
3159
    unsigned int size = PARAM2;
3160

    
3161
    T0 = ((uint32_t)T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0);
3162
    RETURN();
3163
}
3164

    
3165
void op_ins(void)
3166
{
3167
    unsigned int pos = PARAM1;
3168
    unsigned int size = PARAM2;
3169
    target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos;
3170

    
3171
    T0 = (T0 & ~mask) | (((uint32_t)T1 << pos) & mask);
3172
    RETURN();
3173
}
3174

    
3175
void op_wsbh(void)
3176
{
3177
    T0 = ((T1 << 8) & ~0x00FF00FF) | ((T1 >> 8) & 0x00FF00FF);
3178
    RETURN();
3179
}
3180

    
3181
#ifdef TARGET_MIPS64
3182
void op_dext(void)
3183
{
3184
    unsigned int pos = PARAM1;
3185
    unsigned int size = PARAM2;
3186

    
3187
    T0 = (T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0);
3188
    RETURN();
3189
}
3190

    
3191
void op_dins(void)
3192
{
3193
    unsigned int pos = PARAM1;
3194
    unsigned int size = PARAM2;
3195
    target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos;
3196

    
3197
    T0 = (T0 & ~mask) | ((T1 << pos) & mask);
3198
    RETURN();
3199
}
3200

    
3201
void op_dsbh(void)
3202
{
3203
    T0 = ((T1 << 8) & ~0x00FF00FF00FF00FFULL) | ((T1 >> 8) & 0x00FF00FF00FF00FFULL);
3204
    RETURN();
3205
}
3206

    
3207
void op_dshd(void)
3208
{
3209
    T0 = ((T1 << 16) & ~0x0000FFFF0000FFFFULL) | ((T1 >> 16) & 0x0000FFFF0000FFFFULL);
3210
    RETURN();
3211
}
3212
#endif
3213

    
3214
void op_seb(void)
3215
{
3216
    T0 = ((T1 & 0xFF) ^ 0x80) - 0x80;
3217
    RETURN();
3218
}
3219

    
3220
void op_seh(void)
3221
{
3222
    T0 = ((T1 & 0xFFFF) ^ 0x8000) - 0x8000;
3223
    RETURN();
3224
}