root / target-sh4 / op.c @ 5fafdf24
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/*
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* SH4 emulation
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*
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* Copyright (c) 2005 Samuel Tardieu
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "exec.h" |
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static inline void set_flag(uint32_t flag) |
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{
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env->flags |= flag; |
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} |
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static inline void clr_flag(uint32_t flag) |
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{
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env->flags &= ~flag; |
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} |
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static inline void set_t(void) |
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{
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env->sr |= SR_T; |
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} |
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|
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static inline void clr_t(void) |
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{
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env->sr &= ~SR_T; |
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} |
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|
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static inline void cond_t(int cond) |
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{
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if (cond)
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set_t(); |
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else
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clr_t(); |
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} |
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|
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void OPPROTO op_movl_imm_T0(void) |
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{
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T0 = (uint32_t) PARAM1; |
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RETURN(); |
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} |
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|
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void OPPROTO op_movl_imm_T1(void) |
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{
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T0 = (uint32_t) PARAM1; |
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RETURN(); |
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} |
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|
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void OPPROTO op_movl_imm_T2(void) |
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{
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T0 = (uint32_t) PARAM1; |
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RETURN(); |
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} |
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|
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void OPPROTO op_cmp_eq_imm_T0(void) |
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{
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cond_t((int32_t) T0 == (int32_t) PARAM1); |
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RETURN(); |
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} |
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|
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void OPPROTO op_cmd_eq_T0_T1(void) |
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{
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cond_t(T0 == T1); |
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RETURN(); |
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} |
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|
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void OPPROTO op_cmd_hs_T0_T1(void) |
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{
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cond_t((uint32_t) T0 <= (uint32_t) T1); |
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RETURN(); |
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} |
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|
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void OPPROTO op_cmd_ge_T0_T1(void) |
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{
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cond_t((int32_t) T0 <= (int32_t) T1); |
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RETURN(); |
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} |
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|
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void OPPROTO op_cmd_hi_T0_T1(void) |
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{
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cond_t((uint32_t) T0 < (uint32_t) T1); |
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RETURN(); |
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} |
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|
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void OPPROTO op_cmd_gt_T0_T1(void) |
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{
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cond_t((int32_t) T0 < (int32_t) T1); |
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RETURN(); |
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} |
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|
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void OPPROTO op_not_T0(void) |
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{
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T0 = ~T0; |
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RETURN(); |
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} |
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|
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void OPPROTO op_bf_s(void) |
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{
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env->delayed_pc = PARAM1; |
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set_flag(DELAY_SLOT_CONDITIONAL | ((~env->sr) & SR_T)); |
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RETURN(); |
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} |
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|
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void OPPROTO op_bt_s(void) |
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{
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env->delayed_pc = PARAM1; |
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set_flag(DELAY_SLOT_CONDITIONAL | (env->sr & SR_T)); |
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RETURN(); |
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} |
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|
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void OPPROTO op_bra(void) |
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{
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env->delayed_pc = PARAM1; |
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set_flag(DELAY_SLOT); |
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RETURN(); |
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} |
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|
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void OPPROTO op_braf_T0(void) |
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{
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env->delayed_pc = PARAM1 + T0; |
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set_flag(DELAY_SLOT); |
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RETURN(); |
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} |
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void OPPROTO op_bsr(void) |
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{
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env->pr = PARAM1; |
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env->delayed_pc = PARAM2; |
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set_flag(DELAY_SLOT); |
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RETURN(); |
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} |
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|
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void OPPROTO op_bsrf_T0(void) |
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{
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env->pr = PARAM1; |
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env->delayed_pc = PARAM1 + T0; |
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set_flag(DELAY_SLOT); |
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RETURN(); |
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} |
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void OPPROTO op_jsr_T0(void) |
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{
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env->pr = PARAM1; |
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env->delayed_pc = T0; |
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set_flag(DELAY_SLOT); |
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RETURN(); |
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} |
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void OPPROTO op_rts(void) |
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{
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env->delayed_pc = env->pr; |
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set_flag(DELAY_SLOT); |
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RETURN(); |
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} |
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void OPPROTO op_clr_delay_slot(void) |
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{
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clr_flag(DELAY_SLOT); |
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RETURN(); |
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} |
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void OPPROTO op_clr_delay_slot_conditional(void) |
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{
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clr_flag(DELAY_SLOT_CONDITIONAL); |
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RETURN(); |
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} |
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void OPPROTO op_exit_tb(void) |
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{
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EXIT_TB(); |
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RETURN(); |
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} |
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void OPPROTO op_addl_imm_T0(void) |
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{
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T0 += PARAM1; |
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RETURN(); |
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} |
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void OPPROTO op_addl_imm_T1(void) |
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{
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T1 += PARAM1; |
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RETURN(); |
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} |
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void OPPROTO op_clrmac(void) |
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{
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env->mach = env->macl = 0;
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RETURN(); |
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} |
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void OPPROTO op_clrs(void) |
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{
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env->sr &= ~SR_S; |
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RETURN(); |
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} |
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void OPPROTO op_clrt(void) |
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{
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env->sr &= ~SR_T; |
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RETURN(); |
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} |
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void OPPROTO op_sets(void) |
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{
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env->sr |= SR_S; |
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RETURN(); |
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} |
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void OPPROTO op_sett(void) |
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{
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env->sr |= SR_T; |
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RETURN(); |
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} |
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void OPPROTO op_frchg(void) |
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{
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env->fpscr ^= FPSCR_FR; |
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RETURN(); |
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} |
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void OPPROTO op_fschg(void) |
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{
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env->fpscr ^= FPSCR_SZ; |
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RETURN(); |
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} |
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void OPPROTO op_rte(void) |
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{
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env->sr = env->ssr; |
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env->delayed_pc = env->spc; |
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set_flag(DELAY_SLOT); |
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RETURN(); |
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} |
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void OPPROTO op_swapb_T0(void) |
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{
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T0 = (T0 & 0xffff0000) | ((T0 & 0xff) << 8) | ((T0 >> 8) & 0xff); |
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RETURN(); |
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} |
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void OPPROTO op_swapw_T0(void) |
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{
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T0 = ((T0 & 0xffff) << 16) | ((T0 >> 16) & 0xffff); |
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RETURN(); |
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} |
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void OPPROTO op_xtrct_T0_T1(void) |
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{
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T1 = ((T0 & 0xffff) << 16) | ((T1 >> 16) & 0xffff); |
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RETURN(); |
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} |
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void OPPROTO op_addc_T0_T1(void) |
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{
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helper_addc_T0_T1(); |
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RETURN(); |
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} |
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void OPPROTO op_addv_T0_T1(void) |
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{
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helper_addv_T0_T1(); |
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RETURN(); |
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} |
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void OPPROTO op_cmp_eq_T0_T1(void) |
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{
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cond_t(T1 == T0); |
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RETURN(); |
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} |
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void OPPROTO op_cmp_ge_T0_T1(void) |
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{
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cond_t((int32_t) T1 >= (int32_t) T0); |
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RETURN(); |
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} |
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void OPPROTO op_cmp_gt_T0_T1(void) |
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{
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cond_t((int32_t) T1 > (int32_t) T0); |
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RETURN(); |
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} |
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void OPPROTO op_cmp_hi_T0_T1(void) |
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{
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cond_t((uint32_t) T1 > (uint32_t) T0); |
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RETURN(); |
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} |
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void OPPROTO op_cmp_hs_T0_T1(void) |
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{
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cond_t((uint32_t) T1 >= (uint32_t) T0); |
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RETURN(); |
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} |
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void OPPROTO op_cmp_str_T0_T1(void) |
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{
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cond_t((T0 & 0x000000ff) == (T1 & 0x000000ff) || |
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(T0 & 0x0000ff00) == (T1 & 0x0000ff00) || |
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(T0 & 0x00ff0000) == (T1 & 0x00ff0000) || |
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(T0 & 0xff000000) == (T1 & 0xff000000)); |
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RETURN(); |
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} |
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|
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void OPPROTO op_tst_T0_T1(void) |
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{
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cond_t((T1 & T0) == 0);
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RETURN(); |
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} |
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|
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void OPPROTO op_div0s_T0_T1(void) |
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{
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if (T1 & 0x80000000) |
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env->sr |= SR_Q; |
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else
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env->sr &= ~SR_Q; |
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if (T0 & 0x80000000) |
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env->sr |= SR_M; |
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else
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env->sr &= ~SR_M; |
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cond_t((T1 ^ T0) & 0x80000000);
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RETURN(); |
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} |
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void OPPROTO op_div0u(void) |
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{
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env->sr &= ~(SR_M | SR_Q | SR_T); |
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RETURN(); |
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} |
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|
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void OPPROTO op_div1_T0_T1(void) |
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{
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helper_div1_T0_T1(); |
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RETURN(); |
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} |
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|
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void OPPROTO op_dmulsl_T0_T1(void) |
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{
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helper_dmulsl_T0_T1(); |
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RETURN(); |
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} |
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void OPPROTO op_dmulul_T0_T1(void) |
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{
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helper_dmulul_T0_T1(); |
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RETURN(); |
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} |
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|
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void OPPROTO op_macl_T0_T1(void) |
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{
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helper_macl_T0_T1(); |
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RETURN(); |
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} |
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void OPPROTO op_macw_T0_T1(void) |
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{
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helper_macw_T0_T1(); |
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RETURN(); |
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} |
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|
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void OPPROTO op_mull_T0_T1(void) |
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{
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env->macl = (T0 * T1) & 0xffffffff;
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RETURN(); |
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} |
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|
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void OPPROTO op_mulsw_T0_T1(void) |
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{
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env->macl = (int32_t) T0 *(int32_t) T1; |
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RETURN(); |
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} |
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|
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void OPPROTO op_muluw_T0_T1(void) |
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{
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env->macl = (uint32_t) T0 *(uint32_t) T1; |
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RETURN(); |
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} |
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|
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void OPPROTO op_neg_T0(void) |
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{
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T0 = -T0; |
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RETURN(); |
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} |
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|
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void OPPROTO op_negc_T0(void) |
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{
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helper_negc_T0(); |
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RETURN(); |
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} |
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|
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void OPPROTO op_shad_T0_T1(void) |
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{
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if ((T0 & 0x80000000) == 0) |
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T1 <<= (T0 & 0x1f);
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else if ((T0 & 0x1f) == 0) |
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T1 = 0;
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else
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T1 = ((int32_t) T1) >> ((~T0 & 0x1f) + 1); |
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RETURN(); |
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} |
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|
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void OPPROTO op_shld_T0_T1(void) |
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{
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if ((T0 & 0x80000000) == 0) |
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T1 <<= (T0 & 0x1f);
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else if ((T0 & 0x1f) == 0) |
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T1 = 0;
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else
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T1 = ((uint32_t) T1) >> ((~T0 & 0x1f) + 1); |
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RETURN(); |
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} |
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|
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void OPPROTO op_subc_T0_T1(void) |
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{
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helper_subc_T0_T1(); |
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RETURN(); |
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} |
| 431 |
|
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void OPPROTO op_subv_T0_T1(void) |
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{
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helper_subv_T0_T1(); |
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RETURN(); |
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} |
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|
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void OPPROTO op_trapa(void) |
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{
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env->tra = PARAM1 * 2;
|
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env->exception_index = 0x160;
|
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do_raise_exception(); |
| 443 |
RETURN(); |
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} |
| 445 |
|
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void OPPROTO op_cmp_pl_T0(void) |
| 447 |
{
|
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cond_t((int32_t) T0 > 0);
|
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RETURN(); |
| 450 |
} |
| 451 |
|
| 452 |
void OPPROTO op_cmp_pz_T0(void) |
| 453 |
{
|
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cond_t((int32_t) T0 >= 0);
|
| 455 |
RETURN(); |
| 456 |
} |
| 457 |
|
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void OPPROTO op_jmp_T0(void) |
| 459 |
{
|
| 460 |
env->delayed_pc = T0; |
| 461 |
set_flag(DELAY_SLOT); |
| 462 |
RETURN(); |
| 463 |
} |
| 464 |
|
| 465 |
void OPPROTO op_movl_rN_rN(void) |
| 466 |
{
|
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env->gregs[PARAM2] = env->gregs[PARAM1]; |
| 468 |
RETURN(); |
| 469 |
} |
| 470 |
|
| 471 |
void OPPROTO op_ldcl_rMplus_rN_bank(void) |
| 472 |
{
|
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env->gregs[PARAM2] = env->gregs[PARAM1]; |
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env->gregs[PARAM1] += 4;
|
| 475 |
RETURN(); |
| 476 |
} |
| 477 |
|
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void OPPROTO op_ldc_T0_sr(void) |
| 479 |
{
|
| 480 |
env->sr = T0 & 0x700083f3;
|
| 481 |
RETURN(); |
| 482 |
} |
| 483 |
|
| 484 |
void OPPROTO op_stc_sr_T0(void) |
| 485 |
{
|
| 486 |
T0 = env->sr; |
| 487 |
RETURN(); |
| 488 |
} |
| 489 |
|
| 490 |
#define LDSTOPS(target,load,store) \
|
| 491 |
void OPPROTO op_##load##_T0_##target (void) \ |
| 492 |
{ env ->target = T0; RETURN(); \
|
| 493 |
} \ |
| 494 |
void OPPROTO op_##store##_##target##_T0 (void) \ |
| 495 |
{ T0 = env->target; RETURN(); \
|
| 496 |
} \ |
| 497 |
|
| 498 |
LDSTOPS(gbr, ldc, stc) |
| 499 |
LDSTOPS(vbr, ldc, stc) |
| 500 |
LDSTOPS(ssr, ldc, stc) |
| 501 |
LDSTOPS(spc, ldc, stc) |
| 502 |
LDSTOPS(sgr, ldc, stc) |
| 503 |
LDSTOPS(dbr, ldc, stc) |
| 504 |
LDSTOPS(mach, lds, sts) |
| 505 |
LDSTOPS(macl, lds, sts) |
| 506 |
LDSTOPS(pr, lds, sts) |
| 507 |
LDSTOPS(fpul, lds, sts) |
| 508 |
|
| 509 |
void OPPROTO op_lds_T0_fpscr(void) |
| 510 |
{
|
| 511 |
env->fpscr = T0 & 0x003fffff;
|
| 512 |
env->fp_status.float_rounding_mode = T0 & 0x01 ?
|
| 513 |
float_round_to_zero : float_round_nearest_even; |
| 514 |
|
| 515 |
RETURN(); |
| 516 |
} |
| 517 |
|
| 518 |
void OPPROTO op_sts_fpscr_T0(void) |
| 519 |
{
|
| 520 |
T0 = env->fpscr & 0x003fffff;
|
| 521 |
RETURN(); |
| 522 |
} |
| 523 |
|
| 524 |
void OPPROTO op_movt_rN(void) |
| 525 |
{
|
| 526 |
env->gregs[PARAM1] = env->sr & SR_T; |
| 527 |
RETURN(); |
| 528 |
} |
| 529 |
|
| 530 |
void OPPROTO op_rotcl_Rn(void) |
| 531 |
{
|
| 532 |
helper_rotcl(&env->gregs[PARAM1]); |
| 533 |
RETURN(); |
| 534 |
} |
| 535 |
|
| 536 |
void OPPROTO op_rotcr_Rn(void) |
| 537 |
{
|
| 538 |
helper_rotcr(&env->gregs[PARAM1]); |
| 539 |
RETURN(); |
| 540 |
} |
| 541 |
|
| 542 |
void OPPROTO op_rotl_Rn(void) |
| 543 |
{
|
| 544 |
cond_t(env->gregs[PARAM1] & 0x80000000);
|
| 545 |
env->gregs[PARAM1] = (env->gregs[PARAM1] << 1) | (env->sr & SR_T);
|
| 546 |
RETURN(); |
| 547 |
} |
| 548 |
|
| 549 |
void OPPROTO op_rotr_Rn(void) |
| 550 |
{
|
| 551 |
cond_t(env->gregs[PARAM1] & 1);
|
| 552 |
env->gregs[PARAM1] = (env->gregs[PARAM1] >> 1) |
|
| 553 |
((env->sr & SR_T) ? 0x80000000 : 0); |
| 554 |
RETURN(); |
| 555 |
} |
| 556 |
|
| 557 |
void OPPROTO op_shal_Rn(void) |
| 558 |
{
|
| 559 |
cond_t(env->gregs[PARAM1] & 0x80000000);
|
| 560 |
env->gregs[PARAM1] <<= 1;
|
| 561 |
RETURN(); |
| 562 |
} |
| 563 |
|
| 564 |
void OPPROTO op_shar_Rn(void) |
| 565 |
{
|
| 566 |
cond_t(env->gregs[PARAM1] & 1);
|
| 567 |
env->gregs[PARAM1] >>= 1;
|
| 568 |
RETURN(); |
| 569 |
} |
| 570 |
|
| 571 |
void OPPROTO op_shlr_Rn(void) |
| 572 |
{
|
| 573 |
cond_t(env->gregs[PARAM1] & 1);
|
| 574 |
env->gregs[PARAM1] >>= 1;
|
| 575 |
RETURN(); |
| 576 |
} |
| 577 |
|
| 578 |
void OPPROTO op_shll2_Rn(void) |
| 579 |
{
|
| 580 |
env->gregs[PARAM1] <<= 2;
|
| 581 |
RETURN(); |
| 582 |
} |
| 583 |
|
| 584 |
void OPPROTO op_shll8_Rn(void) |
| 585 |
{
|
| 586 |
env->gregs[PARAM1] <<= 8;
|
| 587 |
RETURN(); |
| 588 |
} |
| 589 |
|
| 590 |
void OPPROTO op_shll16_Rn(void) |
| 591 |
{
|
| 592 |
env->gregs[PARAM1] <<= 16;
|
| 593 |
RETURN(); |
| 594 |
} |
| 595 |
|
| 596 |
void OPPROTO op_shlr2_Rn(void) |
| 597 |
{
|
| 598 |
env->gregs[PARAM1] >>= 2;
|
| 599 |
RETURN(); |
| 600 |
} |
| 601 |
|
| 602 |
void OPPROTO op_shlr8_Rn(void) |
| 603 |
{
|
| 604 |
env->gregs[PARAM1] >>= 8;
|
| 605 |
RETURN(); |
| 606 |
} |
| 607 |
|
| 608 |
void OPPROTO op_shlr16_Rn(void) |
| 609 |
{
|
| 610 |
env->gregs[PARAM1] >>= 16;
|
| 611 |
RETURN(); |
| 612 |
} |
| 613 |
|
| 614 |
void OPPROTO op_tasb_rN(void) |
| 615 |
{
|
| 616 |
cond_t(*(int8_t *) env->gregs[PARAM1] == 0);
|
| 617 |
*(int8_t *) env->gregs[PARAM1] |= 0x80;
|
| 618 |
RETURN(); |
| 619 |
} |
| 620 |
|
| 621 |
void OPPROTO op_movl_T0_rN(void) |
| 622 |
{
|
| 623 |
env->gregs[PARAM1] = T0; |
| 624 |
RETURN(); |
| 625 |
} |
| 626 |
|
| 627 |
void OPPROTO op_movl_T1_rN(void) |
| 628 |
{
|
| 629 |
env->gregs[PARAM1] = T1; |
| 630 |
RETURN(); |
| 631 |
} |
| 632 |
|
| 633 |
void OPPROTO op_movb_rN_T0(void) |
| 634 |
{
|
| 635 |
T0 = (int32_t) (int8_t) (env->gregs[PARAM1] & 0xff);
|
| 636 |
RETURN(); |
| 637 |
} |
| 638 |
|
| 639 |
void OPPROTO op_movub_rN_T0(void) |
| 640 |
{
|
| 641 |
T0 = env->gregs[PARAM1] & 0xff;
|
| 642 |
RETURN(); |
| 643 |
} |
| 644 |
|
| 645 |
void OPPROTO op_movw_rN_T0(void) |
| 646 |
{
|
| 647 |
T0 = (int32_t) (int16_t) (env->gregs[PARAM1] & 0xffff);
|
| 648 |
RETURN(); |
| 649 |
} |
| 650 |
|
| 651 |
void OPPROTO op_movuw_rN_T0(void) |
| 652 |
{
|
| 653 |
T0 = env->gregs[PARAM1] & 0xffff;
|
| 654 |
RETURN(); |
| 655 |
} |
| 656 |
|
| 657 |
void OPPROTO op_movl_rN_T0(void) |
| 658 |
{
|
| 659 |
T0 = env->gregs[PARAM1]; |
| 660 |
RETURN(); |
| 661 |
} |
| 662 |
|
| 663 |
void OPPROTO op_movb_rN_T1(void) |
| 664 |
{
|
| 665 |
T1 = (int32_t) (int8_t) (env->gregs[PARAM1] & 0xff);
|
| 666 |
RETURN(); |
| 667 |
} |
| 668 |
|
| 669 |
void OPPROTO op_movub_rN_T1(void) |
| 670 |
{
|
| 671 |
T1 = env->gregs[PARAM1] & 0xff;
|
| 672 |
RETURN(); |
| 673 |
} |
| 674 |
|
| 675 |
void OPPROTO op_movw_rN_T1(void) |
| 676 |
{
|
| 677 |
T1 = (int32_t) (int16_t) (env->gregs[PARAM1] & 0xffff);
|
| 678 |
RETURN(); |
| 679 |
} |
| 680 |
|
| 681 |
void OPPROTO op_movuw_rN_T1(void) |
| 682 |
{
|
| 683 |
T1 = env->gregs[PARAM1] & 0xffff;
|
| 684 |
RETURN(); |
| 685 |
} |
| 686 |
|
| 687 |
void OPPROTO op_movl_rN_T1(void) |
| 688 |
{
|
| 689 |
T1 = env->gregs[PARAM1]; |
| 690 |
RETURN(); |
| 691 |
} |
| 692 |
|
| 693 |
void OPPROTO op_movl_imm_rN(void) |
| 694 |
{
|
| 695 |
env->gregs[PARAM2] = PARAM1; |
| 696 |
RETURN(); |
| 697 |
} |
| 698 |
|
| 699 |
void OPPROTO op_fmov_frN_FT0(void) |
| 700 |
{
|
| 701 |
FT0 = env->fregs[PARAM1]; |
| 702 |
RETURN(); |
| 703 |
} |
| 704 |
|
| 705 |
void OPPROTO op_fmov_drN_DT0(void) |
| 706 |
{
|
| 707 |
CPU_DoubleU d; |
| 708 |
|
| 709 |
d.l.upper = *(uint32_t *)&env->fregs[PARAM1]; |
| 710 |
d.l.lower = *(uint32_t *)&env->fregs[PARAM1 + 1];
|
| 711 |
DT0 = d.d; |
| 712 |
RETURN(); |
| 713 |
} |
| 714 |
|
| 715 |
void OPPROTO op_fmov_frN_FT1(void) |
| 716 |
{
|
| 717 |
FT1 = env->fregs[PARAM1]; |
| 718 |
RETURN(); |
| 719 |
} |
| 720 |
|
| 721 |
void OPPROTO op_fmov_drN_DT1(void) |
| 722 |
{
|
| 723 |
CPU_DoubleU d; |
| 724 |
|
| 725 |
d.l.upper = *(uint32_t *)&env->fregs[PARAM1]; |
| 726 |
d.l.lower = *(uint32_t *)&env->fregs[PARAM1 + 1];
|
| 727 |
DT1 = d.d; |
| 728 |
RETURN(); |
| 729 |
} |
| 730 |
|
| 731 |
void OPPROTO op_fmov_FT0_frN(void) |
| 732 |
{
|
| 733 |
env->fregs[PARAM1] = FT0; |
| 734 |
RETURN(); |
| 735 |
} |
| 736 |
|
| 737 |
void OPPROTO op_fmov_DT0_drN(void) |
| 738 |
{
|
| 739 |
CPU_DoubleU d; |
| 740 |
|
| 741 |
d.d = DT0; |
| 742 |
*(uint32_t *)&env->fregs[PARAM1] = d.l.upper; |
| 743 |
*(uint32_t *)&env->fregs[PARAM1 + 1] = d.l.lower;
|
| 744 |
RETURN(); |
| 745 |
} |
| 746 |
|
| 747 |
void OPPROTO op_fadd_FT(void) |
| 748 |
{
|
| 749 |
FT0 = float32_add(FT0, FT1, &env->fp_status); |
| 750 |
RETURN(); |
| 751 |
} |
| 752 |
|
| 753 |
void OPPROTO op_fadd_DT(void) |
| 754 |
{
|
| 755 |
DT0 = float64_add(DT0, DT1, &env->fp_status); |
| 756 |
RETURN(); |
| 757 |
} |
| 758 |
|
| 759 |
void OPPROTO op_fsub_FT(void) |
| 760 |
{
|
| 761 |
FT0 = float32_sub(FT0, FT1, &env->fp_status); |
| 762 |
RETURN(); |
| 763 |
} |
| 764 |
|
| 765 |
void OPPROTO op_fsub_DT(void) |
| 766 |
{
|
| 767 |
DT0 = float64_sub(DT0, DT1, &env->fp_status); |
| 768 |
RETURN(); |
| 769 |
} |
| 770 |
|
| 771 |
void OPPROTO op_fmul_FT(void) |
| 772 |
{
|
| 773 |
FT0 = float32_mul(FT0, FT1, &env->fp_status); |
| 774 |
RETURN(); |
| 775 |
} |
| 776 |
|
| 777 |
void OPPROTO op_fmul_DT(void) |
| 778 |
{
|
| 779 |
DT0 = float64_mul(DT0, DT1, &env->fp_status); |
| 780 |
RETURN(); |
| 781 |
} |
| 782 |
|
| 783 |
void OPPROTO op_fdiv_FT(void) |
| 784 |
{
|
| 785 |
FT0 = float32_div(FT0, FT1, &env->fp_status); |
| 786 |
RETURN(); |
| 787 |
} |
| 788 |
|
| 789 |
void OPPROTO op_fdiv_DT(void) |
| 790 |
{
|
| 791 |
DT0 = float64_div(DT0, DT1, &env->fp_status); |
| 792 |
RETURN(); |
| 793 |
} |
| 794 |
|
| 795 |
void OPPROTO op_float_FT(void) |
| 796 |
{
|
| 797 |
FT0 = int32_to_float32(env->fpul, &env->fp_status); |
| 798 |
RETURN(); |
| 799 |
} |
| 800 |
|
| 801 |
void OPPROTO op_float_DT(void) |
| 802 |
{
|
| 803 |
DT0 = int32_to_float64(env->fpul, &env->fp_status); |
| 804 |
RETURN(); |
| 805 |
} |
| 806 |
|
| 807 |
void OPPROTO op_ftrc_FT(void) |
| 808 |
{
|
| 809 |
env->fpul = float32_to_int32_round_to_zero(FT0, &env->fp_status); |
| 810 |
RETURN(); |
| 811 |
} |
| 812 |
|
| 813 |
void OPPROTO op_ftrc_DT(void) |
| 814 |
{
|
| 815 |
env->fpul = float64_to_int32_round_to_zero(DT0, &env->fp_status); |
| 816 |
RETURN(); |
| 817 |
} |
| 818 |
|
| 819 |
void OPPROTO op_fmov_T0_frN(void) |
| 820 |
{
|
| 821 |
*(unsigned int *)&env->fregs[PARAM1] = T0; |
| 822 |
RETURN(); |
| 823 |
} |
| 824 |
|
| 825 |
void OPPROTO op_dec1_rN(void) |
| 826 |
{
|
| 827 |
env->gregs[PARAM1] -= 1;
|
| 828 |
RETURN(); |
| 829 |
} |
| 830 |
|
| 831 |
void OPPROTO op_dec2_rN(void) |
| 832 |
{
|
| 833 |
env->gregs[PARAM1] -= 2;
|
| 834 |
RETURN(); |
| 835 |
} |
| 836 |
|
| 837 |
void OPPROTO op_dec4_rN(void) |
| 838 |
{
|
| 839 |
env->gregs[PARAM1] -= 4;
|
| 840 |
RETURN(); |
| 841 |
} |
| 842 |
|
| 843 |
void OPPROTO op_dec8_rN(void) |
| 844 |
{
|
| 845 |
env->gregs[PARAM1] -= 8;
|
| 846 |
RETURN(); |
| 847 |
} |
| 848 |
|
| 849 |
void OPPROTO op_inc1_rN(void) |
| 850 |
{
|
| 851 |
env->gregs[PARAM1] += 1;
|
| 852 |
RETURN(); |
| 853 |
} |
| 854 |
|
| 855 |
void OPPROTO op_inc2_rN(void) |
| 856 |
{
|
| 857 |
env->gregs[PARAM1] += 2;
|
| 858 |
RETURN(); |
| 859 |
} |
| 860 |
|
| 861 |
void OPPROTO op_inc4_rN(void) |
| 862 |
{
|
| 863 |
env->gregs[PARAM1] += 4;
|
| 864 |
RETURN(); |
| 865 |
} |
| 866 |
|
| 867 |
void OPPROTO op_inc8_rN(void) |
| 868 |
{
|
| 869 |
env->gregs[PARAM1] += 8;
|
| 870 |
RETURN(); |
| 871 |
} |
| 872 |
|
| 873 |
void OPPROTO op_add_T0_rN(void) |
| 874 |
{
|
| 875 |
env->gregs[PARAM1] += T0; |
| 876 |
RETURN(); |
| 877 |
} |
| 878 |
|
| 879 |
void OPPROTO op_sub_T0_rN(void) |
| 880 |
{
|
| 881 |
env->gregs[PARAM1] -= T0; |
| 882 |
RETURN(); |
| 883 |
} |
| 884 |
|
| 885 |
void OPPROTO op_and_T0_rN(void) |
| 886 |
{
|
| 887 |
env->gregs[PARAM1] &= T0; |
| 888 |
RETURN(); |
| 889 |
} |
| 890 |
|
| 891 |
void OPPROTO op_or_T0_rN(void) |
| 892 |
{
|
| 893 |
env->gregs[PARAM1] |= T0; |
| 894 |
RETURN(); |
| 895 |
} |
| 896 |
|
| 897 |
void OPPROTO op_xor_T0_rN(void) |
| 898 |
{
|
| 899 |
env->gregs[PARAM1] ^= T0; |
| 900 |
RETURN(); |
| 901 |
} |
| 902 |
|
| 903 |
void OPPROTO op_add_rN_T0(void) |
| 904 |
{
|
| 905 |
T0 += env->gregs[PARAM1]; |
| 906 |
RETURN(); |
| 907 |
} |
| 908 |
|
| 909 |
void OPPROTO op_add_rN_T1(void) |
| 910 |
{
|
| 911 |
T1 += env->gregs[PARAM1]; |
| 912 |
RETURN(); |
| 913 |
} |
| 914 |
|
| 915 |
void OPPROTO op_add_imm_rN(void) |
| 916 |
{
|
| 917 |
env->gregs[PARAM2] += PARAM1; |
| 918 |
RETURN(); |
| 919 |
} |
| 920 |
|
| 921 |
void OPPROTO op_and_imm_rN(void) |
| 922 |
{
|
| 923 |
env->gregs[PARAM2] &= PARAM1; |
| 924 |
RETURN(); |
| 925 |
} |
| 926 |
|
| 927 |
void OPPROTO op_or_imm_rN(void) |
| 928 |
{
|
| 929 |
env->gregs[PARAM2] |= PARAM1; |
| 930 |
RETURN(); |
| 931 |
} |
| 932 |
|
| 933 |
void OPPROTO op_xor_imm_rN(void) |
| 934 |
{
|
| 935 |
env->gregs[PARAM2] ^= PARAM1; |
| 936 |
RETURN(); |
| 937 |
} |
| 938 |
|
| 939 |
void OPPROTO op_dt_rN(void) |
| 940 |
{
|
| 941 |
cond_t((--env->gregs[PARAM1]) == 0);
|
| 942 |
RETURN(); |
| 943 |
} |
| 944 |
|
| 945 |
void OPPROTO op_tst_imm_rN(void) |
| 946 |
{
|
| 947 |
cond_t((env->gregs[PARAM2] & PARAM1) == 0);
|
| 948 |
RETURN(); |
| 949 |
} |
| 950 |
|
| 951 |
void OPPROTO op_movl_T0_T1(void) |
| 952 |
{
|
| 953 |
T1 = T0; |
| 954 |
RETURN(); |
| 955 |
} |
| 956 |
|
| 957 |
void OPPROTO op_movl_fpul_FT0(void) |
| 958 |
{
|
| 959 |
FT0 = *(float32 *)&env->fpul; |
| 960 |
RETURN(); |
| 961 |
} |
| 962 |
|
| 963 |
void OPPROTO op_movl_FT0_fpul(void) |
| 964 |
{
|
| 965 |
*(float32 *)&env->fpul = FT0; |
| 966 |
RETURN(); |
| 967 |
} |
| 968 |
|
| 969 |
void OPPROTO op_goto_tb0(void) |
| 970 |
{
|
| 971 |
GOTO_TB(op_goto_tb0, PARAM1, 0);
|
| 972 |
RETURN(); |
| 973 |
} |
| 974 |
|
| 975 |
void OPPROTO op_goto_tb1(void) |
| 976 |
{
|
| 977 |
GOTO_TB(op_goto_tb1, PARAM1, 1);
|
| 978 |
RETURN(); |
| 979 |
} |
| 980 |
|
| 981 |
void OPPROTO op_movl_imm_PC(void) |
| 982 |
{
|
| 983 |
env->pc = PARAM1; |
| 984 |
RETURN(); |
| 985 |
} |
| 986 |
|
| 987 |
void OPPROTO op_jT(void) |
| 988 |
{
|
| 989 |
if (env->sr & SR_T)
|
| 990 |
GOTO_LABEL_PARAM(1);
|
| 991 |
RETURN(); |
| 992 |
} |
| 993 |
|
| 994 |
void OPPROTO op_jdelayed(void) |
| 995 |
{
|
| 996 |
uint32_t flags; |
| 997 |
flags = env->flags; |
| 998 |
env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); |
| 999 |
if (flags & DELAY_SLOT)
|
| 1000 |
GOTO_LABEL_PARAM(1);
|
| 1001 |
RETURN(); |
| 1002 |
} |
| 1003 |
|
| 1004 |
void OPPROTO op_movl_delayed_pc_PC(void) |
| 1005 |
{
|
| 1006 |
env->pc = env->delayed_pc; |
| 1007 |
RETURN(); |
| 1008 |
} |
| 1009 |
|
| 1010 |
void OPPROTO op_addl_GBR_T0(void) |
| 1011 |
{
|
| 1012 |
T0 += env->gbr; |
| 1013 |
RETURN(); |
| 1014 |
} |
| 1015 |
|
| 1016 |
void OPPROTO op_and_imm_T0(void) |
| 1017 |
{
|
| 1018 |
T0 &= PARAM1; |
| 1019 |
RETURN(); |
| 1020 |
} |
| 1021 |
|
| 1022 |
void OPPROTO op_or_imm_T0(void) |
| 1023 |
{
|
| 1024 |
T0 |= PARAM1; |
| 1025 |
RETURN(); |
| 1026 |
} |
| 1027 |
|
| 1028 |
void OPPROTO op_xor_imm_T0(void) |
| 1029 |
{
|
| 1030 |
T0 ^= PARAM1; |
| 1031 |
RETURN(); |
| 1032 |
} |
| 1033 |
|
| 1034 |
void OPPROTO op_tst_imm_T0(void) |
| 1035 |
{
|
| 1036 |
cond_t((T0 & PARAM1) == 0);
|
| 1037 |
RETURN(); |
| 1038 |
} |
| 1039 |
|
| 1040 |
void OPPROTO op_raise_illegal_instruction(void) |
| 1041 |
{
|
| 1042 |
env->exception_index = 0x180;
|
| 1043 |
do_raise_exception(); |
| 1044 |
RETURN(); |
| 1045 |
} |
| 1046 |
|
| 1047 |
void OPPROTO op_raise_slot_illegal_instruction(void) |
| 1048 |
{
|
| 1049 |
env->exception_index = 0x1a0;
|
| 1050 |
do_raise_exception(); |
| 1051 |
RETURN(); |
| 1052 |
} |
| 1053 |
|
| 1054 |
void OPPROTO op_debug(void) |
| 1055 |
{
|
| 1056 |
env->exception_index = EXCP_DEBUG; |
| 1057 |
cpu_loop_exit(); |
| 1058 |
} |
| 1059 |
|
| 1060 |
/* Load and store */
|
| 1061 |
#define MEMSUFFIX _raw
|
| 1062 |
#include "op_mem.c" |
| 1063 |
#undef MEMSUFFIX
|
| 1064 |
#if !defined(CONFIG_USER_ONLY)
|
| 1065 |
#define MEMSUFFIX _user
|
| 1066 |
#include "op_mem.c" |
| 1067 |
#undef MEMSUFFIX
|
| 1068 |
|
| 1069 |
#define MEMSUFFIX _kernel
|
| 1070 |
#include "op_mem.c" |
| 1071 |
#undef MEMSUFFIX
|
| 1072 |
#endif
|