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/*
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 * QEMU System Emulator header
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 *
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 * Copyright (c) 2003 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#ifndef VL_H
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#define VL_H
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/* we put basic includes here to avoid repeating them in device drivers */
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdarg.h>
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#include <string.h>
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#include <inttypes.h>
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#include <limits.h>
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#include <time.h>
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#include <ctype.h>
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#include <errno.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include <sys/stat.h>
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#ifndef O_LARGEFILE
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#define O_LARGEFILE 0
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#endif
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#ifndef O_BINARY
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#define O_BINARY 0
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#endif
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#ifndef ENOMEDIUM
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#define ENOMEDIUM ENODEV
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#endif
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#ifdef _WIN32
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#include <windows.h>
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#define fsync _commit
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#define lseek _lseeki64
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#define ENOTSUP 4096
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extern int qemu_ftruncate64(int, int64_t);
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#define ftruncate qemu_ftruncate64
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static inline char *realpath(const char *path, char *resolved_path)
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{
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    _fullpath(resolved_path, path, _MAX_PATH);
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    return resolved_path;
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}
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#define PRId64 "I64d"
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#define PRIx64 "I64x"
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#define PRIu64 "I64u"
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#define PRIo64 "I64o"
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#endif
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#ifdef QEMU_TOOL
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/* we use QEMU_TOOL in the command line tools which do not depend on
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   the target CPU type */
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#include "config-host.h"
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#include <setjmp.h>
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#include "osdep.h"
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#include "bswap.h"
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#else
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#include "audio/audio.h"
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#include "cpu.h"
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#endif /* !defined(QEMU_TOOL) */
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#ifndef glue
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#define xglue(x, y) x ## y
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#define glue(x, y) xglue(x, y)
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#define stringify(s)        tostring(s)
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#define tostring(s)        #s
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#endif
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#ifndef MIN
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#define MIN(a, b) (((a) < (b)) ? (a) : (b))
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#endif
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#ifndef MAX
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#define MAX(a, b) (((a) > (b)) ? (a) : (b))
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#endif
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/* cutils.c */
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void pstrcpy(char *buf, int buf_size, const char *str);
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char *pstrcat(char *buf, int buf_size, const char *s);
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int strstart(const char *str, const char *val, const char **ptr);
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int stristart(const char *str, const char *val, const char **ptr);
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/* vl.c */
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uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
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void hw_error(const char *fmt, ...);
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extern const char *bios_dir;
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extern int vm_running;
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extern const char *qemu_name;
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typedef struct vm_change_state_entry VMChangeStateEntry;
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typedef void VMChangeStateHandler(void *opaque, int running);
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typedef void VMStopHandler(void *opaque, int reason);
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VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
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                                                     void *opaque);
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void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
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int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque);
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void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque);
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void vm_start(void);
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void vm_stop(int reason);
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typedef void QEMUResetHandler(void *opaque);
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void qemu_register_reset(QEMUResetHandler *func, void *opaque);
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void qemu_system_reset_request(void);
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void qemu_system_shutdown_request(void);
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void qemu_system_powerdown_request(void);
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#if !defined(TARGET_SPARC)
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// Please implement a power failure function to signal the OS
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#define qemu_system_powerdown() do{}while(0)
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#else
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void qemu_system_powerdown(void);
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#endif
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void main_loop_wait(int timeout);
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extern int ram_size;
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extern int bios_size;
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extern int rtc_utc;
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extern int cirrus_vga_enabled;
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extern int vmsvga_enabled;
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extern int graphic_width;
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extern int graphic_height;
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extern int graphic_depth;
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extern const char *keyboard_layout;
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extern int kqemu_allowed;
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extern int win2k_install_hack;
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extern int alt_grab;
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extern int usb_enabled;
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extern int smp_cpus;
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extern int cursor_hide;
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extern int graphic_rotate;
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extern int no_quit;
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extern int semihosting_enabled;
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extern int autostart;
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extern int old_param;
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extern const char *bootp_filename;
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#define MAX_OPTION_ROMS 16
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extern const char *option_rom[MAX_OPTION_ROMS];
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extern int nb_option_roms;
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#ifdef TARGET_SPARC
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#define MAX_PROM_ENVS 128
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extern const char *prom_envs[MAX_PROM_ENVS];
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extern unsigned int nb_prom_envs;
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#endif
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/* XXX: make it dynamic */
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#define MAX_BIOS_SIZE (4 * 1024 * 1024)
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#if defined (TARGET_PPC) || defined (TARGET_SPARC64)
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#define BIOS_SIZE ((512 + 32) * 1024)
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#elif defined(TARGET_MIPS)
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#define BIOS_SIZE (4 * 1024 * 1024)
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#endif
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/* keyboard/mouse support */
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#define MOUSE_EVENT_LBUTTON 0x01
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#define MOUSE_EVENT_RBUTTON 0x02
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#define MOUSE_EVENT_MBUTTON 0x04
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typedef void QEMUPutKBDEvent(void *opaque, int keycode);
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typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state);
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typedef struct QEMUPutMouseEntry {
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    QEMUPutMouseEvent *qemu_put_mouse_event;
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    void *qemu_put_mouse_event_opaque;
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    int qemu_put_mouse_event_absolute;
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    char *qemu_put_mouse_event_name;
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    /* used internally by qemu for handling mice */
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    struct QEMUPutMouseEntry *next;
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} QEMUPutMouseEntry;
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void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque);
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QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func,
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                                                void *opaque, int absolute,
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                                                const char *name);
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void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
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void kbd_put_keycode(int keycode);
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void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
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int kbd_mouse_is_absolute(void);
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void do_info_mice(void);
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void do_mouse_set(int index);
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/* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
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   constants) */
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#define QEMU_KEY_ESC1(c) ((c) | 0xe100)
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#define QEMU_KEY_BACKSPACE  0x007f
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#define QEMU_KEY_UP         QEMU_KEY_ESC1('A')
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#define QEMU_KEY_DOWN       QEMU_KEY_ESC1('B')
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#define QEMU_KEY_RIGHT      QEMU_KEY_ESC1('C')
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#define QEMU_KEY_LEFT       QEMU_KEY_ESC1('D')
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#define QEMU_KEY_HOME       QEMU_KEY_ESC1(1)
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#define QEMU_KEY_END        QEMU_KEY_ESC1(4)
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#define QEMU_KEY_PAGEUP     QEMU_KEY_ESC1(5)
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#define QEMU_KEY_PAGEDOWN   QEMU_KEY_ESC1(6)
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#define QEMU_KEY_DELETE     QEMU_KEY_ESC1(3)
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#define QEMU_KEY_CTRL_UP         0xe400
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#define QEMU_KEY_CTRL_DOWN       0xe401
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#define QEMU_KEY_CTRL_LEFT       0xe402
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#define QEMU_KEY_CTRL_RIGHT      0xe403
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#define QEMU_KEY_CTRL_HOME       0xe404
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#define QEMU_KEY_CTRL_END        0xe405
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#define QEMU_KEY_CTRL_PAGEUP     0xe406
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#define QEMU_KEY_CTRL_PAGEDOWN   0xe407
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void kbd_put_keysym(int keysym);
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/* async I/O support */
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typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size);
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typedef int IOCanRWHandler(void *opaque);
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typedef void IOHandler(void *opaque);
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int qemu_set_fd_handler2(int fd,
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                         IOCanRWHandler *fd_read_poll,
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                         IOHandler *fd_read,
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                         IOHandler *fd_write,
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                         void *opaque);
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int qemu_set_fd_handler(int fd,
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                        IOHandler *fd_read,
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                        IOHandler *fd_write,
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                        void *opaque);
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/* Polling handling */
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/* return TRUE if no sleep should be done afterwards */
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typedef int PollingFunc(void *opaque);
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int qemu_add_polling_cb(PollingFunc *func, void *opaque);
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void qemu_del_polling_cb(PollingFunc *func, void *opaque);
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#ifdef _WIN32
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/* Wait objects handling */
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typedef void WaitObjectFunc(void *opaque);
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int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
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void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
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#endif
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typedef struct QEMUBH QEMUBH;
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/* character device */
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#define CHR_EVENT_BREAK 0 /* serial break char */
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#define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
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#define CHR_EVENT_RESET 2 /* new connection established */
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#define CHR_IOCTL_SERIAL_SET_PARAMS   1
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typedef struct {
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    int speed;
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    int parity;
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    int data_bits;
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    int stop_bits;
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} QEMUSerialSetParams;
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#define CHR_IOCTL_SERIAL_SET_BREAK    2
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#define CHR_IOCTL_PP_READ_DATA        3
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#define CHR_IOCTL_PP_WRITE_DATA       4
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#define CHR_IOCTL_PP_READ_CONTROL     5
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#define CHR_IOCTL_PP_WRITE_CONTROL    6
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#define CHR_IOCTL_PP_READ_STATUS      7
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#define CHR_IOCTL_PP_EPP_READ_ADDR    8
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#define CHR_IOCTL_PP_EPP_READ         9
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#define CHR_IOCTL_PP_EPP_WRITE_ADDR  10
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#define CHR_IOCTL_PP_EPP_WRITE       11
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typedef void IOEventHandler(void *opaque, int event);
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typedef struct CharDriverState {
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    int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
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    void (*chr_update_read_handler)(struct CharDriverState *s);
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    int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
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    IOEventHandler *chr_event;
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    IOCanRWHandler *chr_can_read;
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    IOReadHandler *chr_read;
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    void *handler_opaque;
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    void (*chr_send_event)(struct CharDriverState *chr, int event);
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    void (*chr_close)(struct CharDriverState *chr);
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    void *opaque;
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    int focus;
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    QEMUBH *bh;
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} CharDriverState;
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CharDriverState *qemu_chr_open(const char *filename);
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void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
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int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
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void qemu_chr_send_event(CharDriverState *s, int event);
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void qemu_chr_add_handlers(CharDriverState *s,
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                           IOCanRWHandler *fd_can_read,
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                           IOReadHandler *fd_read,
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                           IOEventHandler *fd_event,
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                           void *opaque);
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int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
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void qemu_chr_reset(CharDriverState *s);
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int qemu_chr_can_read(CharDriverState *s);
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void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);
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/* consoles */
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typedef struct DisplayState DisplayState;
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typedef struct TextConsole TextConsole;
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typedef void (*vga_hw_update_ptr)(void *);
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typedef void (*vga_hw_invalidate_ptr)(void *);
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typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
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TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
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                                  vga_hw_invalidate_ptr invalidate,
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                                  vga_hw_screen_dump_ptr screen_dump,
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                                  void *opaque);
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void vga_hw_update(void);
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void vga_hw_invalidate(void);
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void vga_hw_screen_dump(const char *filename);
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int is_graphic_console(void);
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CharDriverState *text_console_init(DisplayState *ds, const char *p);
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void console_select(unsigned int index);
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/* serial ports */
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#define MAX_SERIAL_PORTS 4
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extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
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/* parallel ports */
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#define MAX_PARALLEL_PORTS 3
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extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
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struct ParallelIOArg {
371
    void *buffer;
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    int count;
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};
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/* VLANs support */
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typedef struct VLANClientState VLANClientState;
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struct VLANClientState {
380
    IOReadHandler *fd_read;
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    /* Packets may still be sent if this returns zero.  It's used to
382
       rate-limit the slirp code.  */
383
    IOCanRWHandler *fd_can_read;
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    void *opaque;
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    struct VLANClientState *next;
386
    struct VLANState *vlan;
387
    char info_str[256];
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};
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typedef struct VLANState {
391
    int id;
392
    VLANClientState *first_client;
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    struct VLANState *next;
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    unsigned int nb_guest_devs, nb_host_devs;
395
} VLANState;
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VLANState *qemu_find_vlan(int id);
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VLANClientState *qemu_new_vlan_client(VLANState *vlan,
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                                      IOReadHandler *fd_read,
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                                      IOCanRWHandler *fd_can_read,
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                                      void *opaque);
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int qemu_can_send_packet(VLANClientState *vc);
403
void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size);
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void qemu_handler_true(void *opaque);
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406
void do_info_network(void);
407

    
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/* TAP win32 */
409
int tap_win32_init(VLANState *vlan, const char *ifname);
410

    
411
/* NIC info */
412

    
413
#define MAX_NICS 8
414

    
415
typedef struct NICInfo {
416
    uint8_t macaddr[6];
417
    const char *model;
418
    VLANState *vlan;
419
} NICInfo;
420

    
421
extern int nb_nics;
422
extern NICInfo nd_table[MAX_NICS];
423

    
424
/* timers */
425

    
426
typedef struct QEMUClock QEMUClock;
427
typedef struct QEMUTimer QEMUTimer;
428
typedef void QEMUTimerCB(void *opaque);
429

    
430
/* The real time clock should be used only for stuff which does not
431
   change the virtual machine state, as it is run even if the virtual
432
   machine is stopped. The real time clock has a frequency of 1000
433
   Hz. */
434
extern QEMUClock *rt_clock;
435

    
436
/* The virtual clock is only run during the emulation. It is stopped
437
   when the virtual machine is stopped. Virtual timers use a high
438
   precision clock, usually cpu cycles (use ticks_per_sec). */
439
extern QEMUClock *vm_clock;
440

    
441
int64_t qemu_get_clock(QEMUClock *clock);
442

    
443
QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
444
void qemu_free_timer(QEMUTimer *ts);
445
void qemu_del_timer(QEMUTimer *ts);
446
void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
447
int qemu_timer_pending(QEMUTimer *ts);
448

    
449
extern int64_t ticks_per_sec;
450

    
451
int64_t cpu_get_ticks(void);
452
void cpu_enable_ticks(void);
453
void cpu_disable_ticks(void);
454

    
455
/* VM Load/Save */
456

    
457
typedef struct QEMUFile QEMUFile;
458

    
459
QEMUFile *qemu_fopen(const char *filename, const char *mode);
460
void qemu_fflush(QEMUFile *f);
461
void qemu_fclose(QEMUFile *f);
462
void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
463
void qemu_put_byte(QEMUFile *f, int v);
464
void qemu_put_be16(QEMUFile *f, unsigned int v);
465
void qemu_put_be32(QEMUFile *f, unsigned int v);
466
void qemu_put_be64(QEMUFile *f, uint64_t v);
467
int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
468
int qemu_get_byte(QEMUFile *f);
469
unsigned int qemu_get_be16(QEMUFile *f);
470
unsigned int qemu_get_be32(QEMUFile *f);
471
uint64_t qemu_get_be64(QEMUFile *f);
472

    
473
static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv)
474
{
475
    qemu_put_be64(f, *pv);
476
}
477

    
478
static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv)
479
{
480
    qemu_put_be32(f, *pv);
481
}
482

    
483
static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv)
484
{
485
    qemu_put_be16(f, *pv);
486
}
487

    
488
static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv)
489
{
490
    qemu_put_byte(f, *pv);
491
}
492

    
493
static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv)
494
{
495
    *pv = qemu_get_be64(f);
496
}
497

    
498
static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv)
499
{
500
    *pv = qemu_get_be32(f);
501
}
502

    
503
static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv)
504
{
505
    *pv = qemu_get_be16(f);
506
}
507

    
508
static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
509
{
510
    *pv = qemu_get_byte(f);
511
}
512

    
513
#if TARGET_LONG_BITS == 64
514
#define qemu_put_betl qemu_put_be64
515
#define qemu_get_betl qemu_get_be64
516
#define qemu_put_betls qemu_put_be64s
517
#define qemu_get_betls qemu_get_be64s
518
#else
519
#define qemu_put_betl qemu_put_be32
520
#define qemu_get_betl qemu_get_be32
521
#define qemu_put_betls qemu_put_be32s
522
#define qemu_get_betls qemu_get_be32s
523
#endif
524

    
525
int64_t qemu_ftell(QEMUFile *f);
526
int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
527

    
528
typedef void SaveStateHandler(QEMUFile *f, void *opaque);
529
typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
530

    
531
int register_savevm(const char *idstr,
532
                    int instance_id,
533
                    int version_id,
534
                    SaveStateHandler *save_state,
535
                    LoadStateHandler *load_state,
536
                    void *opaque);
537
void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
538
void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
539

    
540
void cpu_save(QEMUFile *f, void *opaque);
541
int cpu_load(QEMUFile *f, void *opaque, int version_id);
542

    
543
void do_savevm(const char *name);
544
void do_loadvm(const char *name);
545
void do_delvm(const char *name);
546
void do_info_snapshots(void);
547

    
548
/* bottom halves */
549
typedef void QEMUBHFunc(void *opaque);
550

    
551
QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque);
552
void qemu_bh_schedule(QEMUBH *bh);
553
void qemu_bh_cancel(QEMUBH *bh);
554
void qemu_bh_delete(QEMUBH *bh);
555
int qemu_bh_poll(void);
556

    
557
/* block.c */
558
typedef struct BlockDriverState BlockDriverState;
559
typedef struct BlockDriver BlockDriver;
560

    
561
extern BlockDriver bdrv_raw;
562
extern BlockDriver bdrv_host_device;
563
extern BlockDriver bdrv_cow;
564
extern BlockDriver bdrv_qcow;
565
extern BlockDriver bdrv_vmdk;
566
extern BlockDriver bdrv_cloop;
567
extern BlockDriver bdrv_dmg;
568
extern BlockDriver bdrv_bochs;
569
extern BlockDriver bdrv_vpc;
570
extern BlockDriver bdrv_vvfat;
571
extern BlockDriver bdrv_qcow2;
572
extern BlockDriver bdrv_parallels;
573

    
574
typedef struct BlockDriverInfo {
575
    /* in bytes, 0 if irrelevant */
576
    int cluster_size;
577
    /* offset at which the VM state can be saved (0 if not possible) */
578
    int64_t vm_state_offset;
579
} BlockDriverInfo;
580

    
581
typedef struct QEMUSnapshotInfo {
582
    char id_str[128]; /* unique snapshot id */
583
    /* the following fields are informative. They are not needed for
584
       the consistency of the snapshot */
585
    char name[256]; /* user choosen name */
586
    uint32_t vm_state_size; /* VM state info size */
587
    uint32_t date_sec; /* UTC date of the snapshot */
588
    uint32_t date_nsec;
589
    uint64_t vm_clock_nsec; /* VM clock relative to boot */
590
} QEMUSnapshotInfo;
591

    
592
#define BDRV_O_RDONLY      0x0000
593
#define BDRV_O_RDWR        0x0002
594
#define BDRV_O_ACCESS      0x0003
595
#define BDRV_O_CREAT       0x0004 /* create an empty file */
596
#define BDRV_O_SNAPSHOT    0x0008 /* open the file read only and save writes in a snapshot */
597
#define BDRV_O_FILE        0x0010 /* open as a raw file (do not try to
598
                                     use a disk image format on top of
599
                                     it (default for
600
                                     bdrv_file_open()) */
601

    
602
void bdrv_init(void);
603
BlockDriver *bdrv_find_format(const char *format_name);
604
int bdrv_create(BlockDriver *drv,
605
                const char *filename, int64_t size_in_sectors,
606
                const char *backing_file, int flags);
607
BlockDriverState *bdrv_new(const char *device_name);
608
void bdrv_delete(BlockDriverState *bs);
609
int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags);
610
int bdrv_open(BlockDriverState *bs, const char *filename, int flags);
611
int bdrv_open2(BlockDriverState *bs, const char *filename, int flags,
612
               BlockDriver *drv);
613
void bdrv_close(BlockDriverState *bs);
614
int bdrv_read(BlockDriverState *bs, int64_t sector_num,
615
              uint8_t *buf, int nb_sectors);
616
int bdrv_write(BlockDriverState *bs, int64_t sector_num,
617
               const uint8_t *buf, int nb_sectors);
618
int bdrv_pread(BlockDriverState *bs, int64_t offset,
619
               void *buf, int count);
620
int bdrv_pwrite(BlockDriverState *bs, int64_t offset,
621
                const void *buf, int count);
622
int bdrv_truncate(BlockDriverState *bs, int64_t offset);
623
int64_t bdrv_getlength(BlockDriverState *bs);
624
void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
625
int bdrv_commit(BlockDriverState *bs);
626
void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size);
627
/* async block I/O */
628
typedef struct BlockDriverAIOCB BlockDriverAIOCB;
629
typedef void BlockDriverCompletionFunc(void *opaque, int ret);
630

    
631
BlockDriverAIOCB *bdrv_aio_read(BlockDriverState *bs, int64_t sector_num,
632
                                uint8_t *buf, int nb_sectors,
633
                                BlockDriverCompletionFunc *cb, void *opaque);
634
BlockDriverAIOCB *bdrv_aio_write(BlockDriverState *bs, int64_t sector_num,
635
                                 const uint8_t *buf, int nb_sectors,
636
                                 BlockDriverCompletionFunc *cb, void *opaque);
637
void bdrv_aio_cancel(BlockDriverAIOCB *acb);
638

    
639
void qemu_aio_init(void);
640
void qemu_aio_poll(void);
641
void qemu_aio_flush(void);
642
void qemu_aio_wait_start(void);
643
void qemu_aio_wait(void);
644
void qemu_aio_wait_end(void);
645

    
646
int qemu_key_check(BlockDriverState *bs, const char *name);
647

    
648
/* Ensure contents are flushed to disk.  */
649
void bdrv_flush(BlockDriverState *bs);
650

    
651
#define BDRV_TYPE_HD     0
652
#define BDRV_TYPE_CDROM  1
653
#define BDRV_TYPE_FLOPPY 2
654
#define BIOS_ATA_TRANSLATION_AUTO   0
655
#define BIOS_ATA_TRANSLATION_NONE   1
656
#define BIOS_ATA_TRANSLATION_LBA    2
657
#define BIOS_ATA_TRANSLATION_LARGE  3
658
#define BIOS_ATA_TRANSLATION_RECHS  4
659

    
660
void bdrv_set_geometry_hint(BlockDriverState *bs,
661
                            int cyls, int heads, int secs);
662
void bdrv_set_type_hint(BlockDriverState *bs, int type);
663
void bdrv_set_translation_hint(BlockDriverState *bs, int translation);
664
void bdrv_get_geometry_hint(BlockDriverState *bs,
665
                            int *pcyls, int *pheads, int *psecs);
666
int bdrv_get_type_hint(BlockDriverState *bs);
667
int bdrv_get_translation_hint(BlockDriverState *bs);
668
int bdrv_is_removable(BlockDriverState *bs);
669
int bdrv_is_read_only(BlockDriverState *bs);
670
int bdrv_is_inserted(BlockDriverState *bs);
671
int bdrv_media_changed(BlockDriverState *bs);
672
int bdrv_is_locked(BlockDriverState *bs);
673
void bdrv_set_locked(BlockDriverState *bs, int locked);
674
void bdrv_eject(BlockDriverState *bs, int eject_flag);
675
void bdrv_set_change_cb(BlockDriverState *bs,
676
                        void (*change_cb)(void *opaque), void *opaque);
677
void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size);
678
void bdrv_info(void);
679
BlockDriverState *bdrv_find(const char *name);
680
void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque);
681
int bdrv_is_encrypted(BlockDriverState *bs);
682
int bdrv_set_key(BlockDriverState *bs, const char *key);
683
void bdrv_iterate_format(void (*it)(void *opaque, const char *name),
684
                         void *opaque);
685
const char *bdrv_get_device_name(BlockDriverState *bs);
686
int bdrv_write_compressed(BlockDriverState *bs, int64_t sector_num,
687
                          const uint8_t *buf, int nb_sectors);
688
int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi);
689

    
690
void bdrv_get_backing_filename(BlockDriverState *bs,
691
                               char *filename, int filename_size);
692
int bdrv_snapshot_create(BlockDriverState *bs,
693
                         QEMUSnapshotInfo *sn_info);
694
int bdrv_snapshot_goto(BlockDriverState *bs,
695
                       const char *snapshot_id);
696
int bdrv_snapshot_delete(BlockDriverState *bs, const char *snapshot_id);
697
int bdrv_snapshot_list(BlockDriverState *bs,
698
                       QEMUSnapshotInfo **psn_info);
699
char *bdrv_snapshot_dump(char *buf, int buf_size, QEMUSnapshotInfo *sn);
700

    
701
char *get_human_readable_size(char *buf, int buf_size, int64_t size);
702
int path_is_absolute(const char *path);
703
void path_combine(char *dest, int dest_size,
704
                  const char *base_path,
705
                  const char *filename);
706

    
707
#ifndef QEMU_TOOL
708

    
709
typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size,
710
                                 int boot_device,
711
             DisplayState *ds, const char **fd_filename, int snapshot,
712
             const char *kernel_filename, const char *kernel_cmdline,
713
             const char *initrd_filename, const char *cpu_model);
714

    
715
typedef struct QEMUMachine {
716
    const char *name;
717
    const char *desc;
718
    QEMUMachineInitFunc *init;
719
    struct QEMUMachine *next;
720
} QEMUMachine;
721

    
722
int qemu_register_machine(QEMUMachine *m);
723

    
724
typedef void SetIRQFunc(void *opaque, int irq_num, int level);
725

    
726
#if defined(TARGET_PPC)
727
void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
728
#endif
729

    
730
#if defined(TARGET_MIPS)
731
void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
732
#endif
733

    
734
#include "hw/irq.h"
735

    
736
/* ISA bus */
737

    
738
extern target_phys_addr_t isa_mem_base;
739

    
740
typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
741
typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
742

    
743
int register_ioport_read(int start, int length, int size,
744
                         IOPortReadFunc *func, void *opaque);
745
int register_ioport_write(int start, int length, int size,
746
                          IOPortWriteFunc *func, void *opaque);
747
void isa_unassign_ioport(int start, int length);
748

    
749
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
750

    
751
/* PCI bus */
752

    
753
extern target_phys_addr_t pci_mem_base;
754

    
755
typedef struct PCIBus PCIBus;
756
typedef struct PCIDevice PCIDevice;
757

    
758
typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
759
                                uint32_t address, uint32_t data, int len);
760
typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
761
                                   uint32_t address, int len);
762
typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
763
                                uint32_t addr, uint32_t size, int type);
764

    
765
#define PCI_ADDRESS_SPACE_MEM                0x00
766
#define PCI_ADDRESS_SPACE_IO                0x01
767
#define PCI_ADDRESS_SPACE_MEM_PREFETCH        0x08
768

    
769
typedef struct PCIIORegion {
770
    uint32_t addr; /* current PCI mapping address. -1 means not mapped */
771
    uint32_t size;
772
    uint8_t type;
773
    PCIMapIORegionFunc *map_func;
774
} PCIIORegion;
775

    
776
#define PCI_ROM_SLOT 6
777
#define PCI_NUM_REGIONS 7
778

    
779
#define PCI_DEVICES_MAX 64
780

    
781
#define PCI_VENDOR_ID                0x00        /* 16 bits */
782
#define PCI_DEVICE_ID                0x02        /* 16 bits */
783
#define PCI_COMMAND                0x04        /* 16 bits */
784
#define  PCI_COMMAND_IO                0x1        /* Enable response in I/O space */
785
#define  PCI_COMMAND_MEMORY        0x2        /* Enable response in Memory space */
786
#define PCI_CLASS_DEVICE        0x0a    /* Device class */
787
#define PCI_INTERRUPT_LINE        0x3c        /* 8 bits */
788
#define PCI_INTERRUPT_PIN        0x3d        /* 8 bits */
789
#define PCI_MIN_GNT                0x3e        /* 8 bits */
790
#define PCI_MAX_LAT                0x3f        /* 8 bits */
791

    
792
struct PCIDevice {
793
    /* PCI config space */
794
    uint8_t config[256];
795

    
796
    /* the following fields are read only */
797
    PCIBus *bus;
798
    int devfn;
799
    char name[64];
800
    PCIIORegion io_regions[PCI_NUM_REGIONS];
801
   
802
    /* do not access the following fields */
803
    PCIConfigReadFunc *config_read;
804
    PCIConfigWriteFunc *config_write;
805
    /* ??? This is a PC-specific hack, and should be removed.  */
806
    int irq_index;
807

    
808
    /* IRQ objects for the INTA-INTD pins.  */
809
    qemu_irq *irq;
810

    
811
    /* Current IRQ levels.  Used internally by the generic PCI code.  */
812
    int irq_state[4];
813
};
814

    
815
PCIDevice *pci_register_device(PCIBus *bus, const char *name,
816
                               int instance_size, int devfn,
817
                               PCIConfigReadFunc *config_read,
818
                               PCIConfigWriteFunc *config_write);
819

    
820
void pci_register_io_region(PCIDevice *pci_dev, int region_num,
821
                            uint32_t size, int type,
822
                            PCIMapIORegionFunc *map_func);
823

    
824
uint32_t pci_default_read_config(PCIDevice *d,
825
                                 uint32_t address, int len);
826
void pci_default_write_config(PCIDevice *d,
827
                              uint32_t address, uint32_t val, int len);
828
void pci_device_save(PCIDevice *s, QEMUFile *f);
829
int pci_device_load(PCIDevice *s, QEMUFile *f);
830

    
831
typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
832
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
833
PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
834
                         qemu_irq *pic, int devfn_min, int nirq);
835

    
836
void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
837
void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
838
uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
839
int pci_bus_num(PCIBus *s);
840
void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
841

    
842
void pci_info(void);
843
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
844
                        pci_map_irq_fn map_irq, const char *name);
845

    
846
/* prep_pci.c */
847
PCIBus *pci_prep_init(qemu_irq *pic);
848

    
849
/* grackle_pci.c */
850
PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic);
851

    
852
/* unin_pci.c */
853
PCIBus *pci_pmac_init(qemu_irq *pic);
854

    
855
/* apb_pci.c */
856
PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base,
857
                     qemu_irq *pic);
858

    
859
PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview);
860

    
861
/* piix_pci.c */
862
PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
863
void i440fx_set_smm(PCIDevice *d, int val);
864
int piix3_init(PCIBus *bus, int devfn);
865
void i440fx_init_memory_mappings(PCIDevice *d);
866

    
867
int piix4_init(PCIBus *bus, int devfn);
868

    
869
/* openpic.c */
870
/* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
871
enum {
872
    OPENPIC_OUTPUT_INT = 0, /* IRQ                       */
873
    OPENPIC_OUTPUT_CINT,    /* critical IRQ              */
874
    OPENPIC_OUTPUT_MCK,     /* Machine check event       */
875
    OPENPIC_OUTPUT_DEBUG,   /* Inconditional debug event */
876
    OPENPIC_OUTPUT_RESET,   /* Core reset event          */
877
    OPENPIC_OUTPUT_NB,
878
};
879
qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
880
                        qemu_irq **irqs, qemu_irq irq_out);
881

    
882
/* heathrow_pic.c */
883
qemu_irq *heathrow_pic_init(int *pmem_index);
884

    
885
/* gt64xxx.c */
886
PCIBus *pci_gt64120_init(qemu_irq *pic);
887

    
888
#ifdef HAS_AUDIO
889
struct soundhw {
890
    const char *name;
891
    const char *descr;
892
    int enabled;
893
    int isa;
894
    union {
895
        int (*init_isa) (AudioState *s, qemu_irq *pic);
896
        int (*init_pci) (PCIBus *bus, AudioState *s);
897
    } init;
898
};
899

    
900
extern struct soundhw soundhw[];
901
#endif
902

    
903
/* vga.c */
904

    
905
#ifndef TARGET_SPARC
906
#define VGA_RAM_SIZE (8192 * 1024)
907
#else
908
#define VGA_RAM_SIZE (9 * 1024 * 1024)
909
#endif
910

    
911
struct DisplayState {
912
    uint8_t *data;
913
    int linesize;
914
    int depth;
915
    int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */
916
    int width;
917
    int height;
918
    void *opaque;
919
    QEMUTimer *gui_timer;
920

    
921
    void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h);
922
    void (*dpy_resize)(struct DisplayState *s, int w, int h);
923
    void (*dpy_refresh)(struct DisplayState *s);
924
    void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y,
925
                     int dst_x, int dst_y, int w, int h);
926
    void (*dpy_fill)(struct DisplayState *s, int x, int y,
927
                     int w, int h, uint32_t c);
928
    void (*mouse_set)(int x, int y, int on);
929
    void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y,
930
                          uint8_t *image, uint8_t *mask);
931
};
932

    
933
static inline void dpy_update(DisplayState *s, int x, int y, int w, int h)
934
{
935
    s->dpy_update(s, x, y, w, h);
936
}
937

    
938
static inline void dpy_resize(DisplayState *s, int w, int h)
939
{
940
    s->dpy_resize(s, w, h);
941
}
942

    
943
int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
944
                 unsigned long vga_ram_offset, int vga_ram_size);
945
int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
946
                 unsigned long vga_ram_offset, int vga_ram_size,
947
                 unsigned long vga_bios_offset, int vga_bios_size);
948
int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
949
                    unsigned long vga_ram_offset, int vga_ram_size,
950
                    target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
951
                    int it_shift);
952

    
953
/* cirrus_vga.c */
954
void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
955
                         unsigned long vga_ram_offset, int vga_ram_size);
956
void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
957
                         unsigned long vga_ram_offset, int vga_ram_size);
958

    
959
/* vmware_vga.c */
960
void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
961
                     unsigned long vga_ram_offset, int vga_ram_size);
962

    
963
/* sdl.c */
964
void sdl_display_init(DisplayState *ds, int full_screen, int no_frame);
965

    
966
/* cocoa.m */
967
void cocoa_display_init(DisplayState *ds, int full_screen);
968

    
969
/* vnc.c */
970
void vnc_display_init(DisplayState *ds);
971
void vnc_display_close(DisplayState *ds);
972
int vnc_display_open(DisplayState *ds, const char *display);
973
int vnc_display_password(DisplayState *ds, const char *password);
974
void do_info_vnc(void);
975

    
976
/* x_keymap.c */
977
extern uint8_t _translate_keycode(const int key);
978

    
979
/* ide.c */
980
#define MAX_DISKS 4
981

    
982
extern BlockDriverState *bs_table[MAX_DISKS + 1];
983
extern BlockDriverState *sd_bdrv;
984
extern BlockDriverState *mtd_bdrv;
985

    
986
void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
987
                  BlockDriverState *hd0, BlockDriverState *hd1);
988
void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
989
                         int secondary_ide_enabled);
990
void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
991
                        qemu_irq *pic);
992
void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
993
                        qemu_irq *pic);
994
int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq);
995

    
996
/* cdrom.c */
997
int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track);
998
int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num);
999

    
1000
/* ds1225y.c */
1001
typedef struct ds1225y_t ds1225y_t;
1002
ds1225y_t *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
1003

    
1004
/* es1370.c */
1005
int es1370_init (PCIBus *bus, AudioState *s);
1006

    
1007
/* sb16.c */
1008
int SB16_init (AudioState *s, qemu_irq *pic);
1009

    
1010
/* adlib.c */
1011
int Adlib_init (AudioState *s, qemu_irq *pic);
1012

    
1013
/* gus.c */
1014
int GUS_init (AudioState *s, qemu_irq *pic);
1015

    
1016
/* dma.c */
1017
typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size);
1018
int DMA_get_channel_mode (int nchan);
1019
int DMA_read_memory (int nchan, void *buf, int pos, int size);
1020
int DMA_write_memory (int nchan, void *buf, int pos, int size);
1021
void DMA_hold_DREQ (int nchan);
1022
void DMA_release_DREQ (int nchan);
1023
void DMA_schedule(int nchan);
1024
void DMA_run (void);
1025
void DMA_init (int high_page_enable);
1026
void DMA_register_channel (int nchan,
1027
                           DMA_transfer_handler transfer_handler,
1028
                           void *opaque);
1029
/* fdc.c */
1030
#define MAX_FD 2
1031
extern BlockDriverState *fd_table[MAX_FD];
1032

    
1033
typedef struct fdctrl_t fdctrl_t;
1034

    
1035
fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
1036
                       target_phys_addr_t io_base,
1037
                       BlockDriverState **fds);
1038
int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
1039

    
1040
/* eepro100.c */
1041

    
1042
void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
1043
void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
1044
void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
1045

    
1046
/* ne2000.c */
1047

    
1048
void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
1049
void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
1050

    
1051
/* rtl8139.c */
1052

    
1053
void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
1054

    
1055
/* pcnet.c */
1056

    
1057
void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
1058
void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
1059
                qemu_irq irq, qemu_irq *reset);
1060

    
1061
/* vmmouse.c */
1062
void *vmmouse_init(void *m);
1063

    
1064
/* vmport.c */
1065
#ifdef TARGET_I386
1066
void vmport_init(CPUState *env);
1067
void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
1068
#endif
1069

    
1070
/* pckbd.c */
1071

    
1072
void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
1073
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
1074
                   target_phys_addr_t base, int it_shift);
1075

    
1076
/* mc146818rtc.c */
1077

    
1078
typedef struct RTCState RTCState;
1079

    
1080
RTCState *rtc_init(int base, qemu_irq irq);
1081
RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
1082
void rtc_set_memory(RTCState *s, int addr, int val);
1083
void rtc_set_date(RTCState *s, const struct tm *tm);
1084

    
1085
/* serial.c */
1086

    
1087
typedef struct SerialState SerialState;
1088
SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
1089
SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
1090
                             qemu_irq irq, CharDriverState *chr,
1091
                             int ioregister);
1092
uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
1093
void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
1094
uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
1095
void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
1096
uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
1097
void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
1098

    
1099
/* parallel.c */
1100

    
1101
typedef struct ParallelState ParallelState;
1102
ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
1103
ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
1104

    
1105
/* i8259.c */
1106

    
1107
typedef struct PicState2 PicState2;
1108
extern PicState2 *isa_pic;
1109
void pic_set_irq(int irq, int level);
1110
void pic_set_irq_new(void *opaque, int irq, int level);
1111
qemu_irq *i8259_init(qemu_irq parent_irq);
1112
void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
1113
                          void *alt_irq_opaque);
1114
int pic_read_irq(PicState2 *s);
1115
void pic_update_irq(PicState2 *s);
1116
uint32_t pic_intack_read(PicState2 *s);
1117
void pic_info(void);
1118
void irq_info(void);
1119

    
1120
/* APIC */
1121
typedef struct IOAPICState IOAPICState;
1122

    
1123
int apic_init(CPUState *env);
1124
int apic_get_interrupt(CPUState *env);
1125
IOAPICState *ioapic_init(void);
1126
void ioapic_set_irq(void *opaque, int vector, int level);
1127

    
1128
/* i8254.c */
1129

    
1130
#define PIT_FREQ 1193182
1131

    
1132
typedef struct PITState PITState;
1133

    
1134
PITState *pit_init(int base, qemu_irq irq);
1135
void pit_set_gate(PITState *pit, int channel, int val);
1136
int pit_get_gate(PITState *pit, int channel);
1137
int pit_get_initial_count(PITState *pit, int channel);
1138
int pit_get_mode(PITState *pit, int channel);
1139
int pit_get_out(PITState *pit, int channel, int64_t current_time);
1140

    
1141
/* jazz_led.c */
1142
extern void jazz_led_init(DisplayState *ds, target_phys_addr_t base);
1143

    
1144
/* pcspk.c */
1145
void pcspk_init(PITState *);
1146
int pcspk_audio_init(AudioState *, qemu_irq *pic);
1147

    
1148
#include "hw/i2c.h"
1149

    
1150
#include "hw/smbus.h"
1151

    
1152
/* acpi.c */
1153
extern int acpi_enabled;
1154
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
1155
void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
1156
void acpi_bios_init(void);
1157

    
1158
/* pc.c */
1159
extern QEMUMachine pc_machine;
1160
extern QEMUMachine isapc_machine;
1161
extern int fd_bootchk;
1162

    
1163
void ioport_set_a20(int enable);
1164
int ioport_get_a20(void);
1165

    
1166
/* ppc.c */
1167
extern QEMUMachine prep_machine;
1168
extern QEMUMachine core99_machine;
1169
extern QEMUMachine heathrow_machine;
1170
extern QEMUMachine ref405ep_machine;
1171
extern QEMUMachine taihu_machine;
1172

    
1173
/* mips_r4k.c */
1174
extern QEMUMachine mips_machine;
1175

    
1176
/* mips_malta.c */
1177
extern QEMUMachine mips_malta_machine;
1178

    
1179
/* mips_int.c */
1180
extern void cpu_mips_irq_init_cpu(CPUState *env);
1181

    
1182
/* mips_pica61.c */
1183
extern QEMUMachine mips_pica61_machine;
1184

    
1185
/* mips_timer.c */
1186
extern void cpu_mips_clock_init(CPUState *);
1187
extern void cpu_mips_irqctrl_init (void);
1188

    
1189
/* shix.c */
1190
extern QEMUMachine shix_machine;
1191

    
1192
#ifdef TARGET_PPC
1193
/* PowerPC hardware exceptions management helpers */
1194
typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
1195
typedef struct clk_setup_t clk_setup_t;
1196
struct clk_setup_t {
1197
    clk_setup_cb cb;
1198
    void *opaque;
1199
};
1200
static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
1201
{
1202
    if (clk->cb != NULL)
1203
        (*clk->cb)(clk->opaque, freq);
1204
}
1205

    
1206
clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
1207
/* Embedded PowerPC DCR management */
1208
typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn);
1209
typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val);
1210
int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
1211
                  int (*dcr_write_error)(int dcrn));
1212
int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
1213
                      dcr_read_cb drc_read, dcr_write_cb dcr_write);
1214
clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq);
1215
/* Embedded PowerPC reset */
1216
void ppc40x_core_reset (CPUState *env);
1217
void ppc40x_chip_reset (CPUState *env);
1218
void ppc40x_system_reset (CPUState *env);
1219
#endif
1220
void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
1221

    
1222
extern CPUWriteMemoryFunc *PPC_io_write[];
1223
extern CPUReadMemoryFunc *PPC_io_read[];
1224
void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
1225

    
1226
/* sun4m.c */
1227
extern QEMUMachine ss5_machine, ss10_machine;
1228

    
1229
/* iommu.c */
1230
void *iommu_init(target_phys_addr_t addr);
1231
void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
1232
                                 uint8_t *buf, int len, int is_write);
1233
static inline void sparc_iommu_memory_read(void *opaque,
1234
                                           target_phys_addr_t addr,
1235
                                           uint8_t *buf, int len)
1236
{
1237
    sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
1238
}
1239

    
1240
static inline void sparc_iommu_memory_write(void *opaque,
1241
                                            target_phys_addr_t addr,
1242
                                            uint8_t *buf, int len)
1243
{
1244
    sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
1245
}
1246

    
1247
/* tcx.c */
1248
void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
1249
              unsigned long vram_offset, int vram_size, int width, int height,
1250
              int depth);
1251

    
1252
/* slavio_intctl.c */
1253
void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
1254
                         const uint32_t *intbit_to_level,
1255
                         qemu_irq **irq, qemu_irq **cpu_irq,
1256
                         qemu_irq **parent_irq, unsigned int cputimer);
1257
void slavio_pic_info(void *opaque);
1258
void slavio_irq_info(void *opaque);
1259

    
1260
/* loader.c */
1261
int get_image_size(const char *filename);
1262
int load_image(const char *filename, uint8_t *addr);
1263
int load_elf(const char *filename, int64_t virt_to_phys_addend,
1264
             uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr);
1265
int load_aout(const char *filename, uint8_t *addr);
1266
int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
1267

    
1268
/* slavio_timer.c */
1269
void slavio_timer_init(target_phys_addr_t addr, qemu_irq irq, int mode);
1270

    
1271
/* slavio_serial.c */
1272
SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
1273
                                CharDriverState *chr1, CharDriverState *chr2);
1274
void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq);
1275

    
1276
/* slavio_misc.c */
1277
void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
1278
                       qemu_irq irq);
1279
void slavio_set_power_fail(void *opaque, int power_failing);
1280

    
1281
/* esp.c */
1282
void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1283
void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
1284
               void *dma_opaque, qemu_irq irq, qemu_irq *reset);
1285

    
1286
/* sparc32_dma.c */
1287
void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
1288
                       void *iommu, qemu_irq **dev_irq, qemu_irq **reset);
1289
void ledma_memory_read(void *opaque, target_phys_addr_t addr,
1290
                       uint8_t *buf, int len, int do_bswap);
1291
void ledma_memory_write(void *opaque, target_phys_addr_t addr,
1292
                        uint8_t *buf, int len, int do_bswap);
1293
void espdma_memory_read(void *opaque, uint8_t *buf, int len);
1294
void espdma_memory_write(void *opaque, uint8_t *buf, int len);
1295

    
1296
/* cs4231.c */
1297
void cs_init(target_phys_addr_t base, int irq, void *intctl);
1298

    
1299
/* sun4u.c */
1300
extern QEMUMachine sun4u_machine;
1301

    
1302
/* NVRAM helpers */
1303
#include "hw/m48t59.h"
1304

    
1305
void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value);
1306
uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr);
1307
void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value);
1308
uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr);
1309
void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value);
1310
uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr);
1311
void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
1312
                       const unsigned char *str, uint32_t max);
1313
int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max);
1314
void NVRAM_set_crc (m48t59_t *nvram, uint32_t addr,
1315
                    uint32_t start, uint32_t count);
1316
int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
1317
                          const unsigned char *arch,
1318
                          uint32_t RAM_size, int boot_device,
1319
                          uint32_t kernel_image, uint32_t kernel_size,
1320
                          const char *cmdline,
1321
                          uint32_t initrd_image, uint32_t initrd_size,
1322
                          uint32_t NVRAM_image,
1323
                          int width, int height, int depth);
1324

    
1325
/* adb.c */
1326

    
1327
#define MAX_ADB_DEVICES 16
1328

    
1329
#define ADB_MAX_OUT_LEN 16
1330

    
1331
typedef struct ADBDevice ADBDevice;
1332

    
1333
/* buf = NULL means polling */
1334
typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
1335
                              const uint8_t *buf, int len);
1336
typedef int ADBDeviceReset(ADBDevice *d);
1337

    
1338
struct ADBDevice {
1339
    struct ADBBusState *bus;
1340
    int devaddr;
1341
    int handler;
1342
    ADBDeviceRequest *devreq;
1343
    ADBDeviceReset *devreset;
1344
    void *opaque;
1345
};
1346

    
1347
typedef struct ADBBusState {
1348
    ADBDevice devices[MAX_ADB_DEVICES];
1349
    int nb_devices;
1350
    int poll_index;
1351
} ADBBusState;
1352

    
1353
int adb_request(ADBBusState *s, uint8_t *buf_out,
1354
                const uint8_t *buf, int len);
1355
int adb_poll(ADBBusState *s, uint8_t *buf_out);
1356

    
1357
ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
1358
                               ADBDeviceRequest *devreq,
1359
                               ADBDeviceReset *devreset,
1360
                               void *opaque);
1361
void adb_kbd_init(ADBBusState *bus);
1362
void adb_mouse_init(ADBBusState *bus);
1363

    
1364
/* cuda.c */
1365

    
1366
extern ADBBusState adb_bus;
1367
int cuda_init(qemu_irq irq);
1368

    
1369
#include "hw/usb.h"
1370

    
1371
/* usb ports of the VM */
1372

    
1373
void qemu_register_usb_port(USBPort *port, void *opaque, int index,
1374
                            usb_attachfn attach);
1375

    
1376
#define VM_USB_HUB_SIZE 8
1377

    
1378
void do_usb_add(const char *devname);
1379
void do_usb_del(const char *devname);
1380
void usb_info(void);
1381

    
1382
/* scsi-disk.c */
1383
enum scsi_reason {
1384
    SCSI_REASON_DONE, /* Command complete.  */
1385
    SCSI_REASON_DATA  /* Transfer complete, more data required.  */
1386
};
1387

    
1388
typedef struct SCSIDevice SCSIDevice;
1389
typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag,
1390
                                  uint32_t arg);
1391

    
1392
SCSIDevice *scsi_disk_init(BlockDriverState *bdrv,
1393
                           int tcq,
1394
                           scsi_completionfn completion,
1395
                           void *opaque);
1396
void scsi_disk_destroy(SCSIDevice *s);
1397

    
1398
int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
1399
/* SCSI data transfers are asynchrnonous.  However, unlike the block IO
1400
   layer the completion routine may be called directly by
1401
   scsi_{read,write}_data.  */
1402
void scsi_read_data(SCSIDevice *s, uint32_t tag);
1403
int scsi_write_data(SCSIDevice *s, uint32_t tag);
1404
void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
1405
uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag);
1406

    
1407
/* lsi53c895a.c */
1408
void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1409
void *lsi_scsi_init(PCIBus *bus, int devfn);
1410

    
1411
/* integratorcp.c */
1412
extern QEMUMachine integratorcp_machine;
1413

    
1414
/* versatilepb.c */
1415
extern QEMUMachine versatilepb_machine;
1416
extern QEMUMachine versatileab_machine;
1417

    
1418
/* realview.c */
1419
extern QEMUMachine realview_machine;
1420

    
1421
/* spitz.c */
1422
extern QEMUMachine akitapda_machine;
1423
extern QEMUMachine spitzpda_machine;
1424
extern QEMUMachine borzoipda_machine;
1425
extern QEMUMachine terrierpda_machine;
1426

    
1427
/* palm.c */
1428
extern QEMUMachine palmte_machine;
1429

    
1430
/* ps2.c */
1431
void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
1432
void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
1433
void ps2_write_mouse(void *, int val);
1434
void ps2_write_keyboard(void *, int val);
1435
uint32_t ps2_read_data(void *);
1436
void ps2_queue(void *, int b);
1437
void ps2_keyboard_set_translation(void *opaque, int mode);
1438
void ps2_mouse_fake_event(void *opaque);
1439

    
1440
/* smc91c111.c */
1441
void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
1442

    
1443
/* pl031.c */
1444
void pl031_init(uint32_t base, qemu_irq irq);
1445

    
1446
/* pl110.c */
1447
void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq, int);
1448

    
1449
/* pl011.c */
1450
void pl011_init(uint32_t base, qemu_irq irq, CharDriverState *chr);
1451

    
1452
/* pl050.c */
1453
void pl050_init(uint32_t base, qemu_irq irq, int is_mouse);
1454

    
1455
/* pl080.c */
1456
void *pl080_init(uint32_t base, qemu_irq irq, int nchannels);
1457

    
1458
/* pl181.c */
1459
void pl181_init(uint32_t base, BlockDriverState *bd,
1460
                qemu_irq irq0, qemu_irq irq1);
1461

    
1462
/* pl190.c */
1463
qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq);
1464

    
1465
/* arm-timer.c */
1466
void sp804_init(uint32_t base, qemu_irq irq);
1467
void icp_pit_init(uint32_t base, qemu_irq *pic, int irq);
1468

    
1469
/* arm_sysctl.c */
1470
void arm_sysctl_init(uint32_t base, uint32_t sys_id);
1471

    
1472
/* arm_gic.c */
1473
qemu_irq *arm_gic_init(uint32_t base, qemu_irq parent_irq);
1474

    
1475
/* arm_boot.c */
1476

    
1477
void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename,
1478
                     const char *kernel_cmdline, const char *initrd_filename,
1479
                     int board_id, target_phys_addr_t loader_start);
1480

    
1481
/* sh7750.c */
1482
struct SH7750State;
1483

    
1484
struct SH7750State *sh7750_init(CPUState * cpu);
1485

    
1486
typedef struct {
1487
    /* The callback will be triggered if any of the designated lines change */
1488
    uint16_t portamask_trigger;
1489
    uint16_t portbmask_trigger;
1490
    /* Return 0 if no action was taken */
1491
    int (*port_change_cb) (uint16_t porta, uint16_t portb,
1492
                           uint16_t * periph_pdtra,
1493
                           uint16_t * periph_portdira,
1494
                           uint16_t * periph_pdtrb,
1495
                           uint16_t * periph_portdirb);
1496
} sh7750_io_device;
1497

    
1498
int sh7750_register_io_device(struct SH7750State *s,
1499
                              sh7750_io_device * device);
1500
/* tc58128.c */
1501
int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
1502

    
1503
/* NOR flash devices */
1504
#define MAX_PFLASH 4
1505
extern BlockDriverState *pflash_table[MAX_PFLASH];
1506
typedef struct pflash_t pflash_t;
1507

    
1508
pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off,
1509
                           BlockDriverState *bs,
1510
                           uint32_t sector_len, int nb_blocs, int width,
1511
                           uint16_t id0, uint16_t id1,
1512
                           uint16_t id2, uint16_t id3);
1513

    
1514
/* nand.c */
1515
struct nand_flash_s;
1516
struct nand_flash_s *nand_init(int manf_id, int chip_id);
1517
void nand_done(struct nand_flash_s *s);
1518
void nand_setpins(struct nand_flash_s *s,
1519
                int cle, int ale, int ce, int wp, int gnd);
1520
void nand_getpins(struct nand_flash_s *s, int *rb);
1521
void nand_setio(struct nand_flash_s *s, uint8_t value);
1522
uint8_t nand_getio(struct nand_flash_s *s);
1523

    
1524
#define NAND_MFR_TOSHIBA        0x98
1525
#define NAND_MFR_SAMSUNG        0xec
1526
#define NAND_MFR_FUJITSU        0x04
1527
#define NAND_MFR_NATIONAL        0x8f
1528
#define NAND_MFR_RENESAS        0x07
1529
#define NAND_MFR_STMICRO        0x20
1530
#define NAND_MFR_HYNIX                0xad
1531
#define NAND_MFR_MICRON                0x2c
1532

    
1533
#include "ecc.h"
1534

    
1535
/* GPIO */
1536
typedef void (*gpio_handler_t)(int line, int level, void *opaque);
1537

    
1538
/* ads7846.c */
1539
struct ads7846_state_s;
1540
uint32_t ads7846_read(void *opaque);
1541
void ads7846_write(void *opaque, uint32_t value);
1542
struct ads7846_state_s *ads7846_init(qemu_irq penirq);
1543

    
1544
/* max111x.c */
1545
struct max111x_s;
1546
uint32_t max111x_read(void *opaque);
1547
void max111x_write(void *opaque, uint32_t value);
1548
struct max111x_s *max1110_init(qemu_irq cb);
1549
struct max111x_s *max1111_init(qemu_irq cb);
1550
void max111x_set_input(struct max111x_s *s, int line, uint8_t value);
1551

    
1552
/* PCMCIA/Cardbus */
1553

    
1554
struct pcmcia_socket_s {
1555
    qemu_irq irq;
1556
    int attached;
1557
    const char *slot_string;
1558
    const char *card_string;
1559
};
1560

    
1561
void pcmcia_socket_register(struct pcmcia_socket_s *socket);
1562
void pcmcia_socket_unregister(struct pcmcia_socket_s *socket);
1563
void pcmcia_info(void);
1564

    
1565
struct pcmcia_card_s {
1566
    void *state;
1567
    struct pcmcia_socket_s *slot;
1568
    int (*attach)(void *state);
1569
    int (*detach)(void *state);
1570
    const uint8_t *cis;
1571
    int cis_len;
1572

    
1573
    /* Only valid if attached */
1574
    uint8_t (*attr_read)(void *state, uint32_t address);
1575
    void (*attr_write)(void *state, uint32_t address, uint8_t value);
1576
    uint16_t (*common_read)(void *state, uint32_t address);
1577
    void (*common_write)(void *state, uint32_t address, uint16_t value);
1578
    uint16_t (*io_read)(void *state, uint32_t address);
1579
    void (*io_write)(void *state, uint32_t address, uint16_t value);
1580
};
1581

    
1582
#define CISTPL_DEVICE                0x01        /* 5V Device Information Tuple */
1583
#define CISTPL_NO_LINK                0x14        /* No Link Tuple */
1584
#define CISTPL_VERS_1                0x15        /* Level 1 Version Tuple */
1585
#define CISTPL_JEDEC_C                0x18        /* JEDEC ID Tuple */
1586
#define CISTPL_JEDEC_A                0x19        /* JEDEC ID Tuple */
1587
#define CISTPL_CONFIG                0x1a        /* Configuration Tuple */
1588
#define CISTPL_CFTABLE_ENTRY        0x1b        /* 16-bit PCCard Configuration */
1589
#define CISTPL_DEVICE_OC        0x1c        /* Additional Device Information */
1590
#define CISTPL_DEVICE_OA        0x1d        /* Additional Device Information */
1591
#define CISTPL_DEVICE_GEO        0x1e        /* Additional Device Information */
1592
#define CISTPL_DEVICE_GEO_A        0x1f        /* Additional Device Information */
1593
#define CISTPL_MANFID                0x20        /* Manufacture ID Tuple */
1594
#define CISTPL_FUNCID                0x21        /* Function ID Tuple */
1595
#define CISTPL_FUNCE                0x22        /* Function Extension Tuple */
1596
#define CISTPL_END                0xff        /* Tuple End */
1597
#define CISTPL_ENDMARK                0xff
1598

    
1599
/* dscm1xxxx.c */
1600
struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv);
1601

    
1602
/* ptimer.c */
1603
typedef struct ptimer_state ptimer_state;
1604
typedef void (*ptimer_cb)(void *opaque);
1605

    
1606
ptimer_state *ptimer_init(QEMUBH *bh);
1607
void ptimer_set_period(ptimer_state *s, int64_t period);
1608
void ptimer_set_freq(ptimer_state *s, uint32_t freq);
1609
void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload);
1610
uint64_t ptimer_get_count(ptimer_state *s);
1611
void ptimer_set_count(ptimer_state *s, uint64_t count);
1612
void ptimer_run(ptimer_state *s, int oneshot);
1613
void ptimer_stop(ptimer_state *s);
1614
void qemu_put_ptimer(QEMUFile *f, ptimer_state *s);
1615
void qemu_get_ptimer(QEMUFile *f, ptimer_state *s);
1616

    
1617
#include "hw/pxa.h"
1618

    
1619
#include "hw/omap.h"
1620

    
1621
/* mcf_uart.c */
1622
uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr);
1623
void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val);
1624
void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
1625
void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
1626
                      CharDriverState *chr);
1627

    
1628
/* mcf_intc.c */
1629
qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env);
1630

    
1631
/* mcf_fec.c */
1632
void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq);
1633

    
1634
/* mcf5206.c */
1635
qemu_irq *mcf5206_init(uint32_t base, CPUState *env);
1636

    
1637
/* an5206.c */
1638
extern QEMUMachine an5206_machine;
1639

    
1640
/* mcf5208.c */
1641
extern QEMUMachine mcf5208evb_machine;
1642

    
1643
#include "gdbstub.h"
1644

    
1645
#endif /* defined(QEMU_TOOL) */
1646

    
1647
/* monitor.c */
1648
void monitor_init(CharDriverState *hd, int show_banner);
1649
void term_puts(const char *str);
1650
void term_vprintf(const char *fmt, va_list ap);
1651
void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
1652
void term_print_filename(const char *filename);
1653
void term_flush(void);
1654
void term_print_help(void);
1655
void monitor_readline(const char *prompt, int is_password,
1656
                      char *buf, int buf_size);
1657

    
1658
/* readline.c */
1659
typedef void ReadLineFunc(void *opaque, const char *str);
1660

    
1661
extern int completion_index;
1662
void add_completion(const char *str);
1663
void readline_handle_byte(int ch);
1664
void readline_find_completion(const char *cmdline);
1665
const char *readline_get_history(unsigned int index);
1666
void readline_start(const char *prompt, int is_password,
1667
                    ReadLineFunc *readline_func, void *opaque);
1668

    
1669
void kqemu_record_dump(void);
1670

    
1671
#endif /* VL_H */