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/*
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 * Tiny Code Generator for QEMU
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 *
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 * Copyright (c) 2008 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "tcg.h"
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/* legacy dyngen operations */
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#include "gen-op.h"
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int gen_new_label(void);
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static inline void tcg_gen_op1(int opc, TCGv arg1)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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}
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static inline void tcg_gen_op1i(int opc, TCGArg arg1)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = arg1;
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}
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static inline void tcg_gen_op2(int opc, TCGv arg1, TCGv arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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}
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static inline void tcg_gen_op2i(int opc, TCGv arg1, TCGArg arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = arg2;
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}
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static inline void tcg_gen_op3(int opc, TCGv arg1, TCGv arg2, TCGv arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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}
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static inline void tcg_gen_op3i(int opc, TCGv arg1, TCGv arg2, TCGArg arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = arg3;
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}
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static inline void tcg_gen_op4(int opc, TCGv arg1, TCGv arg2, TCGv arg3, 
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                               TCGv arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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    *gen_opparam_ptr++ = GET_TCGV(arg4);
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}
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static inline void tcg_gen_op4i(int opc, TCGv arg1, TCGv arg2, TCGv arg3, 
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                                TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op4ii(int opc, TCGv arg1, TCGv arg2, TCGArg arg3, 
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                                 TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = arg3;
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op5(int opc, TCGv arg1, TCGv arg2, 
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                               TCGv arg3, TCGv arg4,
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                               TCGv arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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    *gen_opparam_ptr++ = GET_TCGV(arg4);
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    *gen_opparam_ptr++ = GET_TCGV(arg5);
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}
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static inline void tcg_gen_op5i(int opc, TCGv arg1, TCGv arg2, 
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                                TCGv arg3, TCGv arg4,
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                                TCGArg arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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    *gen_opparam_ptr++ = GET_TCGV(arg4);
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    *gen_opparam_ptr++ = arg5;
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}
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static inline void tcg_gen_op6(int opc, TCGv arg1, TCGv arg2, 
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                               TCGv arg3, TCGv arg4,
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                               TCGv arg5, TCGv arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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    *gen_opparam_ptr++ = GET_TCGV(arg4);
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    *gen_opparam_ptr++ = GET_TCGV(arg5);
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    *gen_opparam_ptr++ = GET_TCGV(arg6);
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}
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static inline void tcg_gen_op6ii(int opc, TCGv arg1, TCGv arg2, 
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                                 TCGv arg3, TCGv arg4,
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                                 TCGArg arg5, TCGArg arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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    *gen_opparam_ptr++ = GET_TCGV(arg4);
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    *gen_opparam_ptr++ = arg5;
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    *gen_opparam_ptr++ = arg6;
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}
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static inline void gen_set_label(int n)
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{
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    tcg_gen_op1i(INDEX_op_set_label, n);
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}
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static inline void tcg_gen_mov_i32(TCGv ret, TCGv arg)
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{
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    tcg_gen_op2(INDEX_op_mov_i32, ret, arg);
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}
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static inline void tcg_gen_movi_i32(TCGv ret, int32_t arg)
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{
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    tcg_gen_op2i(INDEX_op_movi_i32, ret, arg);
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}
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/* helper calls */
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#define TCG_HELPER_CALL_FLAGS 0
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static inline void tcg_gen_helper_0_0(void *func)
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{
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    tcg_gen_call(&tcg_ctx, 
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                 tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
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                 0, NULL, 0, NULL);
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}
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static inline void tcg_gen_helper_0_1(void *func, TCGv arg)
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{
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    tcg_gen_call(&tcg_ctx,
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                 tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
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                 0, NULL, 1, &arg);
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}
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static inline void tcg_gen_helper_0_2(void *func, TCGv arg1, TCGv arg2)
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{
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    TCGv args[2];
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    args[0] = arg1;
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    args[1] = arg2;
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    tcg_gen_call(&tcg_ctx, 
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                 tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
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                 0, NULL, 2, args);
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}
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static inline void tcg_gen_helper_1_2(void *func, TCGv ret, 
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                                      TCGv arg1, TCGv arg2)
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{
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    TCGv args[2];
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    args[0] = arg1;
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    args[1] = arg2;
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    tcg_gen_call(&tcg_ctx, 
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                 tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
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                 1, &ret, 2, args);
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}
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/* 32 bit ops */
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static inline void tcg_gen_ld8u_i32(TCGv ret, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_ld8u_i32, ret, arg2, offset);
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}
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static inline void tcg_gen_ld8s_i32(TCGv ret, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_ld8s_i32, ret, arg2, offset);
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}
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static inline void tcg_gen_ld16u_i32(TCGv ret, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_ld16u_i32, ret, arg2, offset);
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}
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static inline void tcg_gen_ld16s_i32(TCGv ret, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_ld16s_i32, ret, arg2, offset);
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}
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static inline void tcg_gen_ld_i32(TCGv ret, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_ld_i32, ret, arg2, offset);
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}
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static inline void tcg_gen_st8_i32(TCGv arg1, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_st8_i32, arg1, arg2, offset);
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}
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static inline void tcg_gen_st16_i32(TCGv arg1, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_st16_i32, arg1, arg2, offset);
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}
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static inline void tcg_gen_st_i32(TCGv arg1, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_st_i32, arg1, arg2, offset);
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}
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static inline void tcg_gen_add_i32(TCGv ret, TCGv arg1, TCGv arg2)
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{
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    tcg_gen_op3(INDEX_op_add_i32, ret, arg1, arg2);
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}
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static inline void tcg_gen_addi_i32(TCGv ret, TCGv arg1, int32_t arg2)
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{
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    tcg_gen_add_i32(ret, arg1, tcg_const_i32(arg2));
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}
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static inline void tcg_gen_sub_i32(TCGv ret, TCGv arg1, TCGv arg2)
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{
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    tcg_gen_op3(INDEX_op_sub_i32, ret, arg1, arg2);
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}
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static inline void tcg_gen_subi_i32(TCGv ret, TCGv arg1, int32_t arg2)
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{
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    tcg_gen_sub_i32(ret, arg1, tcg_const_i32(arg2));
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}
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static inline void tcg_gen_and_i32(TCGv ret, TCGv arg1, TCGv arg2)
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{
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    tcg_gen_op3(INDEX_op_and_i32, ret, arg1, arg2);
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}
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static inline void tcg_gen_andi_i32(TCGv ret, TCGv arg1, int32_t arg2)
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{
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    /* some cases can be optimized here */
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    if (arg2 == 0) {
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        tcg_gen_movi_i32(ret, 0);
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    } else if (arg2 == 0xffffffff) {
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        tcg_gen_mov_i32(ret, arg1);
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    } else {
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        tcg_gen_and_i32(ret, arg1, tcg_const_i32(arg2));
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    }
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}
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static inline void tcg_gen_or_i32(TCGv ret, TCGv arg1, TCGv arg2)
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{
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    tcg_gen_op3(INDEX_op_or_i32, ret, arg1, arg2);
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}
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static inline void tcg_gen_ori_i32(TCGv ret, TCGv arg1, int32_t arg2)
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{
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    /* some cases can be optimized here */
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    if (arg2 == 0xffffffff) {
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        tcg_gen_movi_i32(ret, 0);
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    } else if (arg2 == 0) {
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        tcg_gen_mov_i32(ret, arg1);
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    } else {
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        tcg_gen_or_i32(ret, arg1, tcg_const_i32(arg2));
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    }
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}
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static inline void tcg_gen_xor_i32(TCGv ret, TCGv arg1, TCGv arg2)
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{
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    tcg_gen_op3(INDEX_op_xor_i32, ret, arg1, arg2);
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}
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static inline void tcg_gen_xori_i32(TCGv ret, TCGv arg1, int32_t arg2)
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{
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    /* some cases can be optimized here */
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    if (arg2 == 0) {
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        tcg_gen_mov_i32(ret, arg1);
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    } else {
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        tcg_gen_xor_i32(ret, arg1, tcg_const_i32(arg2));
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    }
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}
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static inline void tcg_gen_shl_i32(TCGv ret, TCGv arg1, TCGv arg2)
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{
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    tcg_gen_op3(INDEX_op_shl_i32, ret, arg1, arg2);
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}
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static inline void tcg_gen_shli_i32(TCGv ret, TCGv arg1, int32_t arg2)
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{
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    tcg_gen_shl_i32(ret, arg1, tcg_const_i32(arg2));
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}
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static inline void tcg_gen_shr_i32(TCGv ret, TCGv arg1, TCGv arg2)
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{
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    tcg_gen_op3(INDEX_op_shr_i32, ret, arg1, arg2);
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}
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static inline void tcg_gen_shri_i32(TCGv ret, TCGv arg1, int32_t arg2)
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{
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    tcg_gen_shr_i32(ret, arg1, tcg_const_i32(arg2));
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}
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static inline void tcg_gen_sar_i32(TCGv ret, TCGv arg1, TCGv arg2)
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{
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    tcg_gen_op3(INDEX_op_sar_i32, ret, arg1, arg2);
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}
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static inline void tcg_gen_sari_i32(TCGv ret, TCGv arg1, int32_t arg2)
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{
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    tcg_gen_sar_i32(ret, arg1, tcg_const_i32(arg2));
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}
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static inline void tcg_gen_brcond_i32(int cond, TCGv arg1, TCGv arg2, 
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                                      int label_index)
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{
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    tcg_gen_op4ii(INDEX_op_brcond_i32, arg1, arg2, cond, label_index);
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}
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static inline void tcg_gen_mul_i32(TCGv ret, TCGv arg1, TCGv arg2)
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{
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    tcg_gen_op3(INDEX_op_mul_i32, ret, arg1, arg2);
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}
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#ifdef TCG_TARGET_HAS_div_i32
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static inline void tcg_gen_div_i32(TCGv ret, TCGv arg1, TCGv arg2)
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{
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    tcg_gen_op3(INDEX_op_div_i32, ret, arg1, arg2);
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}
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static inline void tcg_gen_rem_i32(TCGv ret, TCGv arg1, TCGv arg2)
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{
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    tcg_gen_op3(INDEX_op_rem_i32, ret, arg1, arg2);
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}
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static inline void tcg_gen_divu_i32(TCGv ret, TCGv arg1, TCGv arg2)
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{
371 c896fe29 bellard
    tcg_gen_op3(INDEX_op_divu_i32, ret, arg1, arg2);
372 c896fe29 bellard
}
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374 ac56dd48 pbrook
static inline void tcg_gen_remu_i32(TCGv ret, TCGv arg1, TCGv arg2)
375 c896fe29 bellard
{
376 c896fe29 bellard
    tcg_gen_op3(INDEX_op_remu_i32, ret, arg1, arg2);
377 c896fe29 bellard
}
378 c896fe29 bellard
#else
379 ac56dd48 pbrook
static inline void tcg_gen_div_i32(TCGv ret, TCGv arg1, TCGv arg2)
380 c896fe29 bellard
{
381 ac56dd48 pbrook
    TCGv t0;
382 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
383 c896fe29 bellard
    tcg_gen_sari_i32(t0, arg1, 31);
384 c896fe29 bellard
    tcg_gen_op5(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2);
385 c896fe29 bellard
}
386 c896fe29 bellard
387 ac56dd48 pbrook
static inline void tcg_gen_rem_i32(TCGv ret, TCGv arg1, TCGv arg2)
388 c896fe29 bellard
{
389 ac56dd48 pbrook
    TCGv t0;
390 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
391 c896fe29 bellard
    tcg_gen_sari_i32(t0, arg1, 31);
392 c896fe29 bellard
    tcg_gen_op5(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2);
393 c896fe29 bellard
}
394 c896fe29 bellard
395 ac56dd48 pbrook
static inline void tcg_gen_divu_i32(TCGv ret, TCGv arg1, TCGv arg2)
396 c896fe29 bellard
{
397 ac56dd48 pbrook
    TCGv t0;
398 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
399 c896fe29 bellard
    tcg_gen_movi_i32(t0, 0);
400 c896fe29 bellard
    tcg_gen_op5(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2);
401 c896fe29 bellard
}
402 c896fe29 bellard
403 ac56dd48 pbrook
static inline void tcg_gen_remu_i32(TCGv ret, TCGv arg1, TCGv arg2)
404 c896fe29 bellard
{
405 ac56dd48 pbrook
    TCGv t0;
406 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
407 c896fe29 bellard
    tcg_gen_movi_i32(t0, 0);
408 c896fe29 bellard
    tcg_gen_op5(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2);
409 c896fe29 bellard
}
410 c896fe29 bellard
#endif
411 c896fe29 bellard
412 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
413 c896fe29 bellard
414 ac56dd48 pbrook
static inline void tcg_gen_mov_i64(TCGv ret, TCGv arg)
415 c896fe29 bellard
{
416 c896fe29 bellard
    tcg_gen_mov_i32(ret, arg);
417 ac56dd48 pbrook
    tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
418 c896fe29 bellard
}
419 c896fe29 bellard
420 ac56dd48 pbrook
static inline void tcg_gen_movi_i64(TCGv ret, int64_t arg)
421 c896fe29 bellard
{
422 c896fe29 bellard
    tcg_gen_movi_i32(ret, arg);
423 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
424 c896fe29 bellard
}
425 c896fe29 bellard
426 ac56dd48 pbrook
static inline void tcg_gen_ld8u_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
427 c896fe29 bellard
{
428 c896fe29 bellard
    tcg_gen_ld8u_i32(ret, arg2, offset);
429 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
430 c896fe29 bellard
}
431 c896fe29 bellard
432 ac56dd48 pbrook
static inline void tcg_gen_ld8s_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
433 c896fe29 bellard
{
434 c896fe29 bellard
    tcg_gen_ld8s_i32(ret, arg2, offset);
435 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
436 c896fe29 bellard
}
437 c896fe29 bellard
438 ac56dd48 pbrook
static inline void tcg_gen_ld16u_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
439 c896fe29 bellard
{
440 c896fe29 bellard
    tcg_gen_ld16u_i32(ret, arg2, offset);
441 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
442 c896fe29 bellard
}
443 c896fe29 bellard
444 ac56dd48 pbrook
static inline void tcg_gen_ld16s_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
445 c896fe29 bellard
{
446 c896fe29 bellard
    tcg_gen_ld16s_i32(ret, arg2, offset);
447 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
448 c896fe29 bellard
}
449 c896fe29 bellard
450 ac56dd48 pbrook
static inline void tcg_gen_ld32u_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
451 c896fe29 bellard
{
452 c896fe29 bellard
    tcg_gen_ld_i32(ret, arg2, offset);
453 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
454 c896fe29 bellard
}
455 c896fe29 bellard
456 ac56dd48 pbrook
static inline void tcg_gen_ld32s_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
457 c896fe29 bellard
{
458 c896fe29 bellard
    tcg_gen_ld_i32(ret, arg2, offset);
459 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
460 c896fe29 bellard
}
461 c896fe29 bellard
462 ac56dd48 pbrook
static inline void tcg_gen_ld_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
463 c896fe29 bellard
{
464 c896fe29 bellard
    /* since arg2 and ret have different types, they cannot be the
465 c896fe29 bellard
       same temporary */
466 c896fe29 bellard
#ifdef TCG_TARGET_WORDS_BIGENDIAN
467 ac56dd48 pbrook
    tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset);
468 c896fe29 bellard
    tcg_gen_ld_i32(ret, arg2, offset + 4);
469 c896fe29 bellard
#else
470 c896fe29 bellard
    tcg_gen_ld_i32(ret, arg2, offset);
471 ac56dd48 pbrook
    tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
472 c896fe29 bellard
#endif
473 c896fe29 bellard
}
474 c896fe29 bellard
475 ac56dd48 pbrook
static inline void tcg_gen_st8_i64(TCGv arg1, TCGv arg2, tcg_target_long offset)
476 c896fe29 bellard
{
477 c896fe29 bellard
    tcg_gen_st8_i32(arg1, arg2, offset);
478 c896fe29 bellard
}
479 c896fe29 bellard
480 ac56dd48 pbrook
static inline void tcg_gen_st16_i64(TCGv arg1, TCGv arg2, tcg_target_long offset)
481 c896fe29 bellard
{
482 c896fe29 bellard
    tcg_gen_st16_i32(arg1, arg2, offset);
483 c896fe29 bellard
}
484 c896fe29 bellard
485 ac56dd48 pbrook
static inline void tcg_gen_st32_i64(TCGv arg1, TCGv arg2, tcg_target_long offset)
486 c896fe29 bellard
{
487 c896fe29 bellard
    tcg_gen_st_i32(arg1, arg2, offset);
488 c896fe29 bellard
}
489 c896fe29 bellard
490 ac56dd48 pbrook
static inline void tcg_gen_st_i64(TCGv arg1, TCGv arg2, tcg_target_long offset)
491 c896fe29 bellard
{
492 c896fe29 bellard
#ifdef TCG_TARGET_WORDS_BIGENDIAN
493 ac56dd48 pbrook
    tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset);
494 c896fe29 bellard
    tcg_gen_st_i32(arg1, arg2, offset + 4);
495 c896fe29 bellard
#else
496 c896fe29 bellard
    tcg_gen_st_i32(arg1, arg2, offset);
497 ac56dd48 pbrook
    tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
498 c896fe29 bellard
#endif
499 c896fe29 bellard
}
500 c896fe29 bellard
501 ac56dd48 pbrook
static inline void tcg_gen_add_i64(TCGv ret, TCGv arg1, TCGv arg2)
502 c896fe29 bellard
{
503 ac56dd48 pbrook
    tcg_gen_op6(INDEX_op_add2_i32, ret, TCGV_HIGH(ret), 
504 ac56dd48 pbrook
                arg1, TCGV_HIGH(arg1), arg2, TCGV_HIGH(arg2));
505 c896fe29 bellard
}
506 c896fe29 bellard
507 ac56dd48 pbrook
static inline void tcg_gen_addi_i64(TCGv ret, TCGv arg1, int64_t arg2)
508 c896fe29 bellard
{
509 c896fe29 bellard
    tcg_gen_add_i64(ret, arg1, tcg_const_i64(arg2));
510 c896fe29 bellard
}
511 c896fe29 bellard
512 ac56dd48 pbrook
static inline void tcg_gen_sub_i64(TCGv ret, TCGv arg1, TCGv arg2)
513 c896fe29 bellard
{
514 ac56dd48 pbrook
    tcg_gen_op6(INDEX_op_sub2_i32, ret, TCGV_HIGH(ret), 
515 ac56dd48 pbrook
                arg1, TCGV_HIGH(arg1), arg2, TCGV_HIGH(arg2));
516 c896fe29 bellard
}
517 c896fe29 bellard
518 ac56dd48 pbrook
static inline void tcg_gen_subi_i64(TCGv ret, TCGv arg1, int64_t arg2)
519 c896fe29 bellard
{
520 c896fe29 bellard
    tcg_gen_sub_i64(ret, arg1, tcg_const_i64(arg2));
521 c896fe29 bellard
}
522 c896fe29 bellard
523 ac56dd48 pbrook
static inline void tcg_gen_and_i64(TCGv ret, TCGv arg1, TCGv arg2)
524 c896fe29 bellard
{
525 c896fe29 bellard
    tcg_gen_and_i32(ret, arg1, arg2);
526 ac56dd48 pbrook
    tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
527 c896fe29 bellard
}
528 c896fe29 bellard
529 ac56dd48 pbrook
static inline void tcg_gen_andi_i64(TCGv ret, TCGv arg1, int64_t arg2)
530 c896fe29 bellard
{
531 c896fe29 bellard
    tcg_gen_andi_i32(ret, arg1, arg2);
532 ac56dd48 pbrook
    tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
533 c896fe29 bellard
}
534 c896fe29 bellard
535 ac56dd48 pbrook
static inline void tcg_gen_or_i64(TCGv ret, TCGv arg1, TCGv arg2)
536 c896fe29 bellard
{
537 c896fe29 bellard
    tcg_gen_or_i32(ret, arg1, arg2);
538 ac56dd48 pbrook
    tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
539 c896fe29 bellard
}
540 c896fe29 bellard
541 ac56dd48 pbrook
static inline void tcg_gen_ori_i64(TCGv ret, TCGv arg1, int64_t arg2)
542 c896fe29 bellard
{
543 c896fe29 bellard
    tcg_gen_ori_i32(ret, arg1, arg2);
544 ac56dd48 pbrook
    tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
545 c896fe29 bellard
}
546 c896fe29 bellard
547 ac56dd48 pbrook
static inline void tcg_gen_xor_i64(TCGv ret, TCGv arg1, TCGv arg2)
548 c896fe29 bellard
{
549 c896fe29 bellard
    tcg_gen_xor_i32(ret, arg1, arg2);
550 ac56dd48 pbrook
    tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
551 c896fe29 bellard
}
552 c896fe29 bellard
553 ac56dd48 pbrook
static inline void tcg_gen_xori_i64(TCGv ret, TCGv arg1, int64_t arg2)
554 c896fe29 bellard
{
555 c896fe29 bellard
    tcg_gen_xori_i32(ret, arg1, arg2);
556 ac56dd48 pbrook
    tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
557 c896fe29 bellard
}
558 c896fe29 bellard
559 c896fe29 bellard
/* XXX: use generic code when basic block handling is OK or CPU
560 c896fe29 bellard
   specific code (x86) */
561 ac56dd48 pbrook
static inline void tcg_gen_shl_i64(TCGv ret, TCGv arg1, TCGv arg2)
562 c896fe29 bellard
{
563 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_shl_i64, ret, arg1, arg2);
564 c896fe29 bellard
}
565 c896fe29 bellard
566 ac56dd48 pbrook
static inline void tcg_gen_shli_i64(TCGv ret, TCGv arg1, int64_t arg2)
567 c896fe29 bellard
{
568 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0);
569 c896fe29 bellard
}
570 c896fe29 bellard
571 ac56dd48 pbrook
static inline void tcg_gen_shr_i64(TCGv ret, TCGv arg1, TCGv arg2)
572 c896fe29 bellard
{
573 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_shr_i64, ret, arg1, arg2);
574 c896fe29 bellard
}
575 c896fe29 bellard
576 ac56dd48 pbrook
static inline void tcg_gen_shri_i64(TCGv ret, TCGv arg1, int64_t arg2)
577 c896fe29 bellard
{
578 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0);
579 c896fe29 bellard
}
580 c896fe29 bellard
581 ac56dd48 pbrook
static inline void tcg_gen_sar_i64(TCGv ret, TCGv arg1, TCGv arg2)
582 c896fe29 bellard
{
583 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_sar_i64, ret, arg1, arg2);
584 c896fe29 bellard
}
585 c896fe29 bellard
586 ac56dd48 pbrook
static inline void tcg_gen_sari_i64(TCGv ret, TCGv arg1, int64_t arg2)
587 c896fe29 bellard
{
588 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1);
589 c896fe29 bellard
}
590 c896fe29 bellard
591 ac56dd48 pbrook
static inline void tcg_gen_brcond_i64(int cond, TCGv arg1, TCGv arg2, 
592 c896fe29 bellard
                                      int label_index)
593 c896fe29 bellard
{
594 ac56dd48 pbrook
    tcg_gen_op6ii(INDEX_op_brcond2_i32, 
595 ac56dd48 pbrook
                  arg1, TCGV_HIGH(arg1), arg2, TCGV_HIGH(arg2),
596 ac56dd48 pbrook
                  cond, label_index);
597 c896fe29 bellard
}
598 c896fe29 bellard
599 ac56dd48 pbrook
static inline void tcg_gen_mul_i64(TCGv ret, TCGv arg1, TCGv arg2)
600 c896fe29 bellard
{
601 ac56dd48 pbrook
    TCGv t0, t1;
602 c896fe29 bellard
    
603 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I64);
604 c896fe29 bellard
    t1 = tcg_temp_new(TCG_TYPE_I32);
605 c896fe29 bellard
606 ac56dd48 pbrook
    tcg_gen_op4(INDEX_op_mulu2_i32, t0, TCGV_HIGH(t0), arg1, arg2);
607 c896fe29 bellard
    
608 ac56dd48 pbrook
    tcg_gen_mul_i32(t1, arg1, TCGV_HIGH(arg2));
609 ac56dd48 pbrook
    tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
610 ac56dd48 pbrook
    tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), arg2);
611 ac56dd48 pbrook
    tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
612 c896fe29 bellard
    
613 c896fe29 bellard
    tcg_gen_mov_i64(ret, t0);
614 c896fe29 bellard
}
615 c896fe29 bellard
616 ac56dd48 pbrook
static inline void tcg_gen_div_i64(TCGv ret, TCGv arg1, TCGv arg2)
617 c896fe29 bellard
{
618 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_div_i64, ret, arg1, arg2);
619 c896fe29 bellard
}
620 c896fe29 bellard
621 ac56dd48 pbrook
static inline void tcg_gen_rem_i64(TCGv ret, TCGv arg1, TCGv arg2)
622 c896fe29 bellard
{
623 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_rem_i64, ret, arg1, arg2);
624 c896fe29 bellard
}
625 c896fe29 bellard
626 ac56dd48 pbrook
static inline void tcg_gen_divu_i64(TCGv ret, TCGv arg1, TCGv arg2)
627 c896fe29 bellard
{
628 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_divu_i64, ret, arg1, arg2);
629 c896fe29 bellard
}
630 c896fe29 bellard
631 ac56dd48 pbrook
static inline void tcg_gen_remu_i64(TCGv ret, TCGv arg1, TCGv arg2)
632 c896fe29 bellard
{
633 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_remu_i64, ret, arg1, arg2);
634 c896fe29 bellard
}
635 c896fe29 bellard
636 c896fe29 bellard
#else
637 c896fe29 bellard
638 ac56dd48 pbrook
static inline void tcg_gen_mov_i64(TCGv ret, TCGv arg)
639 c896fe29 bellard
{
640 c896fe29 bellard
    tcg_gen_op2(INDEX_op_mov_i64, ret, arg);
641 c896fe29 bellard
}
642 c896fe29 bellard
643 ac56dd48 pbrook
static inline void tcg_gen_movi_i64(TCGv ret, int64_t arg)
644 c896fe29 bellard
{
645 ac56dd48 pbrook
    tcg_gen_op2i(INDEX_op_movi_i64, ret, arg);
646 c896fe29 bellard
}
647 c896fe29 bellard
648 ac56dd48 pbrook
static inline void tcg_gen_ld8u_i64(TCGv ret, TCGv arg2,
649 ac56dd48 pbrook
                                    tcg_target_long offset)
650 c896fe29 bellard
{
651 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld8u_i64, ret, arg2, offset);
652 c896fe29 bellard
}
653 c896fe29 bellard
654 ac56dd48 pbrook
static inline void tcg_gen_ld8s_i64(TCGv ret, TCGv arg2,
655 ac56dd48 pbrook
                                    tcg_target_long offset)
656 c896fe29 bellard
{
657 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld8s_i64, ret, arg2, offset);
658 c896fe29 bellard
}
659 c896fe29 bellard
660 ac56dd48 pbrook
static inline void tcg_gen_ld16u_i64(TCGv ret, TCGv arg2,
661 ac56dd48 pbrook
                                     tcg_target_long offset)
662 c896fe29 bellard
{
663 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld16u_i64, ret, arg2, offset);
664 c896fe29 bellard
}
665 c896fe29 bellard
666 ac56dd48 pbrook
static inline void tcg_gen_ld16s_i64(TCGv ret, TCGv arg2,
667 ac56dd48 pbrook
                                     tcg_target_long offset)
668 c896fe29 bellard
{
669 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld16s_i64, ret, arg2, offset);
670 c896fe29 bellard
}
671 c896fe29 bellard
672 ac56dd48 pbrook
static inline void tcg_gen_ld32u_i64(TCGv ret, TCGv arg2,
673 ac56dd48 pbrook
                                     tcg_target_long offset)
674 c896fe29 bellard
{
675 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld32u_i64, ret, arg2, offset);
676 c896fe29 bellard
}
677 c896fe29 bellard
678 ac56dd48 pbrook
static inline void tcg_gen_ld32s_i64(TCGv ret, TCGv arg2,
679 ac56dd48 pbrook
                                     tcg_target_long offset)
680 c896fe29 bellard
{
681 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld32s_i64, ret, arg2, offset);
682 c896fe29 bellard
}
683 c896fe29 bellard
684 ac56dd48 pbrook
static inline void tcg_gen_ld_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
685 c896fe29 bellard
{
686 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld_i64, ret, arg2, offset);
687 c896fe29 bellard
}
688 c896fe29 bellard
689 ac56dd48 pbrook
static inline void tcg_gen_st8_i64(TCGv arg1, TCGv arg2,
690 ac56dd48 pbrook
                                   tcg_target_long offset)
691 c896fe29 bellard
{
692 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_st8_i64, arg1, arg2, offset);
693 c896fe29 bellard
}
694 c896fe29 bellard
695 ac56dd48 pbrook
static inline void tcg_gen_st16_i64(TCGv arg1, TCGv arg2,
696 ac56dd48 pbrook
                                    tcg_target_long offset)
697 c896fe29 bellard
{
698 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_st16_i64, arg1, arg2, offset);
699 c896fe29 bellard
}
700 c896fe29 bellard
701 ac56dd48 pbrook
static inline void tcg_gen_st32_i64(TCGv arg1, TCGv arg2,
702 ac56dd48 pbrook
                                    tcg_target_long offset)
703 c896fe29 bellard
{
704 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_st32_i64, arg1, arg2, offset);
705 c896fe29 bellard
}
706 c896fe29 bellard
707 ac56dd48 pbrook
static inline void tcg_gen_st_i64(TCGv arg1, TCGv arg2, tcg_target_long offset)
708 c896fe29 bellard
{
709 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_st_i64, arg1, arg2, offset);
710 c896fe29 bellard
}
711 c896fe29 bellard
712 ac56dd48 pbrook
static inline void tcg_gen_add_i64(TCGv ret, TCGv arg1, TCGv arg2)
713 c896fe29 bellard
{
714 c896fe29 bellard
    tcg_gen_op3(INDEX_op_add_i64, ret, arg1, arg2);
715 c896fe29 bellard
}
716 c896fe29 bellard
717 ac56dd48 pbrook
static inline void tcg_gen_addi_i64(TCGv ret, TCGv arg1, int64_t arg2)
718 c896fe29 bellard
{
719 c896fe29 bellard
    tcg_gen_add_i64(ret, arg1, tcg_const_i64(arg2));
720 c896fe29 bellard
}
721 c896fe29 bellard
722 ac56dd48 pbrook
static inline void tcg_gen_sub_i64(TCGv ret, TCGv arg1, TCGv arg2)
723 c896fe29 bellard
{
724 c896fe29 bellard
    tcg_gen_op3(INDEX_op_sub_i64, ret, arg1, arg2);
725 c896fe29 bellard
}
726 c896fe29 bellard
727 ac56dd48 pbrook
static inline void tcg_gen_subi_i64(TCGv ret, TCGv arg1, int64_t arg2)
728 c896fe29 bellard
{
729 c896fe29 bellard
    tcg_gen_sub_i64(ret, arg1, tcg_const_i64(arg2));
730 c896fe29 bellard
}
731 c896fe29 bellard
732 ac56dd48 pbrook
static inline void tcg_gen_and_i64(TCGv ret, TCGv arg1, TCGv arg2)
733 c896fe29 bellard
{
734 c896fe29 bellard
    tcg_gen_op3(INDEX_op_and_i64, ret, arg1, arg2);
735 c896fe29 bellard
}
736 c896fe29 bellard
737 ac56dd48 pbrook
static inline void tcg_gen_andi_i64(TCGv ret, TCGv arg1, int64_t arg2)
738 c896fe29 bellard
{
739 c896fe29 bellard
    tcg_gen_and_i64(ret, arg1, tcg_const_i64(arg2));
740 c896fe29 bellard
}
741 c896fe29 bellard
742 ac56dd48 pbrook
static inline void tcg_gen_or_i64(TCGv ret, TCGv arg1, TCGv arg2)
743 c896fe29 bellard
{
744 c896fe29 bellard
    tcg_gen_op3(INDEX_op_or_i64, ret, arg1, arg2);
745 c896fe29 bellard
}
746 c896fe29 bellard
747 ac56dd48 pbrook
static inline void tcg_gen_ori_i64(TCGv ret, TCGv arg1, int64_t arg2)
748 c896fe29 bellard
{
749 c896fe29 bellard
    tcg_gen_or_i64(ret, arg1, tcg_const_i64(arg2));
750 c896fe29 bellard
}
751 c896fe29 bellard
752 ac56dd48 pbrook
static inline void tcg_gen_xor_i64(TCGv ret, TCGv arg1, TCGv arg2)
753 c896fe29 bellard
{
754 c896fe29 bellard
    tcg_gen_op3(INDEX_op_xor_i64, ret, arg1, arg2);
755 c896fe29 bellard
}
756 c896fe29 bellard
757 ac56dd48 pbrook
static inline void tcg_gen_xori_i64(TCGv ret, TCGv arg1, int64_t arg2)
758 c896fe29 bellard
{
759 c896fe29 bellard
    tcg_gen_xor_i64(ret, arg1, tcg_const_i64(arg2));
760 c896fe29 bellard
}
761 c896fe29 bellard
762 ac56dd48 pbrook
static inline void tcg_gen_shl_i64(TCGv ret, TCGv arg1, TCGv arg2)
763 c896fe29 bellard
{
764 c896fe29 bellard
    tcg_gen_op3(INDEX_op_shl_i64, ret, arg1, arg2);
765 c896fe29 bellard
}
766 c896fe29 bellard
767 ac56dd48 pbrook
static inline void tcg_gen_shli_i64(TCGv ret, TCGv arg1, int64_t arg2)
768 c896fe29 bellard
{
769 c896fe29 bellard
    tcg_gen_shl_i64(ret, arg1, tcg_const_i64(arg2));
770 c896fe29 bellard
}
771 c896fe29 bellard
772 ac56dd48 pbrook
static inline void tcg_gen_shr_i64(TCGv ret, TCGv arg1, TCGv arg2)
773 c896fe29 bellard
{
774 c896fe29 bellard
    tcg_gen_op3(INDEX_op_shr_i64, ret, arg1, arg2);
775 c896fe29 bellard
}
776 c896fe29 bellard
777 ac56dd48 pbrook
static inline void tcg_gen_shri_i64(TCGv ret, TCGv arg1, int64_t arg2)
778 c896fe29 bellard
{
779 c896fe29 bellard
    tcg_gen_shr_i64(ret, arg1, tcg_const_i64(arg2));
780 c896fe29 bellard
}
781 c896fe29 bellard
782 ac56dd48 pbrook
static inline void tcg_gen_sar_i64(TCGv ret, TCGv arg1, TCGv arg2)
783 c896fe29 bellard
{
784 c896fe29 bellard
    tcg_gen_op3(INDEX_op_sar_i64, ret, arg1, arg2);
785 c896fe29 bellard
}
786 c896fe29 bellard
787 ac56dd48 pbrook
static inline void tcg_gen_sari_i64(TCGv ret, TCGv arg1, int64_t arg2)
788 c896fe29 bellard
{
789 c896fe29 bellard
    tcg_gen_sar_i64(ret, arg1, tcg_const_i64(arg2));
790 c896fe29 bellard
}
791 c896fe29 bellard
792 ac56dd48 pbrook
static inline void tcg_gen_brcond_i64(int cond, TCGv arg1, TCGv arg2, 
793 c896fe29 bellard
                                      int label_index)
794 c896fe29 bellard
{
795 ac56dd48 pbrook
    tcg_gen_op4ii(INDEX_op_brcond_i64, arg1, arg2, cond, label_index);
796 c896fe29 bellard
}
797 c896fe29 bellard
798 ac56dd48 pbrook
static inline void tcg_gen_mul_i64(TCGv ret, TCGv arg1, TCGv arg2)
799 c896fe29 bellard
{
800 c896fe29 bellard
    tcg_gen_op3(INDEX_op_mul_i64, ret, arg1, arg2);
801 c896fe29 bellard
}
802 c896fe29 bellard
803 c896fe29 bellard
#ifdef TCG_TARGET_HAS_div_i64
804 ac56dd48 pbrook
static inline void tcg_gen_div_i64(TCGv ret, TCGv arg1, TCGv arg2)
805 c896fe29 bellard
{
806 c896fe29 bellard
    tcg_gen_op3(INDEX_op_div_i64, ret, arg1, arg2);
807 c896fe29 bellard
}
808 c896fe29 bellard
809 ac56dd48 pbrook
static inline void tcg_gen_rem_i64(TCGv ret, TCGv arg1, TCGv arg2)
810 c896fe29 bellard
{
811 c896fe29 bellard
    tcg_gen_op3(INDEX_op_rem_i64, ret, arg1, arg2);
812 c896fe29 bellard
}
813 c896fe29 bellard
814 ac56dd48 pbrook
static inline void tcg_gen_divu_i64(TCGv ret, TCGv arg1, TCGv arg2)
815 c896fe29 bellard
{
816 c896fe29 bellard
    tcg_gen_op3(INDEX_op_divu_i64, ret, arg1, arg2);
817 c896fe29 bellard
}
818 c896fe29 bellard
819 ac56dd48 pbrook
static inline void tcg_gen_remu_i64(TCGv ret, TCGv arg1, TCGv arg2)
820 c896fe29 bellard
{
821 c896fe29 bellard
    tcg_gen_op3(INDEX_op_remu_i64, ret, arg1, arg2);
822 c896fe29 bellard
}
823 c896fe29 bellard
#else
824 ac56dd48 pbrook
static inline void tcg_gen_div_i64(TCGv ret, TCGv arg1, TCGv arg2)
825 c896fe29 bellard
{
826 ac56dd48 pbrook
    TCGv t0;
827 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I64);
828 c896fe29 bellard
    tcg_gen_sari_i64(t0, arg1, 63);
829 c896fe29 bellard
    tcg_gen_op5(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2);
830 c896fe29 bellard
}
831 c896fe29 bellard
832 ac56dd48 pbrook
static inline void tcg_gen_rem_i64(TCGv ret, TCGv arg1, TCGv arg2)
833 c896fe29 bellard
{
834 ac56dd48 pbrook
    TCGv t0;
835 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I64);
836 c896fe29 bellard
    tcg_gen_sari_i64(t0, arg1, 63);
837 c896fe29 bellard
    tcg_gen_op5(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2);
838 c896fe29 bellard
}
839 c896fe29 bellard
840 ac56dd48 pbrook
static inline void tcg_gen_divu_i64(TCGv ret, TCGv arg1, TCGv arg2)
841 c896fe29 bellard
{
842 ac56dd48 pbrook
    TCGv t0;
843 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I64);
844 c896fe29 bellard
    tcg_gen_movi_i64(t0, 0);
845 c896fe29 bellard
    tcg_gen_op5(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2);
846 c896fe29 bellard
}
847 c896fe29 bellard
848 ac56dd48 pbrook
static inline void tcg_gen_remu_i64(TCGv ret, TCGv arg1, TCGv arg2)
849 c896fe29 bellard
{
850 ac56dd48 pbrook
    TCGv t0;
851 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I64);
852 c896fe29 bellard
    tcg_gen_movi_i64(t0, 0);
853 c896fe29 bellard
    tcg_gen_op5(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2);
854 c896fe29 bellard
}
855 c896fe29 bellard
#endif
856 c896fe29 bellard
857 c896fe29 bellard
#endif
858 c896fe29 bellard
859 c896fe29 bellard
/***************************************/
860 c896fe29 bellard
/* optional operations */
861 c896fe29 bellard
862 ac56dd48 pbrook
static inline void tcg_gen_ext8s_i32(TCGv ret, TCGv arg)
863 c896fe29 bellard
{
864 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext8s_i32
865 c896fe29 bellard
    tcg_gen_op2(INDEX_op_ext8s_i32, ret, arg);
866 c896fe29 bellard
#else
867 c896fe29 bellard
    tcg_gen_shli_i32(ret, arg, 24);
868 5ff9d6a4 bellard
    tcg_gen_sari_i32(ret, ret, 24);
869 c896fe29 bellard
#endif
870 c896fe29 bellard
}
871 c896fe29 bellard
872 ac56dd48 pbrook
static inline void tcg_gen_ext16s_i32(TCGv ret, TCGv arg)
873 c896fe29 bellard
{
874 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext16s_i32
875 c896fe29 bellard
    tcg_gen_op2(INDEX_op_ext16s_i32, ret, arg);
876 c896fe29 bellard
#else
877 c896fe29 bellard
    tcg_gen_shli_i32(ret, arg, 16);
878 5ff9d6a4 bellard
    tcg_gen_sari_i32(ret, ret, 16);
879 c896fe29 bellard
#endif
880 c896fe29 bellard
}
881 c896fe29 bellard
882 c896fe29 bellard
/* Note: we assume the two high bytes are set to zero */
883 ac56dd48 pbrook
static inline void tcg_gen_bswap16_i32(TCGv ret, TCGv arg)
884 c896fe29 bellard
{
885 c896fe29 bellard
#ifdef TCG_TARGET_HAS_bswap16_i32
886 c896fe29 bellard
    tcg_gen_op2(INDEX_op_bswap16_i32, ret, arg);
887 c896fe29 bellard
#else
888 ac56dd48 pbrook
    TCGv t0, t1;
889 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
890 c896fe29 bellard
    t1 = tcg_temp_new(TCG_TYPE_I32);
891 c896fe29 bellard
    
892 c896fe29 bellard
    tcg_gen_shri_i32(t0, arg, 8);
893 c896fe29 bellard
    tcg_gen_andi_i32(t1, arg, 0x000000ff);
894 c896fe29 bellard
    tcg_gen_shli_i32(t1, t1, 8);
895 c896fe29 bellard
    tcg_gen_or_i32(ret, t0, t1);
896 c896fe29 bellard
#endif
897 c896fe29 bellard
}
898 c896fe29 bellard
899 ac56dd48 pbrook
static inline void tcg_gen_bswap_i32(TCGv ret, TCGv arg)
900 c896fe29 bellard
{
901 c896fe29 bellard
#ifdef TCG_TARGET_HAS_bswap_i32
902 c896fe29 bellard
    tcg_gen_op2(INDEX_op_bswap_i32, ret, arg);
903 c896fe29 bellard
#else
904 ac56dd48 pbrook
    TCGv t0, t1;
905 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
906 c896fe29 bellard
    t1 = tcg_temp_new(TCG_TYPE_I32);
907 c896fe29 bellard
    
908 c896fe29 bellard
    tcg_gen_shli_i32(t0, arg, 24);
909 c896fe29 bellard
    
910 c896fe29 bellard
    tcg_gen_andi_i32(t1, arg, 0x0000ff00);
911 c896fe29 bellard
    tcg_gen_shli_i32(t1, t1, 8);
912 c896fe29 bellard
    tcg_gen_or_i32(t0, t0, t1);
913 c896fe29 bellard
    
914 c896fe29 bellard
    tcg_gen_shri_i32(t1, arg, 8);
915 c896fe29 bellard
    tcg_gen_andi_i32(t1, t1, 0x0000ff00);
916 c896fe29 bellard
    tcg_gen_or_i32(t0, t0, t1);
917 c896fe29 bellard
    
918 c896fe29 bellard
    tcg_gen_shri_i32(t1, arg, 24);
919 c896fe29 bellard
    tcg_gen_or_i32(ret, t0, t1);
920 c896fe29 bellard
#endif
921 c896fe29 bellard
}
922 c896fe29 bellard
923 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
924 ac56dd48 pbrook
static inline void tcg_gen_ext8s_i64(TCGv ret, TCGv arg)
925 c896fe29 bellard
{
926 c896fe29 bellard
    tcg_gen_ext8s_i32(ret, arg);
927 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
928 c896fe29 bellard
}
929 c896fe29 bellard
930 ac56dd48 pbrook
static inline void tcg_gen_ext16s_i64(TCGv ret, TCGv arg)
931 c896fe29 bellard
{
932 c896fe29 bellard
    tcg_gen_ext16s_i32(ret, arg);
933 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
934 c896fe29 bellard
}
935 c896fe29 bellard
936 ac56dd48 pbrook
static inline void tcg_gen_ext32s_i64(TCGv ret, TCGv arg)
937 c896fe29 bellard
{
938 c896fe29 bellard
    tcg_gen_mov_i32(ret, arg);
939 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
940 c896fe29 bellard
}
941 c896fe29 bellard
942 ac56dd48 pbrook
static inline void tcg_gen_trunc_i64_i32(TCGv ret, TCGv arg)
943 c896fe29 bellard
{
944 c896fe29 bellard
    tcg_gen_mov_i32(ret, arg);
945 c896fe29 bellard
}
946 c896fe29 bellard
947 ac56dd48 pbrook
static inline void tcg_gen_extu_i32_i64(TCGv ret, TCGv arg)
948 c896fe29 bellard
{
949 c896fe29 bellard
    tcg_gen_mov_i32(ret, arg);
950 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
951 c896fe29 bellard
}
952 c896fe29 bellard
953 ac56dd48 pbrook
static inline void tcg_gen_ext_i32_i64(TCGv ret, TCGv arg)
954 c896fe29 bellard
{
955 c896fe29 bellard
    tcg_gen_mov_i32(ret, arg);
956 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
957 c896fe29 bellard
}
958 c896fe29 bellard
959 ac56dd48 pbrook
static inline void tcg_gen_bswap_i64(TCGv ret, TCGv arg)
960 c896fe29 bellard
{
961 ac56dd48 pbrook
    TCGv t0, t1;
962 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
963 c896fe29 bellard
    t1 = tcg_temp_new(TCG_TYPE_I32);
964 c896fe29 bellard
965 c896fe29 bellard
    tcg_gen_bswap_i32(t0, arg);
966 ac56dd48 pbrook
    tcg_gen_bswap_i32(t1, TCGV_HIGH(arg));
967 c896fe29 bellard
    tcg_gen_mov_i32(ret, t1);
968 ac56dd48 pbrook
    tcg_gen_mov_i32(TCGV_HIGH(ret), t0);
969 c896fe29 bellard
}
970 c896fe29 bellard
#else
971 c896fe29 bellard
972 ac56dd48 pbrook
static inline void tcg_gen_ext8s_i64(TCGv ret, TCGv arg)
973 c896fe29 bellard
{
974 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext8s_i64
975 c896fe29 bellard
    tcg_gen_op2(INDEX_op_ext8s_i64, ret, arg);
976 c896fe29 bellard
#else
977 c896fe29 bellard
    tcg_gen_shli_i64(ret, arg, 56);
978 5ff9d6a4 bellard
    tcg_gen_sari_i64(ret, ret, 56);
979 c896fe29 bellard
#endif
980 c896fe29 bellard
}
981 c896fe29 bellard
982 ac56dd48 pbrook
static inline void tcg_gen_ext16s_i64(TCGv ret, TCGv arg)
983 c896fe29 bellard
{
984 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext16s_i64
985 c896fe29 bellard
    tcg_gen_op2(INDEX_op_ext16s_i64, ret, arg);
986 c896fe29 bellard
#else
987 c896fe29 bellard
    tcg_gen_shli_i64(ret, arg, 48);
988 5ff9d6a4 bellard
    tcg_gen_sari_i64(ret, ret, 48);
989 c896fe29 bellard
#endif
990 c896fe29 bellard
}
991 c896fe29 bellard
992 ac56dd48 pbrook
static inline void tcg_gen_ext32s_i64(TCGv ret, TCGv arg)
993 c896fe29 bellard
{
994 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext32s_i64
995 c896fe29 bellard
    tcg_gen_op2(INDEX_op_ext32s_i64, ret, arg);
996 c896fe29 bellard
#else
997 c896fe29 bellard
    tcg_gen_shli_i64(ret, arg, 32);
998 5ff9d6a4 bellard
    tcg_gen_sari_i64(ret, ret, 32);
999 c896fe29 bellard
#endif
1000 c896fe29 bellard
}
1001 c896fe29 bellard
1002 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1003 ac56dd48 pbrook
   registers.  This will probably break MIPS64 targets.  */
1004 ac56dd48 pbrook
static inline void tcg_gen_trunc_i64_i32(TCGv ret, TCGv arg)
1005 c896fe29 bellard
{
1006 c896fe29 bellard
    tcg_gen_mov_i32(ret, arg);
1007 c896fe29 bellard
}
1008 c896fe29 bellard
1009 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1010 c896fe29 bellard
   registers */
1011 ac56dd48 pbrook
static inline void tcg_gen_extu_i32_i64(TCGv ret, TCGv arg)
1012 c896fe29 bellard
{
1013 c896fe29 bellard
    tcg_gen_andi_i64(ret, arg, 0xffffffff);
1014 c896fe29 bellard
}
1015 c896fe29 bellard
1016 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1017 c896fe29 bellard
   registers */
1018 ac56dd48 pbrook
static inline void tcg_gen_ext_i32_i64(TCGv ret, TCGv arg)
1019 c896fe29 bellard
{
1020 c896fe29 bellard
    tcg_gen_ext32s_i64(ret, arg);
1021 c896fe29 bellard
}
1022 c896fe29 bellard
1023 ac56dd48 pbrook
static inline void tcg_gen_bswap_i64(TCGv ret, TCGv arg)
1024 c896fe29 bellard
{
1025 c896fe29 bellard
#ifdef TCG_TARGET_HAS_bswap_i64
1026 c896fe29 bellard
    tcg_gen_op2(INDEX_op_bswap_i64, ret, arg);
1027 c896fe29 bellard
#else
1028 ac56dd48 pbrook
    TCGv t0, t1;
1029 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
1030 c896fe29 bellard
    t1 = tcg_temp_new(TCG_TYPE_I32);
1031 c896fe29 bellard
    
1032 c896fe29 bellard
    tcg_gen_shli_i64(t0, arg, 56);
1033 c896fe29 bellard
    
1034 c896fe29 bellard
    tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1035 c896fe29 bellard
    tcg_gen_shli_i64(t1, t1, 40);
1036 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1037 c896fe29 bellard
    
1038 c896fe29 bellard
    tcg_gen_andi_i64(t1, arg, 0x00ff0000);
1039 c896fe29 bellard
    tcg_gen_shli_i64(t1, t1, 24);
1040 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1041 c896fe29 bellard
1042 c896fe29 bellard
    tcg_gen_andi_i64(t1, arg, 0xff000000);
1043 c896fe29 bellard
    tcg_gen_shli_i64(t1, t1, 8);
1044 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1045 c896fe29 bellard
1046 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 8);
1047 c896fe29 bellard
    tcg_gen_andi_i64(t1, t1, 0xff000000);
1048 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1049 c896fe29 bellard
    
1050 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 24);
1051 c896fe29 bellard
    tcg_gen_andi_i64(t1, t1, 0x00ff0000);
1052 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1053 c896fe29 bellard
1054 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 40);
1055 c896fe29 bellard
    tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1056 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1057 c896fe29 bellard
1058 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 56);
1059 c896fe29 bellard
    tcg_gen_or_i64(ret, t0, t1);
1060 c896fe29 bellard
#endif
1061 c896fe29 bellard
}
1062 c896fe29 bellard
1063 c896fe29 bellard
#endif
1064 c896fe29 bellard
1065 5ff9d6a4 bellard
1066 5ff9d6a4 bellard
static inline void tcg_gen_discard_i32(TCGv arg)
1067 5ff9d6a4 bellard
{
1068 5ff9d6a4 bellard
    tcg_gen_op1(INDEX_op_discard, arg);
1069 5ff9d6a4 bellard
}
1070 5ff9d6a4 bellard
1071 5ff9d6a4 bellard
#if TCG_TARGET_REG_BITS == 32
1072 5ff9d6a4 bellard
static inline void tcg_gen_discard_i64(TCGv arg)
1073 5ff9d6a4 bellard
{
1074 5ff9d6a4 bellard
    tcg_gen_discard_i32(arg);
1075 5ff9d6a4 bellard
    tcg_gen_discard_i32(TCGV_HIGH(arg));
1076 5ff9d6a4 bellard
}
1077 5ff9d6a4 bellard
#else
1078 5ff9d6a4 bellard
static inline void tcg_gen_discard_i64(TCGv arg)
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{
1080 5ff9d6a4 bellard
    tcg_gen_op1(INDEX_op_discard, arg);
1081 5ff9d6a4 bellard
}
1082 5ff9d6a4 bellard
#endif
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1084 c896fe29 bellard
/***************************************/
1085 ac56dd48 pbrook
static inline void tcg_gen_macro_2(TCGv ret0, TCGv ret1, int macro_id)
1086 c896fe29 bellard
{
1087 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_macro_2, ret0, ret1, macro_id);
1088 c896fe29 bellard
}
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1090 c896fe29 bellard
/***************************************/
1091 c896fe29 bellard
/* QEMU specific operations. Their type depend on the QEMU CPU
1092 c896fe29 bellard
   type. */
1093 c896fe29 bellard
#ifndef TARGET_LONG_BITS
1094 c896fe29 bellard
#error must include QEMU headers
1095 c896fe29 bellard
#endif
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1097 c896fe29 bellard
static inline void tcg_gen_exit_tb(tcg_target_long val)
1098 c896fe29 bellard
{
1099 ac56dd48 pbrook
    tcg_gen_op1i(INDEX_op_exit_tb, val);
1100 c896fe29 bellard
}
1101 c896fe29 bellard
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static inline void tcg_gen_goto_tb(int idx)
1103 c896fe29 bellard
{
1104 ac56dd48 pbrook
    tcg_gen_op1i(INDEX_op_goto_tb, idx);
1105 c896fe29 bellard
}
1106 c896fe29 bellard
1107 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
1108 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
1109 c896fe29 bellard
{
1110 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1111 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld8u, ret, addr, mem_index);
1112 c896fe29 bellard
#else
1113 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld8u, ret, addr, TCGV_HIGH(addr), mem_index);
1114 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1115 c896fe29 bellard
#endif
1116 c896fe29 bellard
}
1117 c896fe29 bellard
1118 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
1119 c896fe29 bellard
{
1120 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1121 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld8s, ret, addr, mem_index);
1122 c896fe29 bellard
#else
1123 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld8s, ret, addr, TCGV_HIGH(addr), mem_index);
1124 ac56dd48 pbrook
    tcg_gen_ext8s_i32(TCGV_HIGH(ret), ret);
1125 c896fe29 bellard
#endif
1126 c896fe29 bellard
}
1127 c896fe29 bellard
1128 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
1129 c896fe29 bellard
{
1130 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1131 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld16u, ret, addr, mem_index);
1132 c896fe29 bellard
#else
1133 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld16u, ret, addr, TCGV_HIGH(addr), mem_index);
1134 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1135 c896fe29 bellard
#endif
1136 c896fe29 bellard
}
1137 c896fe29 bellard
1138 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
1139 c896fe29 bellard
{
1140 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1141 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld16s, ret, addr, mem_index);
1142 c896fe29 bellard
#else
1143 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld16s, ret, addr, TCGV_HIGH(addr), mem_index);
1144 ac56dd48 pbrook
    tcg_gen_ext16s_i32(TCGV_HIGH(ret), ret);
1145 c896fe29 bellard
#endif
1146 c896fe29 bellard
}
1147 c896fe29 bellard
1148 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
1149 c896fe29 bellard
{
1150 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1151 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1152 c896fe29 bellard
#else
1153 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld32u, ret, addr, TCGV_HIGH(addr), mem_index);
1154 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1155 c896fe29 bellard
#endif
1156 c896fe29 bellard
}
1157 c896fe29 bellard
1158 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
1159 c896fe29 bellard
{
1160 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1161 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1162 c896fe29 bellard
#else
1163 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld32u, ret, addr, TCGV_HIGH(addr), mem_index);
1164 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
1165 c896fe29 bellard
#endif
1166 c896fe29 bellard
}
1167 c896fe29 bellard
1168 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld64(TCGv ret, TCGv addr, int mem_index)
1169 c896fe29 bellard
{
1170 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1171 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld64, ret, TCGV_HIGH(ret), addr, mem_index);
1172 c896fe29 bellard
#else
1173 ac56dd48 pbrook
    tcg_gen_op5i(INDEX_op_qemu_ld64, ret, TCGV_HIGH(ret),
1174 ac56dd48 pbrook
                 addr, TCGV_HIGH(addr), mem_index);
1175 c896fe29 bellard
#endif
1176 c896fe29 bellard
}
1177 c896fe29 bellard
1178 ac56dd48 pbrook
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
1179 c896fe29 bellard
{
1180 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1181 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st8, arg, addr, mem_index);
1182 c896fe29 bellard
#else
1183 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_st8, arg, addr, TCGV_HIGH(addr), mem_index);
1184 c896fe29 bellard
#endif
1185 c896fe29 bellard
}
1186 c896fe29 bellard
1187 ac56dd48 pbrook
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
1188 c896fe29 bellard
{
1189 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1190 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st16, arg, addr, mem_index);
1191 c896fe29 bellard
#else
1192 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_st16, arg, addr, TCGV_HIGH(addr), mem_index);
1193 c896fe29 bellard
#endif
1194 c896fe29 bellard
}
1195 c896fe29 bellard
1196 ac56dd48 pbrook
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
1197 c896fe29 bellard
{
1198 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1199 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st32, arg, addr, mem_index);
1200 c896fe29 bellard
#else
1201 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_st32, arg, addr, TCGV_HIGH(addr), mem_index);
1202 c896fe29 bellard
#endif
1203 c896fe29 bellard
}
1204 c896fe29 bellard
1205 ac56dd48 pbrook
static inline void tcg_gen_qemu_st64(TCGv arg, TCGv addr, int mem_index)
1206 c896fe29 bellard
{
1207 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1208 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_st64, arg, TCGV_HIGH(arg), addr, mem_index);
1209 c896fe29 bellard
#else
1210 ac56dd48 pbrook
    tcg_gen_op5i(INDEX_op_qemu_st64, arg, TCGV_HIGH(arg),
1211 ac56dd48 pbrook
                 addr, TCGV_HIGH(addr), mem_index);
1212 c896fe29 bellard
#endif
1213 c896fe29 bellard
}
1214 c896fe29 bellard
1215 c896fe29 bellard
#else /* TCG_TARGET_REG_BITS == 32 */
1216 c896fe29 bellard
1217 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
1218 c896fe29 bellard
{
1219 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld8u, ret, addr, mem_index);
1220 c896fe29 bellard
}
1221 c896fe29 bellard
1222 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
1223 c896fe29 bellard
{
1224 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld8s, ret, addr, mem_index);
1225 c896fe29 bellard
}
1226 c896fe29 bellard
1227 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
1228 c896fe29 bellard
{
1229 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld16u, ret, addr, mem_index);
1230 c896fe29 bellard
}
1231 c896fe29 bellard
1232 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
1233 c896fe29 bellard
{
1234 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld16s, ret, addr, mem_index);
1235 c896fe29 bellard
}
1236 c896fe29 bellard
1237 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
1238 c896fe29 bellard
{
1239 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1240 c896fe29 bellard
}
1241 c896fe29 bellard
1242 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
1243 c896fe29 bellard
{
1244 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld32s, ret, addr, mem_index);
1245 c896fe29 bellard
}
1246 c896fe29 bellard
1247 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld64(TCGv ret, TCGv addr, int mem_index)
1248 c896fe29 bellard
{
1249 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld64, ret, addr, mem_index);
1250 c896fe29 bellard
}
1251 c896fe29 bellard
1252 ac56dd48 pbrook
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
1253 c896fe29 bellard
{
1254 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st8, arg, addr, mem_index);
1255 c896fe29 bellard
}
1256 c896fe29 bellard
1257 ac56dd48 pbrook
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
1258 c896fe29 bellard
{
1259 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st16, arg, addr, mem_index);
1260 c896fe29 bellard
}
1261 c896fe29 bellard
1262 ac56dd48 pbrook
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
1263 c896fe29 bellard
{
1264 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st32, arg, addr, mem_index);
1265 c896fe29 bellard
}
1266 c896fe29 bellard
1267 ac56dd48 pbrook
static inline void tcg_gen_qemu_st64(TCGv arg, TCGv addr, int mem_index)
1268 c896fe29 bellard
{
1269 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st64, arg, addr, mem_index);
1270 c896fe29 bellard
}
1271 c896fe29 bellard
1272 c896fe29 bellard
#endif /* TCG_TARGET_REG_BITS != 32 */