root / tcg / tcg-op.h @ 5ff9d6a4
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/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "tcg.h" |
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|
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/* legacy dyngen operations */
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#include "gen-op.h" |
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|
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int gen_new_label(void); |
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static inline void tcg_gen_op1(int opc, TCGv arg1) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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} |
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|
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static inline void tcg_gen_op1i(int opc, TCGArg arg1) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = arg1; |
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} |
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|
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static inline void tcg_gen_op2(int opc, TCGv arg1, TCGv arg2) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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} |
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|
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static inline void tcg_gen_op2i(int opc, TCGv arg1, TCGArg arg2) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = arg2; |
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} |
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|
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static inline void tcg_gen_op3(int opc, TCGv arg1, TCGv arg2, TCGv arg3) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = GET_TCGV(arg3); |
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} |
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static inline void tcg_gen_op3i(int opc, TCGv arg1, TCGv arg2, TCGArg arg3) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = arg3; |
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} |
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static inline void tcg_gen_op4(int opc, TCGv arg1, TCGv arg2, TCGv arg3, |
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TCGv arg4) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = GET_TCGV(arg3); |
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*gen_opparam_ptr++ = GET_TCGV(arg4); |
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} |
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static inline void tcg_gen_op4i(int opc, TCGv arg1, TCGv arg2, TCGv arg3, |
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TCGArg arg4) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = GET_TCGV(arg3); |
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*gen_opparam_ptr++ = arg4; |
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} |
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static inline void tcg_gen_op4ii(int opc, TCGv arg1, TCGv arg2, TCGArg arg3, |
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TCGArg arg4) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = arg3; |
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*gen_opparam_ptr++ = arg4; |
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} |
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static inline void tcg_gen_op5(int opc, TCGv arg1, TCGv arg2, |
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TCGv arg3, TCGv arg4, |
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TCGv arg5) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = GET_TCGV(arg3); |
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*gen_opparam_ptr++ = GET_TCGV(arg4); |
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*gen_opparam_ptr++ = GET_TCGV(arg5); |
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} |
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static inline void tcg_gen_op5i(int opc, TCGv arg1, TCGv arg2, |
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TCGv arg3, TCGv arg4, |
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TCGArg arg5) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = GET_TCGV(arg3); |
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*gen_opparam_ptr++ = GET_TCGV(arg4); |
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*gen_opparam_ptr++ = arg5; |
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} |
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static inline void tcg_gen_op6(int opc, TCGv arg1, TCGv arg2, |
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TCGv arg3, TCGv arg4, |
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TCGv arg5, TCGv arg6) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = GET_TCGV(arg3); |
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*gen_opparam_ptr++ = GET_TCGV(arg4); |
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*gen_opparam_ptr++ = GET_TCGV(arg5); |
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*gen_opparam_ptr++ = GET_TCGV(arg6); |
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} |
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static inline void tcg_gen_op6ii(int opc, TCGv arg1, TCGv arg2, |
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TCGv arg3, TCGv arg4, |
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TCGArg arg5, TCGArg arg6) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = GET_TCGV(arg3); |
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*gen_opparam_ptr++ = GET_TCGV(arg4); |
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*gen_opparam_ptr++ = arg5; |
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*gen_opparam_ptr++ = arg6; |
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} |
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static inline void gen_set_label(int n) |
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{
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tcg_gen_op1i(INDEX_op_set_label, n); |
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} |
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static inline void tcg_gen_mov_i32(TCGv ret, TCGv arg) |
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{
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tcg_gen_op2(INDEX_op_mov_i32, ret, arg); |
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} |
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static inline void tcg_gen_movi_i32(TCGv ret, int32_t arg) |
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{
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tcg_gen_op2i(INDEX_op_movi_i32, ret, arg); |
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} |
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/* helper calls */
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#define TCG_HELPER_CALL_FLAGS 0 |
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static inline void tcg_gen_helper_0_0(void *func) |
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{
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tcg_gen_call(&tcg_ctx, |
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tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
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0, NULL, 0, NULL); |
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} |
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static inline void tcg_gen_helper_0_1(void *func, TCGv arg) |
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{
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tcg_gen_call(&tcg_ctx, |
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tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
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0, NULL, 1, &arg); |
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} |
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static inline void tcg_gen_helper_0_2(void *func, TCGv arg1, TCGv arg2) |
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{
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TCGv args[2];
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args[0] = arg1;
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args[1] = arg2;
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tcg_gen_call(&tcg_ctx, |
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tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
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0, NULL, 2, args); |
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} |
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static inline void tcg_gen_helper_1_2(void *func, TCGv ret, |
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TCGv arg1, TCGv arg2) |
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{
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TCGv args[2];
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args[0] = arg1;
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args[1] = arg2;
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tcg_gen_call(&tcg_ctx, |
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tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
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1, &ret, 2, args); |
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} |
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/* 32 bit ops */
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static inline void tcg_gen_ld8u_i32(TCGv ret, TCGv arg2, tcg_target_long offset) |
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{
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tcg_gen_op3i(INDEX_op_ld8u_i32, ret, arg2, offset); |
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} |
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static inline void tcg_gen_ld8s_i32(TCGv ret, TCGv arg2, tcg_target_long offset) |
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{
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tcg_gen_op3i(INDEX_op_ld8s_i32, ret, arg2, offset); |
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} |
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static inline void tcg_gen_ld16u_i32(TCGv ret, TCGv arg2, tcg_target_long offset) |
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{
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tcg_gen_op3i(INDEX_op_ld16u_i32, ret, arg2, offset); |
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} |
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static inline void tcg_gen_ld16s_i32(TCGv ret, TCGv arg2, tcg_target_long offset) |
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{
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tcg_gen_op3i(INDEX_op_ld16s_i32, ret, arg2, offset); |
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} |
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static inline void tcg_gen_ld_i32(TCGv ret, TCGv arg2, tcg_target_long offset) |
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{
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tcg_gen_op3i(INDEX_op_ld_i32, ret, arg2, offset); |
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} |
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static inline void tcg_gen_st8_i32(TCGv arg1, TCGv arg2, tcg_target_long offset) |
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{
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tcg_gen_op3i(INDEX_op_st8_i32, arg1, arg2, offset); |
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} |
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static inline void tcg_gen_st16_i32(TCGv arg1, TCGv arg2, tcg_target_long offset) |
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{
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tcg_gen_op3i(INDEX_op_st16_i32, arg1, arg2, offset); |
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} |
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static inline void tcg_gen_st_i32(TCGv arg1, TCGv arg2, tcg_target_long offset) |
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{
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tcg_gen_op3i(INDEX_op_st_i32, arg1, arg2, offset); |
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} |
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static inline void tcg_gen_add_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{
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tcg_gen_op3(INDEX_op_add_i32, ret, arg1, arg2); |
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} |
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static inline void tcg_gen_addi_i32(TCGv ret, TCGv arg1, int32_t arg2) |
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{
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tcg_gen_add_i32(ret, arg1, tcg_const_i32(arg2)); |
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} |
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static inline void tcg_gen_sub_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{
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tcg_gen_op3(INDEX_op_sub_i32, ret, arg1, arg2); |
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} |
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static inline void tcg_gen_subi_i32(TCGv ret, TCGv arg1, int32_t arg2) |
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{
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tcg_gen_sub_i32(ret, arg1, tcg_const_i32(arg2)); |
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} |
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static inline void tcg_gen_and_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{
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tcg_gen_op3(INDEX_op_and_i32, ret, arg1, arg2); |
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} |
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static inline void tcg_gen_andi_i32(TCGv ret, TCGv arg1, int32_t arg2) |
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{
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/* some cases can be optimized here */
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if (arg2 == 0) { |
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tcg_gen_movi_i32(ret, 0);
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} else if (arg2 == 0xffffffff) { |
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tcg_gen_mov_i32(ret, arg1); |
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} else {
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tcg_gen_and_i32(ret, arg1, tcg_const_i32(arg2)); |
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} |
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} |
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|
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static inline void tcg_gen_or_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{
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tcg_gen_op3(INDEX_op_or_i32, ret, arg1, arg2); |
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} |
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|
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static inline void tcg_gen_ori_i32(TCGv ret, TCGv arg1, int32_t arg2) |
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{
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/* some cases can be optimized here */
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if (arg2 == 0xffffffff) { |
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tcg_gen_movi_i32(ret, 0);
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} else if (arg2 == 0) { |
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tcg_gen_mov_i32(ret, arg1); |
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} else {
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tcg_gen_or_i32(ret, arg1, tcg_const_i32(arg2)); |
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} |
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} |
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|
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static inline void tcg_gen_xor_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{
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tcg_gen_op3(INDEX_op_xor_i32, ret, arg1, arg2); |
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} |
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|
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static inline void tcg_gen_xori_i32(TCGv ret, TCGv arg1, int32_t arg2) |
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{
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/* some cases can be optimized here */
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if (arg2 == 0) { |
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tcg_gen_mov_i32(ret, arg1); |
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} else {
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tcg_gen_xor_i32(ret, arg1, tcg_const_i32(arg2)); |
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} |
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} |
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|
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static inline void tcg_gen_shl_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{
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tcg_gen_op3(INDEX_op_shl_i32, ret, arg1, arg2); |
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} |
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|
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static inline void tcg_gen_shli_i32(TCGv ret, TCGv arg1, int32_t arg2) |
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{
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tcg_gen_shl_i32(ret, arg1, tcg_const_i32(arg2)); |
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} |
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|
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static inline void tcg_gen_shr_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{
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tcg_gen_op3(INDEX_op_shr_i32, ret, arg1, arg2); |
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} |
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|
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static inline void tcg_gen_shri_i32(TCGv ret, TCGv arg1, int32_t arg2) |
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{
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tcg_gen_shr_i32(ret, arg1, tcg_const_i32(arg2)); |
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} |
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|
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static inline void tcg_gen_sar_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{
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tcg_gen_op3(INDEX_op_sar_i32, ret, arg1, arg2); |
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} |
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|
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static inline void tcg_gen_sari_i32(TCGv ret, TCGv arg1, int32_t arg2) |
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{
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tcg_gen_sar_i32(ret, arg1, tcg_const_i32(arg2)); |
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} |
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|
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static inline void tcg_gen_brcond_i32(int cond, TCGv arg1, TCGv arg2, |
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int label_index)
|
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{
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tcg_gen_op4ii(INDEX_op_brcond_i32, arg1, arg2, cond, label_index); |
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} |
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|
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static inline void tcg_gen_mul_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{
|
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tcg_gen_op3(INDEX_op_mul_i32, ret, arg1, arg2); |
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} |
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|
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#ifdef TCG_TARGET_HAS_div_i32
|
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static inline void tcg_gen_div_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{
|
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tcg_gen_op3(INDEX_op_div_i32, ret, arg1, arg2); |
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} |
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|
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static inline void tcg_gen_rem_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{
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tcg_gen_op3(INDEX_op_rem_i32, ret, arg1, arg2); |
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} |
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|
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static inline void tcg_gen_divu_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{
|
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tcg_gen_op3(INDEX_op_divu_i32, ret, arg1, arg2); |
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} |
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|
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static inline void tcg_gen_remu_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{
|
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tcg_gen_op3(INDEX_op_remu_i32, ret, arg1, arg2); |
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} |
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#else
|
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static inline void tcg_gen_div_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{
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TCGv t0; |
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t0 = tcg_temp_new(TCG_TYPE_I32); |
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tcg_gen_sari_i32(t0, arg1, 31);
|
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tcg_gen_op5(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2); |
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} |
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|
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static inline void tcg_gen_rem_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{
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TCGv t0; |
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t0 = tcg_temp_new(TCG_TYPE_I32); |
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tcg_gen_sari_i32(t0, arg1, 31);
|
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tcg_gen_op5(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2); |
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} |
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|
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static inline void tcg_gen_divu_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{
|
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TCGv t0; |
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t0 = tcg_temp_new(TCG_TYPE_I32); |
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tcg_gen_movi_i32(t0, 0);
|
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tcg_gen_op5(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2); |
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} |
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|
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static inline void tcg_gen_remu_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{
|
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TCGv t0; |
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t0 = tcg_temp_new(TCG_TYPE_I32); |
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tcg_gen_movi_i32(t0, 0);
|
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tcg_gen_op5(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2); |
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} |
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#endif
|
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|
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#if TCG_TARGET_REG_BITS == 32 |
| 413 |
|
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static inline void tcg_gen_mov_i64(TCGv ret, TCGv arg) |
| 415 |
{
|
| 416 |
tcg_gen_mov_i32(ret, arg); |
| 417 |
tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
| 418 |
} |
| 419 |
|
| 420 |
static inline void tcg_gen_movi_i64(TCGv ret, int64_t arg) |
| 421 |
{
|
| 422 |
tcg_gen_movi_i32(ret, arg); |
| 423 |
tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
|
| 424 |
} |
| 425 |
|
| 426 |
static inline void tcg_gen_ld8u_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
| 427 |
{
|
| 428 |
tcg_gen_ld8u_i32(ret, arg2, offset); |
| 429 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
| 430 |
} |
| 431 |
|
| 432 |
static inline void tcg_gen_ld8s_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
| 433 |
{
|
| 434 |
tcg_gen_ld8s_i32(ret, arg2, offset); |
| 435 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
| 436 |
} |
| 437 |
|
| 438 |
static inline void tcg_gen_ld16u_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
| 439 |
{
|
| 440 |
tcg_gen_ld16u_i32(ret, arg2, offset); |
| 441 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
| 442 |
} |
| 443 |
|
| 444 |
static inline void tcg_gen_ld16s_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
| 445 |
{
|
| 446 |
tcg_gen_ld16s_i32(ret, arg2, offset); |
| 447 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
| 448 |
} |
| 449 |
|
| 450 |
static inline void tcg_gen_ld32u_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
| 451 |
{
|
| 452 |
tcg_gen_ld_i32(ret, arg2, offset); |
| 453 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
| 454 |
} |
| 455 |
|
| 456 |
static inline void tcg_gen_ld32s_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
| 457 |
{
|
| 458 |
tcg_gen_ld_i32(ret, arg2, offset); |
| 459 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
| 460 |
} |
| 461 |
|
| 462 |
static inline void tcg_gen_ld_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
| 463 |
{
|
| 464 |
/* since arg2 and ret have different types, they cannot be the
|
| 465 |
same temporary */
|
| 466 |
#ifdef TCG_TARGET_WORDS_BIGENDIAN
|
| 467 |
tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset); |
| 468 |
tcg_gen_ld_i32(ret, arg2, offset + 4);
|
| 469 |
#else
|
| 470 |
tcg_gen_ld_i32(ret, arg2, offset); |
| 471 |
tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
|
| 472 |
#endif
|
| 473 |
} |
| 474 |
|
| 475 |
static inline void tcg_gen_st8_i64(TCGv arg1, TCGv arg2, tcg_target_long offset) |
| 476 |
{
|
| 477 |
tcg_gen_st8_i32(arg1, arg2, offset); |
| 478 |
} |
| 479 |
|
| 480 |
static inline void tcg_gen_st16_i64(TCGv arg1, TCGv arg2, tcg_target_long offset) |
| 481 |
{
|
| 482 |
tcg_gen_st16_i32(arg1, arg2, offset); |
| 483 |
} |
| 484 |
|
| 485 |
static inline void tcg_gen_st32_i64(TCGv arg1, TCGv arg2, tcg_target_long offset) |
| 486 |
{
|
| 487 |
tcg_gen_st_i32(arg1, arg2, offset); |
| 488 |
} |
| 489 |
|
| 490 |
static inline void tcg_gen_st_i64(TCGv arg1, TCGv arg2, tcg_target_long offset) |
| 491 |
{
|
| 492 |
#ifdef TCG_TARGET_WORDS_BIGENDIAN
|
| 493 |
tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset); |
| 494 |
tcg_gen_st_i32(arg1, arg2, offset + 4);
|
| 495 |
#else
|
| 496 |
tcg_gen_st_i32(arg1, arg2, offset); |
| 497 |
tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
|
| 498 |
#endif
|
| 499 |
} |
| 500 |
|
| 501 |
static inline void tcg_gen_add_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 502 |
{
|
| 503 |
tcg_gen_op6(INDEX_op_add2_i32, ret, TCGV_HIGH(ret), |
| 504 |
arg1, TCGV_HIGH(arg1), arg2, TCGV_HIGH(arg2)); |
| 505 |
} |
| 506 |
|
| 507 |
static inline void tcg_gen_addi_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 508 |
{
|
| 509 |
tcg_gen_add_i64(ret, arg1, tcg_const_i64(arg2)); |
| 510 |
} |
| 511 |
|
| 512 |
static inline void tcg_gen_sub_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 513 |
{
|
| 514 |
tcg_gen_op6(INDEX_op_sub2_i32, ret, TCGV_HIGH(ret), |
| 515 |
arg1, TCGV_HIGH(arg1), arg2, TCGV_HIGH(arg2)); |
| 516 |
} |
| 517 |
|
| 518 |
static inline void tcg_gen_subi_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 519 |
{
|
| 520 |
tcg_gen_sub_i64(ret, arg1, tcg_const_i64(arg2)); |
| 521 |
} |
| 522 |
|
| 523 |
static inline void tcg_gen_and_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 524 |
{
|
| 525 |
tcg_gen_and_i32(ret, arg1, arg2); |
| 526 |
tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
| 527 |
} |
| 528 |
|
| 529 |
static inline void tcg_gen_andi_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 530 |
{
|
| 531 |
tcg_gen_andi_i32(ret, arg1, arg2); |
| 532 |
tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
|
| 533 |
} |
| 534 |
|
| 535 |
static inline void tcg_gen_or_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 536 |
{
|
| 537 |
tcg_gen_or_i32(ret, arg1, arg2); |
| 538 |
tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
| 539 |
} |
| 540 |
|
| 541 |
static inline void tcg_gen_ori_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 542 |
{
|
| 543 |
tcg_gen_ori_i32(ret, arg1, arg2); |
| 544 |
tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
|
| 545 |
} |
| 546 |
|
| 547 |
static inline void tcg_gen_xor_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 548 |
{
|
| 549 |
tcg_gen_xor_i32(ret, arg1, arg2); |
| 550 |
tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
| 551 |
} |
| 552 |
|
| 553 |
static inline void tcg_gen_xori_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 554 |
{
|
| 555 |
tcg_gen_xori_i32(ret, arg1, arg2); |
| 556 |
tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
|
| 557 |
} |
| 558 |
|
| 559 |
/* XXX: use generic code when basic block handling is OK or CPU
|
| 560 |
specific code (x86) */
|
| 561 |
static inline void tcg_gen_shl_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 562 |
{
|
| 563 |
tcg_gen_helper_1_2(tcg_helper_shl_i64, ret, arg1, arg2); |
| 564 |
} |
| 565 |
|
| 566 |
static inline void tcg_gen_shli_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 567 |
{
|
| 568 |
tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0); |
| 569 |
} |
| 570 |
|
| 571 |
static inline void tcg_gen_shr_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 572 |
{
|
| 573 |
tcg_gen_helper_1_2(tcg_helper_shr_i64, ret, arg1, arg2); |
| 574 |
} |
| 575 |
|
| 576 |
static inline void tcg_gen_shri_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 577 |
{
|
| 578 |
tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0); |
| 579 |
} |
| 580 |
|
| 581 |
static inline void tcg_gen_sar_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 582 |
{
|
| 583 |
tcg_gen_helper_1_2(tcg_helper_sar_i64, ret, arg1, arg2); |
| 584 |
} |
| 585 |
|
| 586 |
static inline void tcg_gen_sari_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 587 |
{
|
| 588 |
tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1); |
| 589 |
} |
| 590 |
|
| 591 |
static inline void tcg_gen_brcond_i64(int cond, TCGv arg1, TCGv arg2, |
| 592 |
int label_index)
|
| 593 |
{
|
| 594 |
tcg_gen_op6ii(INDEX_op_brcond2_i32, |
| 595 |
arg1, TCGV_HIGH(arg1), arg2, TCGV_HIGH(arg2), |
| 596 |
cond, label_index); |
| 597 |
} |
| 598 |
|
| 599 |
static inline void tcg_gen_mul_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 600 |
{
|
| 601 |
TCGv t0, t1; |
| 602 |
|
| 603 |
t0 = tcg_temp_new(TCG_TYPE_I64); |
| 604 |
t1 = tcg_temp_new(TCG_TYPE_I32); |
| 605 |
|
| 606 |
tcg_gen_op4(INDEX_op_mulu2_i32, t0, TCGV_HIGH(t0), arg1, arg2); |
| 607 |
|
| 608 |
tcg_gen_mul_i32(t1, arg1, TCGV_HIGH(arg2)); |
| 609 |
tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
| 610 |
tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), arg2); |
| 611 |
tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
| 612 |
|
| 613 |
tcg_gen_mov_i64(ret, t0); |
| 614 |
} |
| 615 |
|
| 616 |
static inline void tcg_gen_div_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 617 |
{
|
| 618 |
tcg_gen_helper_1_2(tcg_helper_div_i64, ret, arg1, arg2); |
| 619 |
} |
| 620 |
|
| 621 |
static inline void tcg_gen_rem_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 622 |
{
|
| 623 |
tcg_gen_helper_1_2(tcg_helper_rem_i64, ret, arg1, arg2); |
| 624 |
} |
| 625 |
|
| 626 |
static inline void tcg_gen_divu_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 627 |
{
|
| 628 |
tcg_gen_helper_1_2(tcg_helper_divu_i64, ret, arg1, arg2); |
| 629 |
} |
| 630 |
|
| 631 |
static inline void tcg_gen_remu_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 632 |
{
|
| 633 |
tcg_gen_helper_1_2(tcg_helper_remu_i64, ret, arg1, arg2); |
| 634 |
} |
| 635 |
|
| 636 |
#else
|
| 637 |
|
| 638 |
static inline void tcg_gen_mov_i64(TCGv ret, TCGv arg) |
| 639 |
{
|
| 640 |
tcg_gen_op2(INDEX_op_mov_i64, ret, arg); |
| 641 |
} |
| 642 |
|
| 643 |
static inline void tcg_gen_movi_i64(TCGv ret, int64_t arg) |
| 644 |
{
|
| 645 |
tcg_gen_op2i(INDEX_op_movi_i64, ret, arg); |
| 646 |
} |
| 647 |
|
| 648 |
static inline void tcg_gen_ld8u_i64(TCGv ret, TCGv arg2, |
| 649 |
tcg_target_long offset) |
| 650 |
{
|
| 651 |
tcg_gen_op3i(INDEX_op_ld8u_i64, ret, arg2, offset); |
| 652 |
} |
| 653 |
|
| 654 |
static inline void tcg_gen_ld8s_i64(TCGv ret, TCGv arg2, |
| 655 |
tcg_target_long offset) |
| 656 |
{
|
| 657 |
tcg_gen_op3i(INDEX_op_ld8s_i64, ret, arg2, offset); |
| 658 |
} |
| 659 |
|
| 660 |
static inline void tcg_gen_ld16u_i64(TCGv ret, TCGv arg2, |
| 661 |
tcg_target_long offset) |
| 662 |
{
|
| 663 |
tcg_gen_op3i(INDEX_op_ld16u_i64, ret, arg2, offset); |
| 664 |
} |
| 665 |
|
| 666 |
static inline void tcg_gen_ld16s_i64(TCGv ret, TCGv arg2, |
| 667 |
tcg_target_long offset) |
| 668 |
{
|
| 669 |
tcg_gen_op3i(INDEX_op_ld16s_i64, ret, arg2, offset); |
| 670 |
} |
| 671 |
|
| 672 |
static inline void tcg_gen_ld32u_i64(TCGv ret, TCGv arg2, |
| 673 |
tcg_target_long offset) |
| 674 |
{
|
| 675 |
tcg_gen_op3i(INDEX_op_ld32u_i64, ret, arg2, offset); |
| 676 |
} |
| 677 |
|
| 678 |
static inline void tcg_gen_ld32s_i64(TCGv ret, TCGv arg2, |
| 679 |
tcg_target_long offset) |
| 680 |
{
|
| 681 |
tcg_gen_op3i(INDEX_op_ld32s_i64, ret, arg2, offset); |
| 682 |
} |
| 683 |
|
| 684 |
static inline void tcg_gen_ld_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
| 685 |
{
|
| 686 |
tcg_gen_op3i(INDEX_op_ld_i64, ret, arg2, offset); |
| 687 |
} |
| 688 |
|
| 689 |
static inline void tcg_gen_st8_i64(TCGv arg1, TCGv arg2, |
| 690 |
tcg_target_long offset) |
| 691 |
{
|
| 692 |
tcg_gen_op3i(INDEX_op_st8_i64, arg1, arg2, offset); |
| 693 |
} |
| 694 |
|
| 695 |
static inline void tcg_gen_st16_i64(TCGv arg1, TCGv arg2, |
| 696 |
tcg_target_long offset) |
| 697 |
{
|
| 698 |
tcg_gen_op3i(INDEX_op_st16_i64, arg1, arg2, offset); |
| 699 |
} |
| 700 |
|
| 701 |
static inline void tcg_gen_st32_i64(TCGv arg1, TCGv arg2, |
| 702 |
tcg_target_long offset) |
| 703 |
{
|
| 704 |
tcg_gen_op3i(INDEX_op_st32_i64, arg1, arg2, offset); |
| 705 |
} |
| 706 |
|
| 707 |
static inline void tcg_gen_st_i64(TCGv arg1, TCGv arg2, tcg_target_long offset) |
| 708 |
{
|
| 709 |
tcg_gen_op3i(INDEX_op_st_i64, arg1, arg2, offset); |
| 710 |
} |
| 711 |
|
| 712 |
static inline void tcg_gen_add_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 713 |
{
|
| 714 |
tcg_gen_op3(INDEX_op_add_i64, ret, arg1, arg2); |
| 715 |
} |
| 716 |
|
| 717 |
static inline void tcg_gen_addi_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 718 |
{
|
| 719 |
tcg_gen_add_i64(ret, arg1, tcg_const_i64(arg2)); |
| 720 |
} |
| 721 |
|
| 722 |
static inline void tcg_gen_sub_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 723 |
{
|
| 724 |
tcg_gen_op3(INDEX_op_sub_i64, ret, arg1, arg2); |
| 725 |
} |
| 726 |
|
| 727 |
static inline void tcg_gen_subi_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 728 |
{
|
| 729 |
tcg_gen_sub_i64(ret, arg1, tcg_const_i64(arg2)); |
| 730 |
} |
| 731 |
|
| 732 |
static inline void tcg_gen_and_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 733 |
{
|
| 734 |
tcg_gen_op3(INDEX_op_and_i64, ret, arg1, arg2); |
| 735 |
} |
| 736 |
|
| 737 |
static inline void tcg_gen_andi_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 738 |
{
|
| 739 |
tcg_gen_and_i64(ret, arg1, tcg_const_i64(arg2)); |
| 740 |
} |
| 741 |
|
| 742 |
static inline void tcg_gen_or_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 743 |
{
|
| 744 |
tcg_gen_op3(INDEX_op_or_i64, ret, arg1, arg2); |
| 745 |
} |
| 746 |
|
| 747 |
static inline void tcg_gen_ori_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 748 |
{
|
| 749 |
tcg_gen_or_i64(ret, arg1, tcg_const_i64(arg2)); |
| 750 |
} |
| 751 |
|
| 752 |
static inline void tcg_gen_xor_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 753 |
{
|
| 754 |
tcg_gen_op3(INDEX_op_xor_i64, ret, arg1, arg2); |
| 755 |
} |
| 756 |
|
| 757 |
static inline void tcg_gen_xori_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 758 |
{
|
| 759 |
tcg_gen_xor_i64(ret, arg1, tcg_const_i64(arg2)); |
| 760 |
} |
| 761 |
|
| 762 |
static inline void tcg_gen_shl_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 763 |
{
|
| 764 |
tcg_gen_op3(INDEX_op_shl_i64, ret, arg1, arg2); |
| 765 |
} |
| 766 |
|
| 767 |
static inline void tcg_gen_shli_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 768 |
{
|
| 769 |
tcg_gen_shl_i64(ret, arg1, tcg_const_i64(arg2)); |
| 770 |
} |
| 771 |
|
| 772 |
static inline void tcg_gen_shr_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 773 |
{
|
| 774 |
tcg_gen_op3(INDEX_op_shr_i64, ret, arg1, arg2); |
| 775 |
} |
| 776 |
|
| 777 |
static inline void tcg_gen_shri_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 778 |
{
|
| 779 |
tcg_gen_shr_i64(ret, arg1, tcg_const_i64(arg2)); |
| 780 |
} |
| 781 |
|
| 782 |
static inline void tcg_gen_sar_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 783 |
{
|
| 784 |
tcg_gen_op3(INDEX_op_sar_i64, ret, arg1, arg2); |
| 785 |
} |
| 786 |
|
| 787 |
static inline void tcg_gen_sari_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 788 |
{
|
| 789 |
tcg_gen_sar_i64(ret, arg1, tcg_const_i64(arg2)); |
| 790 |
} |
| 791 |
|
| 792 |
static inline void tcg_gen_brcond_i64(int cond, TCGv arg1, TCGv arg2, |
| 793 |
int label_index)
|
| 794 |
{
|
| 795 |
tcg_gen_op4ii(INDEX_op_brcond_i64, arg1, arg2, cond, label_index); |
| 796 |
} |
| 797 |
|
| 798 |
static inline void tcg_gen_mul_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 799 |
{
|
| 800 |
tcg_gen_op3(INDEX_op_mul_i64, ret, arg1, arg2); |
| 801 |
} |
| 802 |
|
| 803 |
#ifdef TCG_TARGET_HAS_div_i64
|
| 804 |
static inline void tcg_gen_div_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 805 |
{
|
| 806 |
tcg_gen_op3(INDEX_op_div_i64, ret, arg1, arg2); |
| 807 |
} |
| 808 |
|
| 809 |
static inline void tcg_gen_rem_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 810 |
{
|
| 811 |
tcg_gen_op3(INDEX_op_rem_i64, ret, arg1, arg2); |
| 812 |
} |
| 813 |
|
| 814 |
static inline void tcg_gen_divu_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 815 |
{
|
| 816 |
tcg_gen_op3(INDEX_op_divu_i64, ret, arg1, arg2); |
| 817 |
} |
| 818 |
|
| 819 |
static inline void tcg_gen_remu_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 820 |
{
|
| 821 |
tcg_gen_op3(INDEX_op_remu_i64, ret, arg1, arg2); |
| 822 |
} |
| 823 |
#else
|
| 824 |
static inline void tcg_gen_div_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 825 |
{
|
| 826 |
TCGv t0; |
| 827 |
t0 = tcg_temp_new(TCG_TYPE_I64); |
| 828 |
tcg_gen_sari_i64(t0, arg1, 63);
|
| 829 |
tcg_gen_op5(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2); |
| 830 |
} |
| 831 |
|
| 832 |
static inline void tcg_gen_rem_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 833 |
{
|
| 834 |
TCGv t0; |
| 835 |
t0 = tcg_temp_new(TCG_TYPE_I64); |
| 836 |
tcg_gen_sari_i64(t0, arg1, 63);
|
| 837 |
tcg_gen_op5(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2); |
| 838 |
} |
| 839 |
|
| 840 |
static inline void tcg_gen_divu_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 841 |
{
|
| 842 |
TCGv t0; |
| 843 |
t0 = tcg_temp_new(TCG_TYPE_I64); |
| 844 |
tcg_gen_movi_i64(t0, 0);
|
| 845 |
tcg_gen_op5(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2); |
| 846 |
} |
| 847 |
|
| 848 |
static inline void tcg_gen_remu_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 849 |
{
|
| 850 |
TCGv t0; |
| 851 |
t0 = tcg_temp_new(TCG_TYPE_I64); |
| 852 |
tcg_gen_movi_i64(t0, 0);
|
| 853 |
tcg_gen_op5(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2); |
| 854 |
} |
| 855 |
#endif
|
| 856 |
|
| 857 |
#endif
|
| 858 |
|
| 859 |
/***************************************/
|
| 860 |
/* optional operations */
|
| 861 |
|
| 862 |
static inline void tcg_gen_ext8s_i32(TCGv ret, TCGv arg) |
| 863 |
{
|
| 864 |
#ifdef TCG_TARGET_HAS_ext8s_i32
|
| 865 |
tcg_gen_op2(INDEX_op_ext8s_i32, ret, arg); |
| 866 |
#else
|
| 867 |
tcg_gen_shli_i32(ret, arg, 24);
|
| 868 |
tcg_gen_sari_i32(ret, ret, 24);
|
| 869 |
#endif
|
| 870 |
} |
| 871 |
|
| 872 |
static inline void tcg_gen_ext16s_i32(TCGv ret, TCGv arg) |
| 873 |
{
|
| 874 |
#ifdef TCG_TARGET_HAS_ext16s_i32
|
| 875 |
tcg_gen_op2(INDEX_op_ext16s_i32, ret, arg); |
| 876 |
#else
|
| 877 |
tcg_gen_shli_i32(ret, arg, 16);
|
| 878 |
tcg_gen_sari_i32(ret, ret, 16);
|
| 879 |
#endif
|
| 880 |
} |
| 881 |
|
| 882 |
/* Note: we assume the two high bytes are set to zero */
|
| 883 |
static inline void tcg_gen_bswap16_i32(TCGv ret, TCGv arg) |
| 884 |
{
|
| 885 |
#ifdef TCG_TARGET_HAS_bswap16_i32
|
| 886 |
tcg_gen_op2(INDEX_op_bswap16_i32, ret, arg); |
| 887 |
#else
|
| 888 |
TCGv t0, t1; |
| 889 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
| 890 |
t1 = tcg_temp_new(TCG_TYPE_I32); |
| 891 |
|
| 892 |
tcg_gen_shri_i32(t0, arg, 8);
|
| 893 |
tcg_gen_andi_i32(t1, arg, 0x000000ff);
|
| 894 |
tcg_gen_shli_i32(t1, t1, 8);
|
| 895 |
tcg_gen_or_i32(ret, t0, t1); |
| 896 |
#endif
|
| 897 |
} |
| 898 |
|
| 899 |
static inline void tcg_gen_bswap_i32(TCGv ret, TCGv arg) |
| 900 |
{
|
| 901 |
#ifdef TCG_TARGET_HAS_bswap_i32
|
| 902 |
tcg_gen_op2(INDEX_op_bswap_i32, ret, arg); |
| 903 |
#else
|
| 904 |
TCGv t0, t1; |
| 905 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
| 906 |
t1 = tcg_temp_new(TCG_TYPE_I32); |
| 907 |
|
| 908 |
tcg_gen_shli_i32(t0, arg, 24);
|
| 909 |
|
| 910 |
tcg_gen_andi_i32(t1, arg, 0x0000ff00);
|
| 911 |
tcg_gen_shli_i32(t1, t1, 8);
|
| 912 |
tcg_gen_or_i32(t0, t0, t1); |
| 913 |
|
| 914 |
tcg_gen_shri_i32(t1, arg, 8);
|
| 915 |
tcg_gen_andi_i32(t1, t1, 0x0000ff00);
|
| 916 |
tcg_gen_or_i32(t0, t0, t1); |
| 917 |
|
| 918 |
tcg_gen_shri_i32(t1, arg, 24);
|
| 919 |
tcg_gen_or_i32(ret, t0, t1); |
| 920 |
#endif
|
| 921 |
} |
| 922 |
|
| 923 |
#if TCG_TARGET_REG_BITS == 32 |
| 924 |
static inline void tcg_gen_ext8s_i64(TCGv ret, TCGv arg) |
| 925 |
{
|
| 926 |
tcg_gen_ext8s_i32(ret, arg); |
| 927 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
| 928 |
} |
| 929 |
|
| 930 |
static inline void tcg_gen_ext16s_i64(TCGv ret, TCGv arg) |
| 931 |
{
|
| 932 |
tcg_gen_ext16s_i32(ret, arg); |
| 933 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
| 934 |
} |
| 935 |
|
| 936 |
static inline void tcg_gen_ext32s_i64(TCGv ret, TCGv arg) |
| 937 |
{
|
| 938 |
tcg_gen_mov_i32(ret, arg); |
| 939 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
| 940 |
} |
| 941 |
|
| 942 |
static inline void tcg_gen_trunc_i64_i32(TCGv ret, TCGv arg) |
| 943 |
{
|
| 944 |
tcg_gen_mov_i32(ret, arg); |
| 945 |
} |
| 946 |
|
| 947 |
static inline void tcg_gen_extu_i32_i64(TCGv ret, TCGv arg) |
| 948 |
{
|
| 949 |
tcg_gen_mov_i32(ret, arg); |
| 950 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
| 951 |
} |
| 952 |
|
| 953 |
static inline void tcg_gen_ext_i32_i64(TCGv ret, TCGv arg) |
| 954 |
{
|
| 955 |
tcg_gen_mov_i32(ret, arg); |
| 956 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
| 957 |
} |
| 958 |
|
| 959 |
static inline void tcg_gen_bswap_i64(TCGv ret, TCGv arg) |
| 960 |
{
|
| 961 |
TCGv t0, t1; |
| 962 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
| 963 |
t1 = tcg_temp_new(TCG_TYPE_I32); |
| 964 |
|
| 965 |
tcg_gen_bswap_i32(t0, arg); |
| 966 |
tcg_gen_bswap_i32(t1, TCGV_HIGH(arg)); |
| 967 |
tcg_gen_mov_i32(ret, t1); |
| 968 |
tcg_gen_mov_i32(TCGV_HIGH(ret), t0); |
| 969 |
} |
| 970 |
#else
|
| 971 |
|
| 972 |
static inline void tcg_gen_ext8s_i64(TCGv ret, TCGv arg) |
| 973 |
{
|
| 974 |
#ifdef TCG_TARGET_HAS_ext8s_i64
|
| 975 |
tcg_gen_op2(INDEX_op_ext8s_i64, ret, arg); |
| 976 |
#else
|
| 977 |
tcg_gen_shli_i64(ret, arg, 56);
|
| 978 |
tcg_gen_sari_i64(ret, ret, 56);
|
| 979 |
#endif
|
| 980 |
} |
| 981 |
|
| 982 |
static inline void tcg_gen_ext16s_i64(TCGv ret, TCGv arg) |
| 983 |
{
|
| 984 |
#ifdef TCG_TARGET_HAS_ext16s_i64
|
| 985 |
tcg_gen_op2(INDEX_op_ext16s_i64, ret, arg); |
| 986 |
#else
|
| 987 |
tcg_gen_shli_i64(ret, arg, 48);
|
| 988 |
tcg_gen_sari_i64(ret, ret, 48);
|
| 989 |
#endif
|
| 990 |
} |
| 991 |
|
| 992 |
static inline void tcg_gen_ext32s_i64(TCGv ret, TCGv arg) |
| 993 |
{
|
| 994 |
#ifdef TCG_TARGET_HAS_ext32s_i64
|
| 995 |
tcg_gen_op2(INDEX_op_ext32s_i64, ret, arg); |
| 996 |
#else
|
| 997 |
tcg_gen_shli_i64(ret, arg, 32);
|
| 998 |
tcg_gen_sari_i64(ret, ret, 32);
|
| 999 |
#endif
|
| 1000 |
} |
| 1001 |
|
| 1002 |
/* Note: we assume the target supports move between 32 and 64 bit
|
| 1003 |
registers. This will probably break MIPS64 targets. */
|
| 1004 |
static inline void tcg_gen_trunc_i64_i32(TCGv ret, TCGv arg) |
| 1005 |
{
|
| 1006 |
tcg_gen_mov_i32(ret, arg); |
| 1007 |
} |
| 1008 |
|
| 1009 |
/* Note: we assume the target supports move between 32 and 64 bit
|
| 1010 |
registers */
|
| 1011 |
static inline void tcg_gen_extu_i32_i64(TCGv ret, TCGv arg) |
| 1012 |
{
|
| 1013 |
tcg_gen_andi_i64(ret, arg, 0xffffffff);
|
| 1014 |
} |
| 1015 |
|
| 1016 |
/* Note: we assume the target supports move between 32 and 64 bit
|
| 1017 |
registers */
|
| 1018 |
static inline void tcg_gen_ext_i32_i64(TCGv ret, TCGv arg) |
| 1019 |
{
|
| 1020 |
tcg_gen_ext32s_i64(ret, arg); |
| 1021 |
} |
| 1022 |
|
| 1023 |
static inline void tcg_gen_bswap_i64(TCGv ret, TCGv arg) |
| 1024 |
{
|
| 1025 |
#ifdef TCG_TARGET_HAS_bswap_i64
|
| 1026 |
tcg_gen_op2(INDEX_op_bswap_i64, ret, arg); |
| 1027 |
#else
|
| 1028 |
TCGv t0, t1; |
| 1029 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
| 1030 |
t1 = tcg_temp_new(TCG_TYPE_I32); |
| 1031 |
|
| 1032 |
tcg_gen_shli_i64(t0, arg, 56);
|
| 1033 |
|
| 1034 |
tcg_gen_andi_i64(t1, arg, 0x0000ff00);
|
| 1035 |
tcg_gen_shli_i64(t1, t1, 40);
|
| 1036 |
tcg_gen_or_i64(t0, t0, t1); |
| 1037 |
|
| 1038 |
tcg_gen_andi_i64(t1, arg, 0x00ff0000);
|
| 1039 |
tcg_gen_shli_i64(t1, t1, 24);
|
| 1040 |
tcg_gen_or_i64(t0, t0, t1); |
| 1041 |
|
| 1042 |
tcg_gen_andi_i64(t1, arg, 0xff000000);
|
| 1043 |
tcg_gen_shli_i64(t1, t1, 8);
|
| 1044 |
tcg_gen_or_i64(t0, t0, t1); |
| 1045 |
|
| 1046 |
tcg_gen_shri_i64(t1, arg, 8);
|
| 1047 |
tcg_gen_andi_i64(t1, t1, 0xff000000);
|
| 1048 |
tcg_gen_or_i64(t0, t0, t1); |
| 1049 |
|
| 1050 |
tcg_gen_shri_i64(t1, arg, 24);
|
| 1051 |
tcg_gen_andi_i64(t1, t1, 0x00ff0000);
|
| 1052 |
tcg_gen_or_i64(t0, t0, t1); |
| 1053 |
|
| 1054 |
tcg_gen_shri_i64(t1, arg, 40);
|
| 1055 |
tcg_gen_andi_i64(t1, t1, 0x0000ff00);
|
| 1056 |
tcg_gen_or_i64(t0, t0, t1); |
| 1057 |
|
| 1058 |
tcg_gen_shri_i64(t1, arg, 56);
|
| 1059 |
tcg_gen_or_i64(ret, t0, t1); |
| 1060 |
#endif
|
| 1061 |
} |
| 1062 |
|
| 1063 |
#endif
|
| 1064 |
|
| 1065 |
|
| 1066 |
static inline void tcg_gen_discard_i32(TCGv arg) |
| 1067 |
{
|
| 1068 |
tcg_gen_op1(INDEX_op_discard, arg); |
| 1069 |
} |
| 1070 |
|
| 1071 |
#if TCG_TARGET_REG_BITS == 32 |
| 1072 |
static inline void tcg_gen_discard_i64(TCGv arg) |
| 1073 |
{
|
| 1074 |
tcg_gen_discard_i32(arg); |
| 1075 |
tcg_gen_discard_i32(TCGV_HIGH(arg)); |
| 1076 |
} |
| 1077 |
#else
|
| 1078 |
static inline void tcg_gen_discard_i64(TCGv arg) |
| 1079 |
{
|
| 1080 |
tcg_gen_op1(INDEX_op_discard, arg); |
| 1081 |
} |
| 1082 |
#endif
|
| 1083 |
|
| 1084 |
/***************************************/
|
| 1085 |
static inline void tcg_gen_macro_2(TCGv ret0, TCGv ret1, int macro_id) |
| 1086 |
{
|
| 1087 |
tcg_gen_op3i(INDEX_op_macro_2, ret0, ret1, macro_id); |
| 1088 |
} |
| 1089 |
|
| 1090 |
/***************************************/
|
| 1091 |
/* QEMU specific operations. Their type depend on the QEMU CPU
|
| 1092 |
type. */
|
| 1093 |
#ifndef TARGET_LONG_BITS
|
| 1094 |
#error must include QEMU headers
|
| 1095 |
#endif
|
| 1096 |
|
| 1097 |
static inline void tcg_gen_exit_tb(tcg_target_long val) |
| 1098 |
{
|
| 1099 |
tcg_gen_op1i(INDEX_op_exit_tb, val); |
| 1100 |
} |
| 1101 |
|
| 1102 |
static inline void tcg_gen_goto_tb(int idx) |
| 1103 |
{
|
| 1104 |
tcg_gen_op1i(INDEX_op_goto_tb, idx); |
| 1105 |
} |
| 1106 |
|
| 1107 |
#if TCG_TARGET_REG_BITS == 32 |
| 1108 |
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
| 1109 |
{
|
| 1110 |
#if TARGET_LONG_BITS == 32 |
| 1111 |
tcg_gen_op3i(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
| 1112 |
#else
|
| 1113 |
tcg_gen_op4i(INDEX_op_qemu_ld8u, ret, addr, TCGV_HIGH(addr), mem_index); |
| 1114 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
| 1115 |
#endif
|
| 1116 |
} |
| 1117 |
|
| 1118 |
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
| 1119 |
{
|
| 1120 |
#if TARGET_LONG_BITS == 32 |
| 1121 |
tcg_gen_op3i(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
| 1122 |
#else
|
| 1123 |
tcg_gen_op4i(INDEX_op_qemu_ld8s, ret, addr, TCGV_HIGH(addr), mem_index); |
| 1124 |
tcg_gen_ext8s_i32(TCGV_HIGH(ret), ret); |
| 1125 |
#endif
|
| 1126 |
} |
| 1127 |
|
| 1128 |
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
| 1129 |
{
|
| 1130 |
#if TARGET_LONG_BITS == 32 |
| 1131 |
tcg_gen_op3i(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
| 1132 |
#else
|
| 1133 |
tcg_gen_op4i(INDEX_op_qemu_ld16u, ret, addr, TCGV_HIGH(addr), mem_index); |
| 1134 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
| 1135 |
#endif
|
| 1136 |
} |
| 1137 |
|
| 1138 |
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
| 1139 |
{
|
| 1140 |
#if TARGET_LONG_BITS == 32 |
| 1141 |
tcg_gen_op3i(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
| 1142 |
#else
|
| 1143 |
tcg_gen_op4i(INDEX_op_qemu_ld16s, ret, addr, TCGV_HIGH(addr), mem_index); |
| 1144 |
tcg_gen_ext16s_i32(TCGV_HIGH(ret), ret); |
| 1145 |
#endif
|
| 1146 |
} |
| 1147 |
|
| 1148 |
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
| 1149 |
{
|
| 1150 |
#if TARGET_LONG_BITS == 32 |
| 1151 |
tcg_gen_op3i(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
| 1152 |
#else
|
| 1153 |
tcg_gen_op4i(INDEX_op_qemu_ld32u, ret, addr, TCGV_HIGH(addr), mem_index); |
| 1154 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
| 1155 |
#endif
|
| 1156 |
} |
| 1157 |
|
| 1158 |
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
| 1159 |
{
|
| 1160 |
#if TARGET_LONG_BITS == 32 |
| 1161 |
tcg_gen_op3i(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
| 1162 |
#else
|
| 1163 |
tcg_gen_op4i(INDEX_op_qemu_ld32u, ret, addr, TCGV_HIGH(addr), mem_index); |
| 1164 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
| 1165 |
#endif
|
| 1166 |
} |
| 1167 |
|
| 1168 |
static inline void tcg_gen_qemu_ld64(TCGv ret, TCGv addr, int mem_index) |
| 1169 |
{
|
| 1170 |
#if TARGET_LONG_BITS == 32 |
| 1171 |
tcg_gen_op4i(INDEX_op_qemu_ld64, ret, TCGV_HIGH(ret), addr, mem_index); |
| 1172 |
#else
|
| 1173 |
tcg_gen_op5i(INDEX_op_qemu_ld64, ret, TCGV_HIGH(ret), |
| 1174 |
addr, TCGV_HIGH(addr), mem_index); |
| 1175 |
#endif
|
| 1176 |
} |
| 1177 |
|
| 1178 |
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
| 1179 |
{
|
| 1180 |
#if TARGET_LONG_BITS == 32 |
| 1181 |
tcg_gen_op3i(INDEX_op_qemu_st8, arg, addr, mem_index); |
| 1182 |
#else
|
| 1183 |
tcg_gen_op4i(INDEX_op_qemu_st8, arg, addr, TCGV_HIGH(addr), mem_index); |
| 1184 |
#endif
|
| 1185 |
} |
| 1186 |
|
| 1187 |
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
| 1188 |
{
|
| 1189 |
#if TARGET_LONG_BITS == 32 |
| 1190 |
tcg_gen_op3i(INDEX_op_qemu_st16, arg, addr, mem_index); |
| 1191 |
#else
|
| 1192 |
tcg_gen_op4i(INDEX_op_qemu_st16, arg, addr, TCGV_HIGH(addr), mem_index); |
| 1193 |
#endif
|
| 1194 |
} |
| 1195 |
|
| 1196 |
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
| 1197 |
{
|
| 1198 |
#if TARGET_LONG_BITS == 32 |
| 1199 |
tcg_gen_op3i(INDEX_op_qemu_st32, arg, addr, mem_index); |
| 1200 |
#else
|
| 1201 |
tcg_gen_op4i(INDEX_op_qemu_st32, arg, addr, TCGV_HIGH(addr), mem_index); |
| 1202 |
#endif
|
| 1203 |
} |
| 1204 |
|
| 1205 |
static inline void tcg_gen_qemu_st64(TCGv arg, TCGv addr, int mem_index) |
| 1206 |
{
|
| 1207 |
#if TARGET_LONG_BITS == 32 |
| 1208 |
tcg_gen_op4i(INDEX_op_qemu_st64, arg, TCGV_HIGH(arg), addr, mem_index); |
| 1209 |
#else
|
| 1210 |
tcg_gen_op5i(INDEX_op_qemu_st64, arg, TCGV_HIGH(arg), |
| 1211 |
addr, TCGV_HIGH(addr), mem_index); |
| 1212 |
#endif
|
| 1213 |
} |
| 1214 |
|
| 1215 |
#else /* TCG_TARGET_REG_BITS == 32 */ |
| 1216 |
|
| 1217 |
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
| 1218 |
{
|
| 1219 |
tcg_gen_op3i(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
| 1220 |
} |
| 1221 |
|
| 1222 |
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
| 1223 |
{
|
| 1224 |
tcg_gen_op3i(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
| 1225 |
} |
| 1226 |
|
| 1227 |
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
| 1228 |
{
|
| 1229 |
tcg_gen_op3i(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
| 1230 |
} |
| 1231 |
|
| 1232 |
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
| 1233 |
{
|
| 1234 |
tcg_gen_op3i(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
| 1235 |
} |
| 1236 |
|
| 1237 |
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
| 1238 |
{
|
| 1239 |
tcg_gen_op3i(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
| 1240 |
} |
| 1241 |
|
| 1242 |
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
| 1243 |
{
|
| 1244 |
tcg_gen_op3i(INDEX_op_qemu_ld32s, ret, addr, mem_index); |
| 1245 |
} |
| 1246 |
|
| 1247 |
static inline void tcg_gen_qemu_ld64(TCGv ret, TCGv addr, int mem_index) |
| 1248 |
{
|
| 1249 |
tcg_gen_op3i(INDEX_op_qemu_ld64, ret, addr, mem_index); |
| 1250 |
} |
| 1251 |
|
| 1252 |
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
| 1253 |
{
|
| 1254 |
tcg_gen_op3i(INDEX_op_qemu_st8, arg, addr, mem_index); |
| 1255 |
} |
| 1256 |
|
| 1257 |
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
| 1258 |
{
|
| 1259 |
tcg_gen_op3i(INDEX_op_qemu_st16, arg, addr, mem_index); |
| 1260 |
} |
| 1261 |
|
| 1262 |
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
| 1263 |
{
|
| 1264 |
tcg_gen_op3i(INDEX_op_qemu_st32, arg, addr, mem_index); |
| 1265 |
} |
| 1266 |
|
| 1267 |
static inline void tcg_gen_qemu_st64(TCGv arg, TCGv addr, int mem_index) |
| 1268 |
{
|
| 1269 |
tcg_gen_op3i(INDEX_op_qemu_st64, arg, addr, mem_index); |
| 1270 |
} |
| 1271 |
|
| 1272 |
#endif /* TCG_TARGET_REG_BITS != 32 */ |