Revision 601d70b9 target-arm/translate.c
b/target-arm/translate.c | ||
---|---|---|
2877 | 2877 |
tmp = load_cpu_field(vfp.xregs[rn]); |
2878 | 2878 |
break; |
2879 | 2879 |
case ARM_VFP_FPSCR: |
2880 |
if (rd == 15) {
|
|
2880 |
if (rd == 15) {
|
|
2881 | 2881 |
tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); |
2882 | 2882 |
tcg_gen_andi_i32(tmp, tmp, 0xf0000000); |
2883 | 2883 |
} else { |
... | ... | |
6887 | 6887 |
|
6888 | 6888 |
if (!(arm_feature(env, ARM_FEATURE_THUMB2) |
6889 | 6889 |
|| arm_feature (env, ARM_FEATURE_M))) { |
6890 |
/* Thumb-1 cores may need to tread bl and blx as a pair of
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|
6890 |
/* Thumb-1 cores may need to treat bl and blx as a pair of
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|
6891 | 6891 |
16-bit instructions to get correct prefetch abort behavior. */ |
6892 | 6892 |
insn = insn_hw1; |
6893 | 6893 |
if ((insn & (1 << 12)) == 0) { |
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