root / hw / gusemu_hal.c @ 6059631c
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/*
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* GUSEMU32 - bus interface part
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*
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* Copyright (C) 2000-2007 Tibor "TS" Schütz
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/*
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* TODO: check mixer: see 7.20 of sdk for panning pos (applies to all gus models?)?
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*/
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#include "gustate.h" |
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#include "gusemu.h" |
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#define GUSregb(position) (* (gusptr+(position)))
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#define GUSregw(position) (*(GUSword *) (gusptr+(position)))
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#define GUSregd(position) (*(GUSdword *)(gusptr+(position)))
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/* size given in bytes */
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unsigned int gus_read(GUSEmuState * state, int port, int size) |
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{
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int value_read = 0; |
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GUSbyte *gusptr; |
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gusptr = state->gusdatapos; |
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GUSregd(portaccesses)++; |
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|
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switch (port & 0xff0f) |
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{
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/* MixerCtrlReg (read not supported on GUS classic) */
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/* case 0x200: return GUSregb(MixerCtrlReg2x0); */
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case 0x206: /* IRQstatReg / SB2x6IRQ */ |
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/* adlib/sb bits set in port handlers */
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/* timer/voice bits set in gus_irqgen() */
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/* dma bit set in gus_dma_transferdata */
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/* midi not implemented yet */
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return GUSregb(IRQStatReg2x6);
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/* case 0x308: */ /* AdLib388 */ |
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case 0x208: |
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if (GUSregb(GUS45TimerCtrl) & 1) |
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return GUSregb(TimerStatus2x8);
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return GUSregb(AdLibStatus2x8); /* AdLibStatus */ |
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case 0x309: /* AdLib389 */ |
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case 0x209: |
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return GUSregb(AdLibData2x9); /* AdLibData */ |
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case 0x20A: |
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return GUSregb(AdLibCommand2xA); /* AdLib2x8_2xA */ |
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|
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#if 0
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case 0x20B: /* GUS hidden registers (read not supported on GUS classic) */
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switch (GUSregb(RegCtrl_2xF) & 0x07)
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{
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case 0: /* IRQ/DMA select */
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if (GUSregb(MixerCtrlReg2x0) & 0x40)
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return GUSregb(IRQ_2xB); /* control register select bit */
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else
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return GUSregb(DMA_2xB);
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/* case 1-5: */ /* general purpose emulation regs */
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/* return ... */ /* + status reset reg (write only) */
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case 6:
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return GUSregb(Jumper_2xB); /* Joystick/MIDI enable (JumperReg) */
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default:;
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}
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break;
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#endif
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|
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case 0x20C: /* SB2xCd */ |
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value_read = GUSregb(SB2xCd); |
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if (GUSregb(StatRead_2xF) & 0x20) |
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GUSregb(SB2xCd) ^= 0x80; /* toggle MSB on read */ |
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return value_read;
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/* case 0x20D: */ /* SB2xD is write only -> 2xE writes to it*/ |
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case 0x20E: |
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if (GUSregb(RegCtrl_2xF) & 0x80) /* 2xE read IRQ enabled? */ |
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{
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GUSregb(StatRead_2xF) |= 0x80;
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GUS_irqrequest(state, state->gusirq, 1);
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} |
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return GUSregb(SB2xE); /* SB2xE */ |
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case 0x20F: /* StatRead_2xF */ |
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/*set/clear fixed bits */
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/*value_read = (GUSregb(StatRead_2xF) & 0xf9)|1; */ /*(LSB not set on GUS classic!)*/ |
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value_read = (GUSregb(StatRead_2xF) & 0xf9);
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if (GUSregb(MixerCtrlReg2x0) & 0x08) |
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value_read |= 2; /* DMA/IRQ enabled flag */ |
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return value_read;
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/* case 0x300: */ /* MIDI (not implemented) */ |
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/* case 0x301: */ /* MIDI (not implemented) */ |
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case 0x302: |
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return GUSregb(VoiceSelReg3x2); /* VoiceSelReg */ |
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case 0x303: |
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return GUSregb(FunkSelReg3x3); /* FunkSelReg */ |
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case 0x304: /* DataRegLoByte3x4 + DataRegWord3x4 */ |
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case 0x305: /* DataRegHiByte3x5 */ |
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switch (GUSregb(FunkSelReg3x3))
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{
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/* common functions */
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case 0x41: /* DramDMAContrReg */ |
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value_read = GUSregb(GUS41DMACtrl); /* &0xfb */
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GUSregb(GUS41DMACtrl) &= 0xbb;
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if (state->gusdma >= 4) |
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value_read |= 0x04;
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if (GUSregb(IRQStatReg2x6) & 0x80) |
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{
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value_read |= 0x40;
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GUSregb(IRQStatReg2x6) &= 0x7f;
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if (!GUSregb(IRQStatReg2x6))
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GUS_irqclear(state, state->gusirq); |
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} |
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return (GUSbyte) value_read;
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/* DramDMAmemPosReg */
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/* case 0x42: value_read=GUSregw(GUS42DMAStart); break;*/
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/* 43h+44h write only */
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case 0x45: |
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return GUSregb(GUS45TimerCtrl); /* TimerCtrlReg */ |
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/* 46h+47h write only */
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/* 48h: samp freq - write only */
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case 0x49: |
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return GUSregb(GUS49SampCtrl) & 0xbf; /* SampCtrlReg */ |
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/* case 4bh: */ /* joystick trim not supported */ |
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/* case 0x4c: return GUSregb(GUS4cReset); */ /* GUSreset: write only*/ |
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/* voice specific functions */
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case 0x80: |
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case 0x81: |
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case 0x82: |
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case 0x83: |
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case 0x84: |
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case 0x85: |
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case 0x86: |
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case 0x87: |
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case 0x88: |
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case 0x89: |
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case 0x8a: |
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case 0x8b: |
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case 0x8c: |
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case 0x8d: |
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{
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int offset = 2 * (GUSregb(FunkSelReg3x3) & 0x0f); |
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offset += ((int) GUSregb(VoiceSelReg3x2) & 0x1f) << 5; /* = Voice*32 + Funktion*2 */ |
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value_read = GUSregw(offset); |
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} |
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break;
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/* voice unspecific functions */
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case 0x8e: /* NumVoice */ |
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return GUSregb(NumVoices);
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case 0x8f: /* irqstatreg */ |
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/* (pseudo IRQ-FIFO is processed during a gus_write(0x3X3,0x8f)) */
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return GUSregb(SynVoiceIRQ8f);
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default:
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return 0xffff; |
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} |
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if (size == 1) |
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{
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if ((port & 0xff0f) == 0x305) |
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value_read = value_read >> 8;
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value_read &= 0xff;
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} |
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return (GUSword) value_read;
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/* case 0x306: */ /* Mixer/Version info */ |
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/* return 0xff; */ /* Pre 3.6 boards, ICS mixer NOT present */ |
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case 0x307: /* DRAMaccess */ |
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{
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GUSbyte *adr; |
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adr = state->himemaddr + (GUSregd(GUSDRAMPOS24bit) & 0xfffff);
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return *adr;
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} |
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default:;
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} |
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return 0xffff; |
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} |
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void gus_write(GUSEmuState * state, int port, int size, unsigned int data) |
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{
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GUSbyte *gusptr; |
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gusptr = state->gusdatapos; |
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GUSregd(portaccesses)++; |
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switch (port & 0xff0f) |
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{
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case 0x200: /* MixerCtrlReg */ |
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GUSregb(MixerCtrlReg2x0) = (GUSbyte) data; |
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break;
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case 0x206: /* IRQstatReg / SB2x6IRQ */ |
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if (GUSregb(GUS45TimerCtrl) & 0x20) /* SB IRQ enabled? -> set 2x6IRQ bit */ |
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{
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GUSregb(TimerStatus2x8) |= 0x08;
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GUSregb(IRQStatReg2x6) = 0x10;
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GUS_irqrequest(state, state->gusirq, 1);
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} |
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break;
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case 0x308: /* AdLib 388h */ |
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case 0x208: /* AdLibCommandReg */ |
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GUSregb(AdLibCommand2xA) = (GUSbyte) data; |
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break;
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case 0x309: /* AdLib 389h */ |
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case 0x209: /* AdLibDataReg */ |
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if ((GUSregb(AdLibCommand2xA) == 0x04) && (!(GUSregb(GUS45TimerCtrl) & 1))) /* GUS auto timer mode enabled? */ |
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{
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if (data & 0x80) |
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GUSregb(TimerStatus2x8) &= 0x1f; /* AdLib IRQ reset? -> clear maskable adl. timer int regs */ |
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else
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GUSregb(TimerDataReg2x9) = (GUSbyte) data; |
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} |
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else
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{
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GUSregb(AdLibData2x9) = (GUSbyte) data; |
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if (GUSregb(GUS45TimerCtrl) & 0x02) |
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{
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GUSregb(TimerStatus2x8) |= 0x01;
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GUSregb(IRQStatReg2x6) = 0x10;
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GUS_irqrequest(state, state->gusirq, 1);
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} |
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} |
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break;
|
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case 0x20A: |
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GUSregb(AdLibStatus2x8) = (GUSbyte) data; |
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break; /* AdLibStatus2x8 */ |
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case 0x20B: /* GUS hidden registers */ |
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switch (GUSregb(RegCtrl_2xF) & 0x7) |
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{
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case 0: |
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if (GUSregb(MixerCtrlReg2x0) & 0x40) |
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GUSregb(IRQ_2xB) = (GUSbyte) data; /* control register select bit */
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else
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GUSregb(DMA_2xB) = (GUSbyte) data; |
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break;
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/* case 1-4: general purpose emulation regs */
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case 5: /* clear stat reg 2xF */ |
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GUSregb(StatRead_2xF) = 0; /* ToDo: is this identical with GUS classic? */ |
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if (!GUSregb(IRQStatReg2x6))
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GUS_irqclear(state, state->gusirq); |
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break;
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case 6: /* Jumper reg (Joystick/MIDI enable) */ |
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GUSregb(Jumper_2xB) = (GUSbyte) data; |
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break;
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default:;
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} |
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break;
|
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case 0x20C: /* SB2xCd */ |
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if (GUSregb(GUS45TimerCtrl) & 0x20) |
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{
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GUSregb(TimerStatus2x8) |= 0x10; /* SB IRQ enabled? -> set 2xCIRQ bit */ |
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GUSregb(IRQStatReg2x6) = 0x10;
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GUS_irqrequest(state, state->gusirq, 1);
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} |
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case 0x20D: /* SB2xCd no IRQ */ |
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GUSregb(SB2xCd) = (GUSbyte) data; |
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break;
|
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case 0x20E: /* SB2xE */ |
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GUSregb(SB2xE) = (GUSbyte) data; |
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break;
|
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case 0x20F: |
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GUSregb(RegCtrl_2xF) = (GUSbyte) data; |
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break; /* CtrlReg2xF */ |
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case 0x302: /* VoiceSelReg */ |
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GUSregb(VoiceSelReg3x2) = (GUSbyte) data; |
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break;
|
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case 0x303: /* FunkSelReg */ |
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GUSregb(FunkSelReg3x3) = (GUSbyte) data; |
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if ((GUSbyte) data == 0x8f) /* set irqstatreg, get voicereg and clear IRQ */ |
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{
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int voice;
|
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if (GUSregd(voicewavetableirq)) /* WavetableIRQ */ |
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{
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for (voice = 0; voice < 31; voice++) |
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{
|
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if (GUSregd(voicewavetableirq) & (1 << voice)) |
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{
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GUSregd(voicewavetableirq) ^= (1 << voice); /* clear IRQ bit */ |
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GUSregb(voice << 5) &= 0x7f; /* clear voice reg irq bit */ |
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if (!GUSregd(voicewavetableirq))
|
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GUSregb(IRQStatReg2x6) &= 0xdf;
|
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if (!GUSregb(IRQStatReg2x6))
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GUS_irqclear(state, state->gusirq); |
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GUSregb(SynVoiceIRQ8f) = voice | 0x60; /* (bit==0 => IRQ wartend) */ |
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return;
|
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} |
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} |
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} |
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else if (GUSregd(voicevolrampirq)) /* VolRamp IRQ */ |
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{
|
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for (voice = 0; voice < 31; voice++) |
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{
|
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if (GUSregd(voicevolrampirq) & (1 << voice)) |
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{
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GUSregd(voicevolrampirq) ^= (1 << voice); /* clear IRQ bit */ |
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GUSregb((voice << 5) + VSRVolRampControl) &= 0x7f; /* clear voice volume reg irq bit */ |
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if (!GUSregd(voicevolrampirq))
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GUSregb(IRQStatReg2x6) &= 0xbf;
|
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if (!GUSregb(IRQStatReg2x6))
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GUS_irqclear(state, state->gusirq); |
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GUSregb(SynVoiceIRQ8f) = voice | 0x80; /* (bit==0 => IRQ wartend) */ |
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return;
|
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} |
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} |
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} |
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GUSregb(SynVoiceIRQ8f) = 0xe8; /* kein IRQ wartet */ |
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} |
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break;
|
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case 0x304: |
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case 0x305: |
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{
|
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GUSword writedata = (GUSword) data; |
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GUSword readmask = 0x0000;
|
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if (size == 1) |
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{
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readmask = 0xff00;
|
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writedata &= 0xff;
|
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if ((port & 0xff0f) == 0x305) |
| 327 |
{
|
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writedata = (GUSword) (writedata << 8);
|
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readmask = 0x00ff;
|
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} |
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} |
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switch (GUSregb(FunkSelReg3x3))
|
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{
|
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/* voice specific functions */
|
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case 0x00: |
| 336 |
case 0x01: |
| 337 |
case 0x02: |
| 338 |
case 0x03: |
| 339 |
case 0x04: |
| 340 |
case 0x05: |
| 341 |
case 0x06: |
| 342 |
case 0x07: |
| 343 |
case 0x08: |
| 344 |
case 0x09: |
| 345 |
case 0x0a: |
| 346 |
case 0x0b: |
| 347 |
case 0x0c: |
| 348 |
case 0x0d: |
| 349 |
{
|
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int offset;
|
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if (!(GUSregb(GUS4cReset) & 0x01)) |
| 352 |
break; /* reset flag active? */ |
| 353 |
offset = 2 * (GUSregb(FunkSelReg3x3) & 0x0f); |
| 354 |
offset += (GUSregb(VoiceSelReg3x2) & 0x1f) << 5; /* = Voice*32 + Funktion*2 */ |
| 355 |
GUSregw(offset) = (GUSword) ((GUSregw(offset) & readmask) | writedata); |
| 356 |
} |
| 357 |
break;
|
| 358 |
/* voice unspecific functions */
|
| 359 |
case 0x0e: /* NumVoices */ |
| 360 |
GUSregb(NumVoices) = (GUSbyte) data; |
| 361 |
break;
|
| 362 |
/* case 0x0f: */ /* read only */ |
| 363 |
/* common functions */
|
| 364 |
case 0x41: /* DramDMAContrReg */ |
| 365 |
GUSregb(GUS41DMACtrl) = (GUSbyte) data; |
| 366 |
if (data & 0x01) |
| 367 |
GUS_dmarequest(state); |
| 368 |
break;
|
| 369 |
case 0x42: /* DramDMAmemPosReg */ |
| 370 |
GUSregw(GUS42DMAStart) = (GUSregw(GUS42DMAStart) & readmask) | writedata; |
| 371 |
GUSregb(GUS50DMAHigh) &= 0xf; /* compatibility stuff... */ |
| 372 |
break;
|
| 373 |
case 0x43: /* DRAMaddrLo */ |
| 374 |
GUSregd(GUSDRAMPOS24bit) = |
| 375 |
(GUSregd(GUSDRAMPOS24bit) & (readmask | 0xff0000)) | writedata;
|
| 376 |
break;
|
| 377 |
case 0x44: /* DRAMaddrHi */ |
| 378 |
GUSregd(GUSDRAMPOS24bit) = |
| 379 |
(GUSregd(GUSDRAMPOS24bit) & 0xffff) | ((data & 0x0f) << 16); |
| 380 |
break;
|
| 381 |
case 0x45: /* TCtrlReg */ |
| 382 |
GUSregb(GUS45TimerCtrl) = (GUSbyte) data; |
| 383 |
if (!(data & 0x20)) |
| 384 |
GUSregb(TimerStatus2x8) &= 0xe7; /* sb IRQ dis? -> clear 2x8/2xC sb IRQ flags */ |
| 385 |
if (!(data & 0x02)) |
| 386 |
GUSregb(TimerStatus2x8) &= 0xfe; /* adlib data IRQ dis? -> clear 2x8 adlib IRQ flag */ |
| 387 |
if (!(GUSregb(TimerStatus2x8) & 0x19)) |
| 388 |
GUSregb(IRQStatReg2x6) &= 0xef; /* 0xe6; $$clear IRQ if both IRQ bits are inactive or cleared */ |
| 389 |
/* catch up delayed timer IRQs: */
|
| 390 |
if ((GUSregw(TimerIRQs) > 1) && (GUSregb(TimerDataReg2x9) & 3)) |
| 391 |
{
|
| 392 |
if (GUSregb(TimerDataReg2x9) & 1) /* start timer 1 (80us decrement rate) */ |
| 393 |
{
|
| 394 |
if (!(GUSregb(TimerDataReg2x9) & 0x40)) |
| 395 |
GUSregb(TimerStatus2x8) |= 0xc0; /* maskable bits */ |
| 396 |
if (data & 4) /* timer1 irq enable */ |
| 397 |
{
|
| 398 |
GUSregb(TimerStatus2x8) |= 4; /* nonmaskable bit */ |
| 399 |
GUSregb(IRQStatReg2x6) |= 4; /* timer 1 irq pending */ |
| 400 |
} |
| 401 |
} |
| 402 |
if (GUSregb(TimerDataReg2x9) & 2) /* start timer 2 (320us decrement rate) */ |
| 403 |
{
|
| 404 |
if (!(GUSregb(TimerDataReg2x9) & 0x20)) |
| 405 |
GUSregb(TimerStatus2x8) |= 0xa0; /* maskable bits */ |
| 406 |
if (data & 8) /* timer2 irq enable */ |
| 407 |
{
|
| 408 |
GUSregb(TimerStatus2x8) |= 2; /* nonmaskable bit */ |
| 409 |
GUSregb(IRQStatReg2x6) |= 8; /* timer 2 irq pending */ |
| 410 |
} |
| 411 |
} |
| 412 |
GUSregw(TimerIRQs)--; |
| 413 |
if (GUSregw(BusyTimerIRQs) > 1) |
| 414 |
GUSregw(BusyTimerIRQs)--; |
| 415 |
else
|
| 416 |
GUSregw(BusyTimerIRQs) = |
| 417 |
GUS_irqrequest(state, state->gusirq, GUSregw(TimerIRQs)); |
| 418 |
} |
| 419 |
else
|
| 420 |
GUSregw(TimerIRQs) = 0;
|
| 421 |
|
| 422 |
if (!(data & 0x04)) |
| 423 |
{
|
| 424 |
GUSregb(TimerStatus2x8) &= 0xfb; /* clear non-maskable timer1 bit */ |
| 425 |
GUSregb(IRQStatReg2x6) &= 0xfb;
|
| 426 |
} |
| 427 |
if (!(data & 0x08)) |
| 428 |
{
|
| 429 |
GUSregb(TimerStatus2x8) &= 0xfd; /* clear non-maskable timer2 bit */ |
| 430 |
GUSregb(IRQStatReg2x6) &= 0xf7;
|
| 431 |
} |
| 432 |
if (!GUSregb(IRQStatReg2x6))
|
| 433 |
GUS_irqclear(state, state->gusirq); |
| 434 |
break;
|
| 435 |
case 0x46: /* Counter1 */ |
| 436 |
GUSregb(GUS46Counter1) = (GUSbyte) data; |
| 437 |
break;
|
| 438 |
case 0x47: /* Counter2 */ |
| 439 |
GUSregb(GUS47Counter2) = (GUSbyte) data; |
| 440 |
break;
|
| 441 |
/* case 0x48: */ /* sampling freq reg not emulated (same as interwave) */ |
| 442 |
case 0x49: /* SampCtrlReg */ |
| 443 |
GUSregb(GUS49SampCtrl) = (GUSbyte) data; |
| 444 |
break;
|
| 445 |
/* case 0x4b: */ /* joystick trim not emulated */ |
| 446 |
case 0x4c: /* GUSreset */ |
| 447 |
GUSregb(GUS4cReset) = (GUSbyte) data; |
| 448 |
if (!(GUSregb(GUS4cReset) & 1)) /* reset... */ |
| 449 |
{
|
| 450 |
GUSregd(voicewavetableirq) = 0;
|
| 451 |
GUSregd(voicevolrampirq) = 0;
|
| 452 |
GUSregw(TimerIRQs) = 0;
|
| 453 |
GUSregw(BusyTimerIRQs) = 0;
|
| 454 |
GUSregb(NumVoices) = 0xcd;
|
| 455 |
GUSregb(IRQStatReg2x6) = 0;
|
| 456 |
GUSregb(TimerStatus2x8) = 0;
|
| 457 |
GUSregb(AdLibData2x9) = 0;
|
| 458 |
GUSregb(TimerDataReg2x9) = 0;
|
| 459 |
GUSregb(GUS41DMACtrl) = 0;
|
| 460 |
GUSregb(GUS45TimerCtrl) = 0;
|
| 461 |
GUSregb(GUS49SampCtrl) = 0;
|
| 462 |
GUSregb(GUS4cReset) &= 0xf9; /* clear IRQ and DAC enable bits */ |
| 463 |
GUS_irqclear(state, state->gusirq); |
| 464 |
} |
| 465 |
/* IRQ enable bit checked elsewhere */
|
| 466 |
/* EnableDAC bit may be used by external callers */
|
| 467 |
break;
|
| 468 |
} |
| 469 |
} |
| 470 |
break;
|
| 471 |
case 0x307: /* DRAMaccess */ |
| 472 |
{
|
| 473 |
GUSbyte *adr; |
| 474 |
adr = state->himemaddr + (GUSregd(GUSDRAMPOS24bit) & 0xfffff);
|
| 475 |
*adr = (GUSbyte) data; |
| 476 |
} |
| 477 |
break;
|
| 478 |
} |
| 479 |
} |
| 480 |
|
| 481 |
/* Attention when breaking up a single DMA transfer to multiple ones:
|
| 482 |
* it may lead to multiple terminal count interrupts and broken transfers:
|
| 483 |
*
|
| 484 |
* 1. Whenever you transfer a piece of data, the gusemu callback is invoked
|
| 485 |
* 2. The callback may generate a TC irq (if the register was set up to do so)
|
| 486 |
* 3. The irq may result in the program using the GUS to reprogram the GUS
|
| 487 |
*
|
| 488 |
* Some programs also decide to upload by just checking if TC occurs
|
| 489 |
* (via interrupt or a cleared GUS dma flag)
|
| 490 |
* and then start the next transfer, without checking DMA state
|
| 491 |
*
|
| 492 |
* Thus: Always make sure to set the TC flag correctly!
|
| 493 |
*
|
| 494 |
* Note that the genuine GUS had a granularity of 16 bytes/words for low/high DMA
|
| 495 |
* while later cards had atomic granularity provided by an additional GUS50DMAHigh register
|
| 496 |
* GUSemu also uses this register to support byte-granular transfers for better compatibility
|
| 497 |
* with emulators other than GUSemu32
|
| 498 |
*/
|
| 499 |
|
| 500 |
void gus_dma_transferdata(GUSEmuState * state, char *dma_addr, unsigned int count, int TC) |
| 501 |
{
|
| 502 |
/* this function gets called by the callback function as soon as a DMA transfer is about to start
|
| 503 |
* dma_addr is a translated address within accessible memory, not the physical one,
|
| 504 |
* count is (real dma count register)+1
|
| 505 |
* note that the amount of bytes transfered is fully determined by values in the DMA registers
|
| 506 |
* do not forget to update DMA states after transferring the entire block:
|
| 507 |
* DREQ cleared & TC asserted after the _whole_ transfer */
|
| 508 |
|
| 509 |
char *srcaddr;
|
| 510 |
char *destaddr;
|
| 511 |
char msbmask = 0; |
| 512 |
GUSbyte *gusptr; |
| 513 |
gusptr = state->gusdatapos; |
| 514 |
|
| 515 |
srcaddr = dma_addr; /* system memory address */
|
| 516 |
{
|
| 517 |
int offset = (GUSregw(GUS42DMAStart) << 4) + (GUSregb(GUS50DMAHigh) & 0xf); |
| 518 |
if (state->gusdma >= 4) |
| 519 |
offset = (offset & 0xc0000) + (2 * (offset & 0x1fff0)); /* 16 bit address translation */ |
| 520 |
destaddr = (char *) state->himemaddr + offset; /* wavetable RAM adress */ |
| 521 |
} |
| 522 |
|
| 523 |
GUSregw(GUS42DMAStart) += (GUSword) (count >> 4); /* ToDo: add 16bit GUS page limit? */ |
| 524 |
GUSregb(GUS50DMAHigh) = (GUSbyte) ((count + GUSregb(GUS50DMAHigh)) & 0xf); /* ToDo: add 16bit GUS page limit? */ |
| 525 |
|
| 526 |
if (GUSregb(GUS41DMACtrl) & 0x02) /* direction, 0 := sysram->gusram */ |
| 527 |
{
|
| 528 |
char *tmpaddr = destaddr;
|
| 529 |
destaddr = srcaddr; |
| 530 |
srcaddr = tmpaddr; |
| 531 |
} |
| 532 |
|
| 533 |
if ((GUSregb(GUS41DMACtrl) & 0x80) && (!(GUSregb(GUS41DMACtrl) & 0x02))) |
| 534 |
msbmask = (const char) 0x80; /* invert MSB */ |
| 535 |
for (; count > 0; count--) |
| 536 |
{
|
| 537 |
if (GUSregb(GUS41DMACtrl) & 0x40) |
| 538 |
*(destaddr++) = *(srcaddr++); /* 16 bit lobyte */
|
| 539 |
else
|
| 540 |
*(destaddr++) = (msbmask ^ (*(srcaddr++))); /* 8 bit */
|
| 541 |
if (state->gusdma >= 4) |
| 542 |
*(destaddr++) = (msbmask ^ (*(srcaddr++))); /* 16 bit hibyte */
|
| 543 |
} |
| 544 |
|
| 545 |
if (TC)
|
| 546 |
{
|
| 547 |
(GUSregb(GUS41DMACtrl)) &= 0xfe; /* clear DMA request bit */ |
| 548 |
if (GUSregb(GUS41DMACtrl) & 0x20) /* DMA terminal count IRQ */ |
| 549 |
{
|
| 550 |
GUSregb(IRQStatReg2x6) |= 0x80;
|
| 551 |
GUS_irqrequest(state, state->gusirq, 1);
|
| 552 |
} |
| 553 |
} |
| 554 |
} |